From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::242; helo=mail-lf0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org Received: from mail-lf0-x242.google.com (mail-lf0-x242.google.com [IPv6:2a00:1450:4010:c07::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 275B52034CF8C for ; Wed, 25 Oct 2017 18:16:25 -0700 (PDT) Received: by mail-lf0-x242.google.com with SMTP id g70so1940880lfl.3 for ; Wed, 25 Oct 2017 18:20:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MGckb2m6lPxbCuQdM1slIPel35gTqteWDvbWhUgZDR4=; b=0DaOALR4FFTzs+GIjfgcV5R1GCia+Qrsp2fYQTt/SD6p1d54XqPjU64Naopu0DVYEb 8kL1JaWkI3lE5iamw7v2JVxeV49o4mxQlsXwZHQHfqU1iD4If9Ex6eYZyBr2F05sS85r 2imxCLnZxSNl8uefFSYOvF+7H0XkZK/XzkgQrUWiFK/mIYFnngifxKZcpB3inef03YoM Ph31OQ6WwD3QwNes/ic2UdXZXZ7O95RhvOrBx8oa7O8IhGcbDY0ynXjCO7RYPCKY1qPl DNzdFRrlVpGlI5mKslpFs266Z95iV7dkFuMN71P4O+UK9GZkVf5P72EGZ9ln2yy+4jkM UIEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MGckb2m6lPxbCuQdM1slIPel35gTqteWDvbWhUgZDR4=; b=Ig9IKq+fygeOVJ4iwkx/fC7y7uDPctm9SPZv8LBd2Y7bX14w4isagoIMbyPqRZyT8v tjct5S8DEt+dngh17HawtHpVUhAd3gSa8XgEj/OUQhdspVUC1N128+ilYSSAtTr0vd4X QMFU+yRiq5SSfw3IHEZM1ympDzMstvbW+Bt0hzrLDHjmcyR4rjkHODIbYywClGALwG4z dW4suafuHA2168qU8jbYxu1Fd9sjXWk/ztakvZJf6rfQiwm0EUW9ZTt375L96cnSdmq0 ZCpsZKRrlYxi7wS3VsXk/0211ATVsaPKH7rmu5audq2ENzE7oIFWqT2pdcKQPhPLRni8 XHxQ== X-Gm-Message-State: AMCzsaUe1h4YV2XQVn1Ax81oNUCYrInBLhrJs+Xf07CYjZZ7O0DiG62F 7DTbk7tDuSZe4tICb3jpBpfoYqs6Exk= X-Google-Smtp-Source: ABhQp+TeNHm4beifMGrA5fqwu1i3sy+cS0VRKhGcmPos7+tWh4GutCuhu/VNanLTJ1jbktGSZ/LD5w== X-Received: by 10.25.148.216 with SMTP id o85mr7266715lfk.190.1508980808811; Wed, 25 Oct 2017 18:20:08 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id h26sm1053428lja.69.2017.10.25.18.20.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 25 Oct 2017 18:20:07 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com, jinghua@marvell.com, mw@semihalf.com, jsd@semihalf.com Date: Thu, 26 Oct 2017 03:19:36 +0200 Message-Id: <1508980777-29006-10-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508980777-29006-1-git-send-email-mw@semihalf.com> References: <1508980777-29006-1-git-send-email-mw@semihalf.com> Subject: [platforms: PATCH 09/10] Marvell/Drivers: XenonDxe: Fix base clock frequency X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Oct 2017 01:16:25 -0000 Incorrectly the clock divisor was calculated relatively to 255MHz instead of actual 400MHz. Fix this. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c b/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c index ccbf355..0b9328b 100644 --- a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c +++ b/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c @@ -16,6 +16,7 @@ **/ #include "SdMmcPciHcDxe.h" +#include "XenonSdhci.h" /** Dump the content of SD/MMC host controller's Capability Register. @@ -703,9 +704,8 @@ SdMmcHcClockSupply ( // // Calculate a divisor for SD clock frequency // - ASSERT (Capability.BaseClkFreq != 0); - BaseClkFreq = Capability.BaseClkFreq; + BaseClkFreq = XENON_MMC_MAX_CLK / 1000 / 1000; if (ClockFreq == 0) { return EFI_INVALID_PARAMETER; } -- 2.7.4