From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::241; helo=mail-lf0-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org Received: from mail-lf0-x241.google.com (mail-lf0-x241.google.com [IPv6:2a00:1450:4010:c07::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3AB872034CF8C for ; Wed, 25 Oct 2017 18:16:26 -0700 (PDT) Received: by mail-lf0-x241.google.com with SMTP id 90so1911569lfs.13 for ; Wed, 25 Oct 2017 18:20:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=su8EVPW+PVySzpBE/RQBDhevNsuQL9eBl4d1g2nHt/8=; b=p7tc8uayo2sVwyJhOM8cZlWqvsowzga8UH781YZhuBzKXjoTNhyje3L4ldNS3ky+HK o+uFDBaoh7HXOY2ULdmZRRzjyfZfCqWg7IrcBEPuhQUaNT7E49MXZ9vY1ChAPOZFr3dc pPKiWXr58DzSmJd4xeeGJHe1hN2rjV5Hi1Zanw5PFxhbV70KRTHFZmyUc9iLrjJrieFF fDNgQKRI3ys2jn+CHC2k2KRtOS3xBtYyTmy2e5hF5jB4hUdc728gNiXJLIhvJxfnNZ1A DhT4+nEthcwprnCUO6eoPr/hpfeuotyiQtEyyOevTs8qRU2qHPd37CT3yWrKX4IE8HNB NE9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=su8EVPW+PVySzpBE/RQBDhevNsuQL9eBl4d1g2nHt/8=; b=Dee5wfr5oFyPexMNYCpbyxS0lsIkxMW5TcIvQ794F3NyxMN96Ua2VkbEfzECVPPZ11 5UYPJ0BQsAPTuCqgKLJVC5m+zCaJFtkyQsuM8o0gWS0JiHBBO0Xpq0rC3LYwzDs7r30s NNEbhY4pmO+hxJwGsdYRR0ubxXyJ8UBVCQtEQ44+7kzxkSHGoQ3CbA7vLofXFO5B8d/l 4JK7EXnEIlYDa2FC7mgqmr2ZX/JXamJi7YlnwuF+Flgr2bHG5g6v8x+mjUba/uQ+tR9c YRXd/3+tTsRT1zqFmUmccY7zWvqr+2xvcUn+uSiraXm4E6UlICd49/Dr6z+pIHSOzdCe FSvQ== X-Gm-Message-State: AMCzsaWdx4KwTacGCjsnqfhcTtp0HyhhV7HhbUfgdG0dU2THnw4wnPSC 3Saz7WfHnmIUBYYAL5w+ts9wd5846qI= X-Google-Smtp-Source: ABhQp+QpZ/Bkc6jDGzyGW8/MUgwMZGB+gpvIklkAoSzLmsFQk7Cj3EmTSAPVM9uOJADdGtV+rXkm1Q== X-Received: by 10.25.202.82 with SMTP id h18mr7919870lfj.54.1508980810031; Wed, 25 Oct 2017 18:20:10 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id h26sm1053428lja.69.2017.10.25.18.20.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 25 Oct 2017 18:20:09 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com, jinghua@marvell.com, mw@semihalf.com, jsd@semihalf.com Date: Thu, 26 Oct 2017 03:19:37 +0200 Message-Id: <1508980777-29006-11-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508980777-29006-1-git-send-email-mw@semihalf.com> References: <1508980777-29006-1-git-send-email-mw@semihalf.com> Subject: [platforms: PATCH 10/10] Marvell/Drivers: XenonDxe: Do not modify FIFO default values X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Oct 2017 01:16:26 -0000 Changing controller's FIFO default values is not necessary and possibly can cause instabilities, when using some devices. Disable the modification and rely on initial settings. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Platform/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/Platform/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c b/Platform/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c index 31f207e..6bbe5bc 100755 --- a/Platform/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c +++ b/Platform/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c @@ -44,20 +44,6 @@ XenonReadVersion ( SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CTRL_VER, TRUE, SDHC_REG_SIZE_2B, ControllerVersion); } -STATIC -VOID -XenonSetFifo ( - IN EFI_PCI_IO_PROTOCOL *PciIo - ) -{ - UINTN Data; - - // Set FIFO_RTC, FIFO_WTC, FIFO_CS and FIFO_PDLVMC - Data = SDHC_SLOT_FIFO_DEFAULT_CONFIG; - - SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SLOT_FIFO_CTRL, FALSE, SDHC_REG_SIZE_4B, &Data); -} - // Auto Clock Gating STATIC VOID @@ -634,8 +620,6 @@ XenonInit ( // Read XENON version XenonReadVersion (PciIo, &Private->ControllerVersion); - XenonSetFifo (PciIo); - // Disable auto clock generator XenonSetAcg (PciIo, FALSE); -- 2.7.4