From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::241; helo=mail-lf0-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org Received: from mail-lf0-x241.google.com (mail-lf0-x241.google.com [IPv6:2a00:1450:4010:c07::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C2B452034A88D for ; Thu, 26 Oct 2017 18:10:55 -0700 (PDT) Received: by mail-lf0-x241.google.com with SMTP id 90so5655294lfs.13 for ; Thu, 26 Oct 2017 18:14:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=A7zc2/u0Y4h9ChbtWDS94GyHyj90ZIKnWA4DhvOjBBw=; b=fHIs1tvnEYx2oqp2qnyYjc276ulStxfJuku7usuri1fHCGCzZ/YnQSA6xFTS1ZBxf+ TnL8qNrhxk/7Lj8TvduAwzBE6u9fnKd4jNlE4+6yFb8msn1AyjEj1+yQ2iHPTMDBQ8Jf bnWVFyg8Gnf4ttIx5rHPWT98UFV5qiQ3N0dTVAbR4CWL+7D0rE1gkWXRkJlhOsSytBl9 VUhfv8OmH0+OV05mMe5iyiL70krywQPjg6ZNE524r5c5f9zPVSNGtBuyAweHS/oOOayn x8mOi3Ajuue2vCpjohjVXBLKJWfQFNvt6KCM9eWFiAQboaRTLzm+lVxbbYNoScz4eSmS w6AA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=A7zc2/u0Y4h9ChbtWDS94GyHyj90ZIKnWA4DhvOjBBw=; b=BORh191uphbXM/FA/+ostkdGtTO05i+jttWghHnBPwXQLmcu+PtDdzkGJVl0ejH7sE bHlyUiHbNn0Heux1Y6YKsuTcYO7wtZgM0D9AX40aR6nfv8kybK9GFgRZVWzyugYqlD0d q5gqiU8jEdfCUSFZewADPwEQHPw9vgjkD2XP4sSgrrnB2493aS+N4rkCDIgrONSi+yms hfXe42lRSECwPpwc+VgiYFkp5NcBbiorUq8WOzGPE4FGISSzZKJlDbRAJnKKENrE0RtR OW4lzpUM41HO1w3zMU0G3XWqpvOt/j28teAwQhFvn4qv5pjHzNgIkWi1xsUufRmUhxJ4 x6gQ== X-Gm-Message-State: AMCzsaVdw0LWXHPB/PrV8w7sVbmnCsp/UOkhm2sntG41u8a1W46btwas n9zkZlW5rImKxhlInoMnIKzNp0uBqAc= X-Google-Smtp-Source: ABhQp+QpU+/gSSio0T4m+rBzp5R5tg/uaskQ/IQ4EVXZadRROghhY2j+NaAOE9U8r331Zed6diwElA== X-Received: by 10.25.18.169 with SMTP id 41mr7111662lfs.166.1509066880680; Thu, 26 Oct 2017 18:14:40 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id m9sm1675702ljb.61.2017.10.26.18.14.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 26 Oct 2017 18:14:39 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com, jinghua@marvell.com, mw@semihalf.com, jsd@semihalf.com Date: Fri, 27 Oct 2017 03:13:52 +0200 Message-Id: <1509066832-5285-11-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509066832-5285-1-git-send-email-mw@semihalf.com> References: <1509066832-5285-1-git-send-email-mw@semihalf.com> Subject: [platforms: PATCH v2 10/10] Marvell/Drivers: XenonDxe: Do not modify FIFO default values X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2017 01:10:56 -0000 Changing controller's FIFO default values is not necessary and possibly can cause instabilities, when using some devices. Disable the modification and rely on initial settings. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/Platform/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c b/Platform/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c index 31f207e..6bbe5bc 100755 --- a/Platform/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c +++ b/Platform/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c @@ -44,20 +44,6 @@ XenonReadVersion ( SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CTRL_VER, TRUE, SDHC_REG_SIZE_2B, ControllerVersion); } -STATIC -VOID -XenonSetFifo ( - IN EFI_PCI_IO_PROTOCOL *PciIo - ) -{ - UINTN Data; - - // Set FIFO_RTC, FIFO_WTC, FIFO_CS and FIFO_PDLVMC - Data = SDHC_SLOT_FIFO_DEFAULT_CONFIG; - - SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SLOT_FIFO_CTRL, FALSE, SDHC_REG_SIZE_4B, &Data); -} - // Auto Clock Gating STATIC VOID @@ -634,8 +620,6 @@ XenonInit ( // Read XENON version XenonReadVersion (PciIo, &Private->ControllerVersion); - XenonSetFifo (PciIo); - // Disable auto clock generator XenonSetAcg (PciIo, FALSE); -- 2.7.4