From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::242; helo=mail-lf0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org Received: from mail-lf0-x242.google.com (mail-lf0-x242.google.com [IPv6:2a00:1450:4010:c07::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4509821F3B3ED for ; Fri, 27 Oct 2017 09:29:02 -0700 (PDT) Received: by mail-lf0-x242.google.com with SMTP id a132so8025513lfa.7 for ; Fri, 27 Oct 2017 09:32:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=A7zc2/u0Y4h9ChbtWDS94GyHyj90ZIKnWA4DhvOjBBw=; b=McN2ofe38Dpwhyb5ZzlqbGaGLGnikjI1ysL0UT3/IUsdQ3gHiZDsqNcaoUgUBLSQ3c n3FSl24vPN+Bw2ChsNydga72L9hs0PG4f+2v9Ai2u273tvqJOFPuVB59KF507FnCRRfV HXAqAm9nH66j62ZlBvRreS6ZBMW5PuGPjLRffstMh5tT2NV6uoOOc4ui3aza1UDUJqTv tYbHjMTVfPPt9wS2nfJ6fP85TZuSdKYVQkkm6qY0we0YJEim9q9Sj02Roj85qNAtpt7f 7xUZdhRo9LXlfODLWvVAK5YeuSpEpcaD/l/Jzh9H8JjbzAWFvOtB5sqtBXp9O5dr39Mm 6gVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=A7zc2/u0Y4h9ChbtWDS94GyHyj90ZIKnWA4DhvOjBBw=; b=ehmBDNa7r9uPk+QnGlg7Ne6eRt34n+UykqaFRTiDo8oNAYAZMjh3y0Rw5HHF+3seLx feGuzYz+0SFe6nI6uSS/i+7Mk/cZBuEMHLWMZc3P8ncLCaMame7JlfQYPF7njRppCR3U ZXKcVPo/ovWPEBSh3utkoa6N7kK0lzOev7pyLyRKyC2mkI88zFddkcLWojtZn3cJb0q1 OLmNFxYOMYOxPNDaOxkJa0C1ZrO62ny+Y5dvhc3FccWLrvsWkav2bvbtR9WCkFxW4ohj /nv9p9TVLv0Ad6/m91SmPTqMapR4F5w4Z2wd2/+aXugJBhstjNDKKJFudz/B6i0lPA8Y 40Wg== X-Gm-Message-State: AMCzsaVmfu077+JVQzxasfHsDERPjSLGibAVtYKpk8fp/RVg0Td33k2b TwCmRTKsjWgjiKOZlnsuQ5Vi2Yz++5o= X-Google-Smtp-Source: ABhQp+RT5BDNjL2zqQ2chDXd8ra5gYL2whznKNN1gsB+Efr5M9/xlQiL7TimJ1bAGdGXlnktGYg4rA== X-Received: by 10.46.64.82 with SMTP id n79mr451457lja.129.1509121967795; Fri, 27 Oct 2017 09:32:47 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id h3sm1569222lfj.26.2017.10.27.09.32.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 27 Oct 2017 09:32:47 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com, jinghua@marvell.com, mw@semihalf.com, jsd@semihalf.com Date: Fri, 27 Oct 2017 18:31:53 +0200 Message-Id: <1509121913-12937-11-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509121913-12937-1-git-send-email-mw@semihalf.com> References: <1509121913-12937-1-git-send-email-mw@semihalf.com> Subject: [platforms: PATCH v3 10/10] Marvell/Drivers: XenonDxe: Do not modify FIFO default values X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2017 16:29:02 -0000 Changing controller's FIFO default values is not necessary and possibly can cause instabilities, when using some devices. Disable the modification and rely on initial settings. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/Platform/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c b/Platform/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c index 31f207e..6bbe5bc 100755 --- a/Platform/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c +++ b/Platform/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c @@ -44,20 +44,6 @@ XenonReadVersion ( SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CTRL_VER, TRUE, SDHC_REG_SIZE_2B, ControllerVersion); } -STATIC -VOID -XenonSetFifo ( - IN EFI_PCI_IO_PROTOCOL *PciIo - ) -{ - UINTN Data; - - // Set FIFO_RTC, FIFO_WTC, FIFO_CS and FIFO_PDLVMC - Data = SDHC_SLOT_FIFO_DEFAULT_CONFIG; - - SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SLOT_FIFO_CTRL, FALSE, SDHC_REG_SIZE_4B, &Data); -} - // Auto Clock Gating STATIC VOID @@ -634,8 +620,6 @@ XenonInit ( // Read XENON version XenonReadVersion (PciIo, &Private->ControllerVersion); - XenonSetFifo (PciIo); - // Disable auto clock generator XenonSetAcg (PciIo, FALSE); -- 2.7.4