From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c00::242; helo=mail-pf0-x242.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf0-x242.google.com (mail-pf0-x242.google.com [IPv6:2607:f8b0:400e:c00::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C8FD22034D819 for ; Tue, 7 Nov 2017 03:02:11 -0800 (PST) Received: by mail-pf0-x242.google.com with SMTP id n14so10063753pfh.8 for ; Tue, 07 Nov 2017 03:06:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=qqI9DuQfSjQ8o410tHBKah+jfjC7FL8yRPmmLVponbM=; b=h5tPMvbt53yUnEhJ7CDzrpod74hXpCsJO80rETDTzLbVvjJj1pDu9XH2B0ceM4QKNX u3DFibGJoSuLQaRNLG417wwbzlNTph5Z7QZgoUsX/paXI6eE44p+gZg+tkyMK1D9hnOl akbaa3SIvtC9lhWPIRtiQu0ZuoyjUWxLPL5wU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=qqI9DuQfSjQ8o410tHBKah+jfjC7FL8yRPmmLVponbM=; b=l3Iy+cz7Dk3SCYjraDKBXbATjg5WXD59mP16YJ8/15/ZhPHcVW6McDYpOWOSfnAzMk YpogUefdfNKc4RUQhwJIZQu9hidvylovuhVThNwcviHNxd1Q+nEiO046cJ1BvLGpsFwN GlktbGbvLpI6gYbEcRdeonpaIGsFAzFxlRpj2ltcMeh6/efSjQOs7Qb/TfIRMCLJ2oll Tapva+6T0BRGwl9mU1itboJjPHbBkYuiwGLTVzqLSWzCpr9zOMS5MkMD8brzRjAF9M3l MVEmxbBAvhyirr3lox36sNh4EVjK8qIKXbeUji9EYvOqvGi1Tv2FUKaeYethBYJCrRMU Lstw== X-Gm-Message-State: AMCzsaX6bxjQohstCxZESpJVMvRDRYHaaS+dCoPfY7rVhc35jHIUFqGj wXMt1qL369+U4oThrGuHiaXVQMTUkwc= X-Google-Smtp-Source: ABhQp+Sr1ZjNWcb4VaULgEJLeF6ACYzlyG1QJ3gGMSOyL/f/XolUeH5M7s86NL5LIjZ8pu6wdFkimg== X-Received: by 10.84.198.131 with SMTP id p3mr17835368pld.245.1510052770649; Tue, 07 Nov 2017 03:06:10 -0800 (PST) Received: from szxbz956.huaweiobz.com ([45.56.152.90]) by smtp.gmail.com with ESMTPSA id t63sm2786605pgc.19.2017.11.07.03.06.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 07 Nov 2017 03:06:10 -0800 (PST) From: Heyi Guo To: linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org Cc: Peicong Li , Heyi Guo , Leif Lindholm , Ard Biesheuvel Date: Tue, 7 Nov 2017 19:05:48 +0800 Message-Id: <1510052748-5564-1-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 2.7.2.windows.1 Subject: [RFC] ArmPkg/ArmMmuLib: Add new attribute WRITE_BACK_NONSHARE X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 07 Nov 2017 11:02:11 -0000 From: Peicong Li Flash region needs to be set as cacheable (write back) to increase performance, if PEI is still XIP on flash or DXE FV is decompressed from flash FV. However some ARM platforms do not support to set flash as inner shareable since flash is not normal DDR memory and it will not respond to cache snoop request, which will causes system hang after MMU is enabled. So we need a new ARM memory region attribute WRITE_BACK_NONSHARE for flash region on these platforms specifically. This attribute will set the region as write back but not inner shared. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Peicong Li Signed-off-by: Heyi Guo Cc: Leif Lindholm Cc: Ard Biesheuvel --- ArmPkg/Include/Library/ArmLib.h | 2 ++ ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h index 24ffe9f..e43e375 100644 --- a/ArmPkg/Include/Library/ArmLib.h +++ b/ArmPkg/Include/Library/ArmLib.h @@ -39,6 +39,8 @@ typedef enum { ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0, ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED, + ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHARE, + ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHARE, ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK, ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK, ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH, diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c index 8bd1c6f..cc10143 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -35,6 +35,10 @@ ArmMemoryAttributeToPageAttribute ( ) { switch (Attributes) { + case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHARE: + case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHARE: + return TT_ATTR_INDX_MEMORY_WRITE_BACK; + case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK: case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK: return TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE; -- 2.7.2.windows.1