From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c00::244; helo=mail-pf0-x244.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf0-x244.google.com (mail-pf0-x244.google.com [IPv6:2607:f8b0:400e:c00::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6B0B52034D81F for ; Tue, 7 Nov 2017 04:53:20 -0800 (PST) Received: by mail-pf0-x244.google.com with SMTP id n14so10265516pfh.8 for ; Tue, 07 Nov 2017 04:57:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jMLjzoyB3STdAP43jPlJEyrXUZGpLiAe1HH07HDbIHA=; b=GZKPcNDWoDZP0Yblv21wgp+dhN4zfH2cvLmWct7bnPexmJxixakqB1xGaZbAaZu1Cm k4NebWbycR4LeROU2JWh//gdDEz597lit+sD3GKezxjendILRiBH8SXiWPHw5cU9mgEL xTPIUVav1+Y5TllzxNOzegfqjHN0kh2ZLiTqM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jMLjzoyB3STdAP43jPlJEyrXUZGpLiAe1HH07HDbIHA=; b=DMgFPfcUgPWkNkK4ulwiRzwWxdienkGvo+U0AQkVwwGpZf/vPFDpuCXe5OzagPo/0t C7ZjcmBc+Vl+jRWRkU5Lci5JaCm30/2Zv1r6gxGRX6e37KIK2WL1idHOqcf13eAhq/VI GMXckP8Tt5gaz1MWKgn3atvdqT7uN6p4Zmjf0oO0/+xVbA5c+1BCoIQycjmLNi20TjuS qeFoN6rJq6il/cPHAhy2shM2SMpqmm4UrfPGMvwDJKYMs6hQ67G3NgRLZMsd7FacXQz5 UqHN8oDha7bS6+37RgQJ8YJtjBGAeEfabT2daRQ9Y5pN+qd32iEBWQj8gqSaBDHjBM6y Gblg== X-Gm-Message-State: AMCzsaWg9hEeNeLZKNAMq8muv5LmqCKnQfm0R8K6ryJm2Y4E72ytw+pt UN1GtzTLVVxvwXr+XoIAewgiXg== X-Google-Smtp-Source: ABhQp+RzWnS8BL97PXSwo70hlg5ZwBjW3ecZSPcRUaAZhd2MPaVmOR1yd1eYtCDxkmbMoZD370Nutw== X-Received: by 10.101.97.81 with SMTP id o17mr18260017pgv.363.1510059439729; Tue, 07 Nov 2017 04:57:19 -0800 (PST) Received: from szxbz956.huaweiobz.com ([45.56.152.90]) by smtp.gmail.com with ESMTPSA id 66sm2700731pgh.31.2017.11.07.04.57.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 07 Nov 2017 04:57:19 -0800 (PST) From: Heyi Guo To: linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, Peicong Li , Heyi Guo Date: Tue, 7 Nov 2017 20:56:51 +0800 Message-Id: <1510059411-6608-2-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 2.7.2.windows.1 In-Reply-To: <1510059411-6608-1-git-send-email-heyi.guo@linaro.org> References: <1510059411-6608-1-git-send-email-heyi.guo@linaro.org> Subject: [PATCH] ArmPkg/ArmMmuLib: Add new attribute WRITE_BACK_NONSHAREABLE X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 07 Nov 2017 12:53:20 -0000 From: Peicong Li Flash region needs to be set as cacheable (write back) to increase performance, if PEI is still XIP on flash or DXE FV is decompressed from flash FV. However some ARM platforms do not support to set flash as inner shareable since flash is not normal DDR memory and it will not respond to cache snoop request, which will causes system hang after MMU is enabled. So we need a new ARM memory region attribute WRITE_BACK_NONSHAREABLE for flash region on these platforms specifically. This attribute will set the region as write back but not inner shared. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Peicong Li Signed-off-by: Heyi Guo Cc: Leif Lindholm Cc: Ard Biesheuvel --- ArmPkg/Include/Library/ArmLib.h | 7 +++++++ ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 4 ++++ 2 files changed, 11 insertions(+) diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h index 24ffe9f..38199be 100644 --- a/ArmPkg/Include/Library/ArmLib.h +++ b/ArmPkg/Include/Library/ArmLib.h @@ -41,6 +41,13 @@ typedef enum { ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED, ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK, ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK, + // On some platforms, memory mapped flash region is designed as not supporting + // shareable attribute, so WRITE_BACK_NONSHAREABLE is added for such special + // need. + // Do NOT use below two attributes if you are not sure. + ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE, + ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE, + ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH, ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH, ARM_MEMORY_REGION_ATTRIBUTE_DEVICE, diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c index 8bd1c6f..4b62ecb 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -35,6 +35,10 @@ ArmMemoryAttributeToPageAttribute ( ) { switch (Attributes) { + case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE: + case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE: + return TT_ATTR_INDX_MEMORY_WRITE_BACK; + case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK: case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK: return TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE; -- 2.7.2.windows.1