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* [PATCH edk2-platforms] [PATCH v3 0/9] Platform/NXP
@ 2017-11-27 10:51 Meenakshi Aggarwal
  2017-11-27 10:51 ` [PATCH edk2-platforms] [PATCH v3 1/9] Platform/NXP: Add support for Big Endian Mmio APIs Meenakshi Aggarwal
                   ` (9 more replies)
  0 siblings, 10 replies; 25+ messages in thread
From: Meenakshi Aggarwal @ 2017-11-27 10:51 UTC (permalink / raw)
  To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel

v3:
Added patch-prefix

v2:
1. Incorporated styling comments
2. Removed/Rewrite function referred from linux
3. Created DS1307 Library under Silicon/Maxim and make it i2c driver based.
4. Created i2c driver

Meenakshi Aggarwal (9):
  Platform/NXP: Add support for Big Endian Mmio APIs
  Platform/NXP : Add support for Watchdog driver
  SocLib : Add support for initialization of peripherals
  Platform/NXP : Add support for DUART library
  Platform/NXP: Add support for I2c driver
  Silicon/Maxim : Add support for DS1307 RTC library
  Platform/NXP: Add support for ArmPlatformLib
  Compilation : Add the fdf, dsc and dec files.
  Build : Add build script and environment script

 Platform/NXP/Drivers/I2cDxe/I2cDxe.c               | 728 +++++++++++++++++++++
 Platform/NXP/Drivers/I2cDxe/I2cDxe.h               |  64 ++
 Platform/NXP/Drivers/I2cDxe/I2cDxe.inf             |  57 ++
 Platform/NXP/Drivers/WatchDog/WatchDog.c           | 421 ++++++++++++
 Platform/NXP/Drivers/WatchDog/WatchDog.h           |  37 ++
 Platform/NXP/Drivers/WatchDog/WatchDogDxe.inf      |  47 ++
 Platform/NXP/Env.cshrc                             |  77 +++
 Platform/NXP/Include/Bitops.h                      | 179 +++++
 Platform/NXP/Include/Library/BeIoLib.h             | 332 ++++++++++
 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec       |  29 +
 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc       |  77 +++
 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf       | 281 ++++++++
 .../Library/PlatformLib/ArmPlatformLib.c           | 105 +++
 .../Library/PlatformLib/ArmPlatformLib.inf         |  70 ++
 .../Library/PlatformLib/NxpQoriqLsHelper.S         |  38 ++
 .../Library/PlatformLib/NxpQoriqLsMem.c            | 184 ++++++
 Platform/NXP/Library/BeIoLib/BeIoLib.c             | 400 +++++++++++
 Platform/NXP/Library/BeIoLib/BeIoLib.inf           |  31 +
 Platform/NXP/Library/DUartPortLib/DUart.h          | 128 ++++
 Platform/NXP/Library/DUartPortLib/DUartPortLib.c   | 331 ++++++++++
 Platform/NXP/Library/DUartPortLib/DUartPortLib.inf |  39 ++
 Platform/NXP/NxpQoriqLs.dec                        | 248 +++++++
 Platform/NXP/NxpQoriqLs.dsc                        | 453 +++++++++++++
 Platform/NXP/Readme.md                             |  15 +
 Platform/NXP/build.sh                              | 103 +++
 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h     |  59 ++
 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c  | 327 +++++++++
 .../Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec    |  26 +
 .../Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf    |  45 ++
 Silicon/NXP/Chassis/Chassis.c                      | 413 ++++++++++++
 Silicon/NXP/Chassis/Chassis.h                      | 144 ++++
 Silicon/NXP/Chassis/Chassis2/Chassis2.dec          |  19 +
 Silicon/NXP/Chassis/Chassis2/SerDes.h              |  69 ++
 Silicon/NXP/Chassis/Chassis2/Soc.c                 | 145 ++++
 Silicon/NXP/Chassis/Chassis2/Soc.h                 | 376 +++++++++++
 Silicon/NXP/Chassis/LS1043aSocLib.inf              |  47 ++
 Silicon/NXP/Chassis/SerDes.c                       | 254 +++++++
 Silicon/NXP/LS1043A/Include/SocSerDes.h            |  55 ++
 Silicon/NXP/LS1043A/LS1043A.dec                    |  22 +
 Silicon/NXP/LS1043A/LS1043A.dsc                    |  82 +++
 40 files changed, 6557 insertions(+)
 create mode 100644 Platform/NXP/Drivers/I2cDxe/I2cDxe.c
 create mode 100644 Platform/NXP/Drivers/I2cDxe/I2cDxe.h
 create mode 100644 Platform/NXP/Drivers/I2cDxe/I2cDxe.inf
 create mode 100644 Platform/NXP/Drivers/WatchDog/WatchDog.c
 create mode 100644 Platform/NXP/Drivers/WatchDog/WatchDog.h
 create mode 100644 Platform/NXP/Drivers/WatchDog/WatchDogDxe.inf
 create mode 100755 Platform/NXP/Env.cshrc
 create mode 100644 Platform/NXP/Include/Bitops.h
 create mode 100644 Platform/NXP/Include/Library/BeIoLib.h
 create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec
 create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
 create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
 create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
 create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
 create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
 create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
 create mode 100644 Platform/NXP/Library/BeIoLib/BeIoLib.c
 create mode 100644 Platform/NXP/Library/BeIoLib/BeIoLib.inf
 create mode 100644 Platform/NXP/Library/DUartPortLib/DUart.h
 create mode 100644 Platform/NXP/Library/DUartPortLib/DUartPortLib.c
 create mode 100644 Platform/NXP/Library/DUartPortLib/DUartPortLib.inf
 create mode 100644 Platform/NXP/NxpQoriqLs.dec
 create mode 100644 Platform/NXP/NxpQoriqLs.dsc
 create mode 100644 Platform/NXP/Readme.md
 create mode 100755 Platform/NXP/build.sh
 create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h
 create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
 create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
 create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
 create mode 100644 Silicon/NXP/Chassis/Chassis.c
 create mode 100644 Silicon/NXP/Chassis/Chassis.h
 create mode 100644 Silicon/NXP/Chassis/Chassis2/Chassis2.dec
 create mode 100644 Silicon/NXP/Chassis/Chassis2/SerDes.h
 create mode 100644 Silicon/NXP/Chassis/Chassis2/Soc.c
 create mode 100644 Silicon/NXP/Chassis/Chassis2/Soc.h
 create mode 100644 Silicon/NXP/Chassis/LS1043aSocLib.inf
 create mode 100644 Silicon/NXP/Chassis/SerDes.c
 create mode 100644 Silicon/NXP/LS1043A/Include/SocSerDes.h
 create mode 100644 Silicon/NXP/LS1043A/LS1043A.dec
 create mode 100644 Silicon/NXP/LS1043A/LS1043A.dsc

v1:
 Following patches will add support of NXP SoCs in edk2-platforms.
 
 Our directory structure will be:
 
 edk2-platforms/
 |-- Platform
 |   |-- NXP
 |   |   |-- build.sh
 |   |   |-- Drivers
 |   |   |-- Env.cshrc
 |   |   |-- Include
 |   |   |   `-- Library
 |   |   |   `-- Drivers
 |   |   |-- Library
 |   |   |-- LS1043aRdbPkg
 |   |   |   |-- Drivers
 |   |   |   |-- Include
 |   |   |   |   `-- Library
 |   |   |   |   `-- Drivers
 |   |   |   |-- Library
 |   |   |   |-- LS1043aRdbPkg.dec
 |   |   |   |-- LS1043aRdbPkg.dsc
 |   |   |   `-- LS1043aRdbPkg.fdf
 |   |   |-- NxpQoriqLs.dec
 |   |   |-- NxpQoriqLs.dsc
 |   |   `-- Readme.md
 `-- Silicon
     |-- NXP
         |-- Chassis
         |   |-- Chassis2
         `-- LS1043A
             |-- Include
             |-- LS1043A.dec
             `-- LS1043A.dsc
             
 In Silicon/NXP, we are keeping our SoC specific information and remaining code will be kept in Platform/NXP.
 
 Platform/NXP/LS1043aRdbPkg will host .dsc and .fdf files to support compilation for LS1043A RDB board.
 
 In next series of patches we will be adding support for LS2088 and LS1046 board.
 
 
 Looking forward for your kind support in upstreaming our board in edk2-platforms.
 
 
 Meenakshi Aggarwal (10):
   Platform/NXP: Library to provide helper functions.
   Platform/NXP: Add support for system reset library
   Platform/NXP: Add support for Big Endian Mmio APIs
   Platform/NXP : Add support for Watchdog driver
   Platform/NXP : Add support for DUART library
   Platform/NXP: Add support for I2c operations library
   Platform/NXP : Add support for DS1307 RTC library
   Platform/NXP: Add support for ArmPlatformLib
   SocLib : Add support for initialization of peripherals
   Compilation : Add the fdf, dsc and dec files.
 
  Platform/NXP/Drivers/WatchDog/WatchDog.c           | 386 +++++++++++++++
  Platform/NXP/Drivers/WatchDog/WatchDog.h           |  37 ++
  Platform/NXP/Drivers/WatchDog/WatchDogDxe.inf      |  47 ++
  Platform/NXP/Env.cshrc                             |  75 +++
  Platform/NXP/Include/Bitops.h                      | 179 +++++++
  Platform/NXP/Include/Library/BeIoLib.h             | 332 +++++++++++++
  Platform/NXP/Include/Library/I2c.h                 | 125 +++++
  Platform/NXP/Include/Library/Utils.h               | 137 +++++
  Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec       |  29 ++
  Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc       |  74 +++
  Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf       | 279 +++++++++++
  .../Library/PlatformLib/ArmPlatformLib.c           | 105 ++++
  .../Library/PlatformLib/ArmPlatformLib.inf         |  70 +++
  .../Library/PlatformLib/NxpQoriqLsHelper.S         |  38 ++
  .../Library/PlatformLib/NxpQoriqLsMem.c            | 184 +++++++
  Platform/NXP/Library/BeIoLib/BeIoLib.c             | 400 +++++++++++++++
  Platform/NXP/Library/BeIoLib/BeIoLib.inf           |  31 ++
  Platform/NXP/Library/DUartPortLib/DUart.h          | 128 +++++
  Platform/NXP/Library/DUartPortLib/DUartPortLib.c   | 334 +++++++++++++
  Platform/NXP/Library/DUartPortLib/DUartPortLib.inf |  39 ++
  Platform/NXP/Library/Ds1307RtcLib/Ds1307Rtc.h      |  40 ++
  Platform/NXP/Library/Ds1307RtcLib/Ds1307RtcLib.c   | 226 +++++++++
  Platform/NXP/Library/Ds1307RtcLib/Ds1307RtcLib.inf |  40 ++
  Platform/NXP/Library/I2cLib/I2cLib.c               | 549 +++++++++++++++++++++
  Platform/NXP/Library/I2cLib/I2cLib.h               | 109 ++++
  Platform/NXP/Library/I2cLib/I2cLib.inf             |  43 ++
  .../NXP/Library/ResetSystemLib/ResetSystemLib.c    |  96 ++++
  .../NXP/Library/ResetSystemLib/ResetSystemLib.inf  |  33 ++
  Platform/NXP/Library/UtilsLib/Utils.c              |  97 ++++
  Platform/NXP/Library/UtilsLib/Utils.inf            |  30 ++
  Platform/NXP/NxpQoriqLs.dec                        | 257 ++++++++++
  Platform/NXP/NxpQoriqLs.dsc                        | 453 +++++++++++++++++
  Platform/NXP/Readme.md                             |  14 +
  Platform/NXP/build.sh                              | 100 ++++
  Silicon/NXP/Chassis/Chassis.c                      | 393 +++++++++++++++
  Silicon/NXP/Chassis/Chassis.h                      | 123 +++++
  Silicon/NXP/Chassis/Chassis2/Chassis2.dec          |  19 +
  Silicon/NXP/Chassis/Chassis2/SerDes.h              |  82 +++
  Silicon/NXP/Chassis/Chassis2/Soc.c                 | 146 ++++++
  Silicon/NXP/Chassis/Chassis2/Soc.h                 | 376 ++++++++++++++
  Silicon/NXP/Chassis/LS1043aSocLib.inf              |  48 ++
  Silicon/NXP/Chassis/SerDes.c                       | 253 ++++++++++
  Silicon/NXP/LS1043A/Include/SocSerDes.h            |  55 +++
  Silicon/NXP/LS1043A/LS1043A.dec                    |  22 +
  Silicon/NXP/LS1043A/LS1043A.dsc                    |  82 +++
  45 files changed, 6715 insertions(+)
  create mode 100644 Platform/NXP/Drivers/WatchDog/WatchDog.c
  create mode 100644 Platform/NXP/Drivers/WatchDog/WatchDog.h
  create mode 100644 Platform/NXP/Drivers/WatchDog/WatchDogDxe.inf
  create mode 100644 Platform/NXP/Env.cshrc  create mode 100644 
 Platform/NXP/Include/Bitops.h  create mode 100644 
 Platform/NXP/Include/Library/BeIoLib.h
  create mode 100644 Platform/NXP/Include/Library/I2c.h
  create mode 100644 Platform/NXP/Include/Library/Utils.h
  create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec
  create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
  create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
  create mode 100644 
 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
  create mode 100644 
 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
  create mode 100644 
 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
  create mode 100644 
 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
  create mode 100644 Platform/NXP/Library/BeIoLib/BeIoLib.c
  create mode 100644 Platform/NXP/Library/BeIoLib/BeIoLib.inf
  create mode 100644 Platform/NXP/Library/DUartPortLib/DUart.h
  create mode 100644 Platform/NXP/Library/DUartPortLib/DUartPortLib.c
  create mode 100644 Platform/NXP/Library/DUartPortLib/DUartPortLib.inf
  create mode 100644 Platform/NXP/Library/Ds1307RtcLib/Ds1307Rtc.h
  create mode 100644 Platform/NXP/Library/Ds1307RtcLib/Ds1307RtcLib.c
  create mode 100644 Platform/NXP/Library/Ds1307RtcLib/Ds1307RtcLib.inf
  create mode 100644 Platform/NXP/Library/I2cLib/I2cLib.c
  create mode 100644 Platform/NXP/Library/I2cLib/I2cLib.h
  create mode 100644 Platform/NXP/Library/I2cLib/I2cLib.inf
  create mode 100644 
 Platform/NXP/Library/ResetSystemLib/ResetSystemLib.c
  create mode 100644 
 Platform/NXP/Library/ResetSystemLib/ResetSystemLib.inf
  create mode 100644 Platform/NXP/Library/UtilsLib/Utils.c
  create mode 100644 Platform/NXP/Library/UtilsLib/Utils.inf
  create mode 100644 Platform/NXP/NxpQoriqLs.dec  create mode 100644 
 Platform/NXP/NxpQoriqLs.dsc  create mode 100644 Platform/NXP/Readme.md  
 create mode 100755 Platform/NXP/build.sh  create mode 100644 
 Silicon/NXP/Chassis/Chassis.c  create mode 100644 
 Silicon/NXP/Chassis/Chassis.h  create mode 100644 
 Silicon/NXP/Chassis/Chassis2/Chassis2.dec
  create mode 100644 Silicon/NXP/Chassis/Chassis2/SerDes.h
  create mode 100644 Silicon/NXP/Chassis/Chassis2/Soc.c
  create mode 100644 Silicon/NXP/Chassis/Chassis2/Soc.h
  create mode 100644 Silicon/NXP/Chassis/LS1043aSocLib.inf
  create mode 100644 Silicon/NXP/Chassis/SerDes.c  create mode 100644 
 Silicon/NXP/LS1043A/Include/SocSerDes.h
  create mode 100644 Silicon/NXP/LS1043A/LS1043A.dec  create mode 
 100644 Silicon/NXP/LS1043A/LS1043A.dsc

-- 
1.9.1



^ permalink raw reply	[flat|nested] 25+ messages in thread

* [PATCH edk2-platforms] [PATCH v3 1/9] Platform/NXP: Add support for Big Endian Mmio APIs
  2017-11-27 10:51 [PATCH edk2-platforms] [PATCH v3 0/9] Platform/NXP Meenakshi Aggarwal
@ 2017-11-27 10:51 ` Meenakshi Aggarwal
  2017-11-27 10:51 ` [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add support for Watchdog driver Meenakshi Aggarwal
                   ` (8 subsequent siblings)
  9 siblings, 0 replies; 25+ messages in thread
From: Meenakshi Aggarwal @ 2017-11-27 10:51 UTC (permalink / raw)
  To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel

This library add supports for BE read/write and other
MMIO helper function.
In this data swapped after reading from MMIO and before
write using MMIO.
It can be used by any module with BE address space.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
 Platform/NXP/Include/Library/BeIoLib.h   | 332 +++++++++++++++++++++++++
 Platform/NXP/Library/BeIoLib/BeIoLib.c   | 400 +++++++++++++++++++++++++++++++
 Platform/NXP/Library/BeIoLib/BeIoLib.inf |  31 +++
 3 files changed, 763 insertions(+)
 create mode 100644 Platform/NXP/Include/Library/BeIoLib.h
 create mode 100644 Platform/NXP/Library/BeIoLib/BeIoLib.c
 create mode 100644 Platform/NXP/Library/BeIoLib/BeIoLib.inf

diff --git a/Platform/NXP/Include/Library/BeIoLib.h b/Platform/NXP/Include/Library/BeIoLib.h
new file mode 100644
index 0000000..639674f
--- /dev/null
+++ b/Platform/NXP/Include/Library/BeIoLib.h
@@ -0,0 +1,332 @@
+/** BeIoLib.h
+ *
+ *  Copyright 2017 NXP
+ *
+ *  This program and the accompanying materials
+ *  are licensed and made available under the terms and conditions of the BSD License
+ *  which accompanies this distribution.  The full text of the license may be found at
+ *  http://opensource.org/licenses/bsd-license.php
+ *
+ *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ *
+ **/
+
+#ifndef __BE_IOLIB_H__
+#define __BE_IOLIB_H__
+
+#include <Base.h>
+
+/**
+  MmioRead8 for Big-Endian modules.
+
+  @param  Address The MMIO register to read.
+
+  @return The value read.
+
+**/
+UINT8
+EFIAPI
+BeMmioRead8 (
+  IN  UINTN     Address
+  );
+
+/**
+  MmioRead16 for Big-Endian modules.
+
+  @param  Address The MMIO register to read.
+
+  @return The value read.
+
+**/
+UINT16
+EFIAPI
+BeMmioRead16 (
+  IN  UINTN     Address
+  );
+
+/**
+  MmioRead32 for Big-Endian modules.
+
+  @param  Address The MMIO register to read.
+
+  @return The value read.
+
+**/
+UINT32
+EFIAPI
+BeMmioRead32 (
+  IN  UINTN     Address
+  );
+
+/**
+  MmioRead64 for Big-Endian modules.
+
+  @param  Address The MMIO register to read.
+
+  @return The value read.
+
+**/
+UINT64
+EFIAPI
+BeMmioRead64 (
+  IN  UINTN     Address
+  );
+
+/**
+  MmioWrite8 for Big-Endian modules.
+
+  @param  Address The MMIO register to write.
+  @param  Value   The value to write to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+BeMmioWrite8 (
+  IN  UINTN     Address,
+  IN  UINT8     Value
+  );
+
+/**
+  MmioWrite16 for Big-Endian modules.
+
+  @param  Address The MMIO register to write.
+  @param  Value   The value to write to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+BeMmioWrite16 (
+  IN  UINTN     Address,
+  IN  UINT16    Value
+  );
+
+/**
+  MmioWrite32 for Big-Endian modules.
+
+  @param  Address The MMIO register to write.
+  @param  Value   The value to write to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+BeMmioWrite32 (
+  IN  UINTN     Address,
+  IN  UINT32    Value
+  );
+
+/**
+  MmioWrite64 for Big-Endian modules.
+
+  @param  Address The MMIO register to write.
+  @param  Value   The value to write to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+BeMmioWrite64 (
+  IN  UINTN     Address,
+  IN  UINT64    Value
+  );
+
+/**
+  MmioAndThenOr8 for Big-Endian modules.
+
+  @param  Address The MMIO register to write.
+  @param  AndData The value to AND with the read value from the MMIO register.
+  @param  OrData  The value to OR with the result of the AND operation.
+
+  @return The value written back to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+BeMmioAndThenOr8 (
+  IN  UINTN     Address,
+  IN  UINT8     AndData,
+  IN  UINT8     OrData
+  );
+
+/**
+  MmioAndThenOr16 for Big-Endian modules.
+
+  @param  Address The MMIO register to write.
+  @param  AndData The value to AND with the read value from the MMIO register.
+  @param  OrData  The value to OR with the result of the AND operation.
+
+  @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+BeMmioAndThenOr16 (
+  IN  UINTN     Address,
+  IN  UINT16    AndData,
+  IN  UINT16    OrData
+  );
+
+/**
+  MmioAndThenOr32 for Big-Endian modules.
+
+  @param  Address The MMIO register to write.
+  @param  AndData The value to AND with the read value from the MMIO register.
+  @param  OrData  The value to OR with the result of the AND operation.
+
+  @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+BeMmioAndThenOr32 (
+  IN  UINTN     Address,
+  IN  UINT32    AndData,
+  IN  UINT32    OrData
+  );
+
+/**
+  MmioAndThenOr64 for Big-Endian modules.
+
+  @param  Address The MMIO register to write.
+  @param  AndData The value to AND with the read value from the MMIO register.
+  @param  OrData  The value to OR with the result of the AND operation.
+
+  @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+BeMmioAndThenOr64 (
+  IN  UINTN     Address,
+  IN  UINT64    AndData,
+  IN  UINT64    OrData
+  );
+
+/**
+  MmioOr8 for Big-Endian modules.
+
+  @param  Address The MMIO register to write.
+  @param  OrData  The value to OR with the read value from the MMIO register.
+
+  @return The value written back to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+BeMmioOr8 (
+  IN  UINTN     Address,
+  IN  UINT8     OrData
+  );
+
+/**
+  MmioOr16 for Big-Endian modules.
+
+  @param  Address The MMIO register to write.
+  @param  OrData  The value to OR with the read value from the MMIO register.
+
+  @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+BeMmioOr16 (
+  IN  UINTN     Address,
+  IN  UINT16    OrData
+  );
+
+/**
+  MmioOr32 for Big-Endian modules.
+
+  @param  Address The MMIO register to write.
+  @param  OrData  The value to OR with the read value from the MMIO register.
+
+  @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+BeMmioOr32 (
+  IN  UINTN     Address,
+  IN  UINT32    OrData
+  );
+
+/**
+  MmioOr64 for Big-Endian modules.
+
+  @param  Address The MMIO register to write.
+  @param  OrData  The value to OR with the read value from the MMIO register.
+
+  @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+BeMmioOr64 (
+  IN  UINTN     Address,
+  IN  UINT64    OrData
+  );
+
+/**
+  MmioAnd8 for Big-Endian modules.
+
+  @param  Address The MMIO register to write.
+  @param  AndData The value to AND with the read value from the MMIO register.
+
+  @return The value written back to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+BeMmioAnd8 (
+  IN  UINTN     Address,
+  IN  UINT8     AndData
+  );
+
+/**
+  MmioAnd16 for Big-Endian modules.
+
+  @param  Address The MMIO register to write.
+  @param  AndData The value to AND with the read value from the MMIO register.
+
+  @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+BeMmioAnd16 (
+  IN  UINTN     Address,
+  IN  UINT16    AndData
+  );
+
+/**
+  MmioAnd32 for Big-Endian modules.
+
+  @param  Address The MMIO register to write.
+  @param  AndData The value to AND with the read value from the MMIO register.
+
+  @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+BeMmioAnd32 (
+  IN  UINTN     Address,
+  IN  UINT32    AndData
+  );
+
+/**
+  MmioAnd64 for Big-Endian modules.
+
+  @param  Address The MMIO register to write.
+  @param  AndData The value to AND with the read value from the MMIO register.
+
+  @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+BeMmioAnd64 (
+  IN  UINTN     Address,
+  IN  UINT64    AndData
+  );
+
+#endif /* _BE_IOLIB_H */
diff --git a/Platform/NXP/Library/BeIoLib/BeIoLib.c b/Platform/NXP/Library/BeIoLib/BeIoLib.c
new file mode 100644
index 0000000..c3d2cf8
--- /dev/null
+++ b/Platform/NXP/Library/BeIoLib/BeIoLib.c
@@ -0,0 +1,400 @@
+/** BeIoLib.c
+
+  Provide MMIO APIs for BE modules.
+
+  Copyright 2017 NXP
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+
+/**
+  MmioRead8 for Big-Endian modules.
+
+  @param  Address The MMIO register to read.
+
+  @return The value read.
+
+**/
+UINT8
+EFIAPI
+BeMmioRead8 (
+  IN  UINTN     Address
+  )
+{
+  return MmioRead8 (Address);
+}
+
+/**
+  MmioRead16 for Big-Endian modules.
+
+  @param  Address The MMIO register to read.
+
+  @return The value read.
+
+**/
+UINT16
+EFIAPI
+BeMmioRead16 (
+  IN  UINTN     Address
+  )
+{
+  return SwapBytes16 (MmioRead16 (Address));
+}
+
+/**
+  MmioRead32 for Big-Endian modules.
+
+  @param  Address The MMIO register to read.
+
+  @return The value read.
+
+**/
+UINT32
+EFIAPI
+BeMmioRead32 (
+  IN  UINTN     Address
+  )
+{
+  return SwapBytes32 (MmioRead32 (Address));
+}
+
+/**
+  MmioRead64 for Big-Endian modules.
+
+  @param  Address The MMIO register to read.
+
+  @return The value read.
+
+**/
+UINT64
+EFIAPI
+BeMmioRead64 (
+  IN  UINTN     Address
+  )
+{
+  return SwapBytes64 (MmioRead64 (Address));
+}
+
+/**
+  MmioWrite8 for Big-Endian modules.
+
+  @param  Address The MMIO register to write.
+  @param  Value   The value to write to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+BeMmioWrite8 (
+  IN  UINTN     Address,
+  IN  UINT8     Value
+  )
+{
+  return MmioWrite8 (Address, Value);
+}
+
+/**
+  MmioWrite16 for Big-Endian modules.
+
+  @param  Address The MMIO register to write.
+  @param  Value   The value to write to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+BeMmioWrite16 (
+  IN  UINTN     Address,
+  IN  UINT16    Value
+  )
+{
+  return MmioWrite16 (Address, SwapBytes16 (Value));
+}
+
+/**
+  MmioWrite32 for Big-Endian modules.
+
+  @param  Address The MMIO register to write.
+  @param  Value   The value to write to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+BeMmioWrite32 (
+  IN  UINTN     Address,
+  IN  UINT32    Value
+  )
+{
+  return MmioWrite32 (Address, SwapBytes32 (Value));
+}
+
+/**
+  MmioWrite64 for Big-Endian modules.
+
+  @param  Address The MMIO register to write.
+  @param  Value   The value to write to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+BeMmioWrite64 (
+  IN  UINTN     Address,
+  IN  UINT64    Value
+  )
+{
+  return MmioWrite64 (Address, SwapBytes64 (Value));
+}
+
+/**
+  MmioAndThenOr8 for Big-Endian modules.
+
+  @param  Address The MMIO register to write.
+  @param  AndData The value to AND with the read value from the MMIO register.
+  @param  OrData  The value to OR with the result of the AND operation.
+
+  @return The value written back to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+BeMmioAndThenOr8 (
+  IN  UINTN     Address,
+  IN  UINT8     AndData,
+  IN  UINT8     OrData
+  )
+{
+  return MmioAndThenOr8 (Address, AndData, OrData);
+}
+
+/**
+  MmioAndThenOr16 for Big-Endian modules.
+
+  @param  Address The MMIO register to write.
+  @param  AndData The value to AND with the read value from the MMIO register.
+  @param  OrData  The value to OR with the result of the AND operation.
+
+  @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+BeMmioAndThenOr16 (
+  IN  UINTN     Address,
+  IN  UINT16    AndData,
+  IN  UINT16    OrData
+  )
+{
+  AndData = SwapBytes16 (AndData);
+  OrData = SwapBytes16 (OrData);
+
+  return MmioAndThenOr16 (Address, AndData, OrData);
+}
+
+/**
+  MmioAndThenOr32 for Big-Endian modules.
+
+  @param  Address The MMIO register to write.
+  @param  AndData The value to AND with the read value from the MMIO register.
+  @param  OrData  The value to OR with the result of the AND operation.
+
+  @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+BeMmioAndThenOr32 (
+  IN  UINTN     Address,
+  IN  UINT32    AndData,
+  IN  UINT32    OrData
+  )
+{
+  AndData = SwapBytes32 (AndData);
+  OrData = SwapBytes32 (OrData);
+
+  return MmioAndThenOr32 (Address, AndData, OrData);
+}
+
+/**
+  MmioAndThenOr64 for Big-Endian modules.
+
+  @param  Address The MMIO register to write.
+  @param  AndData The value to AND with the read value from the MMIO register.
+  @param  OrData  The value to OR with the result of the AND operation.
+
+  @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+BeMmioAndThenOr64 (
+  IN  UINTN     Address,
+  IN  UINT64    AndData,
+  IN  UINT64    OrData
+  )
+{
+  AndData = SwapBytes64 (AndData);
+  OrData = SwapBytes64 (OrData);
+
+  return MmioAndThenOr64 (Address, AndData, OrData);
+}
+
+/**
+  MmioOr8 for Big-Endian modules.
+
+  @param  Address The MMIO register to write.
+  @param  OrData  The value to OR with the read value from the MMIO register.
+
+  @return The value written back to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+BeMmioOr8 (
+  IN  UINTN     Address,
+  IN  UINT8     OrData
+  )
+{
+  return MmioOr8 (Address, OrData);
+}
+
+/**
+  MmioOr16 for Big-Endian modules.
+
+  @param  Address The MMIO register to write.
+  @param  OrData  The value to OR with the read value from the MMIO register.
+
+  @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+BeMmioOr16 (
+  IN  UINTN     Address,
+  IN  UINT16    OrData
+  )
+{
+  return MmioOr16 (Address, SwapBytes16 (OrData));
+}
+
+/**
+  MmioOr32 for Big-Endian modules.
+
+  @param  Address The MMIO register to write.
+  @param  OrData  The value to OR with the read value from the MMIO register.
+
+  @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+BeMmioOr32 (
+  IN  UINTN     Address,
+  IN  UINT32    OrData
+  )
+{
+  return MmioOr32 (Address, SwapBytes32 (OrData));
+}
+
+/**
+  MmioOr64 for Big-Endian modules.
+
+  @param  Address The MMIO register to write.
+  @param  OrData  The value to OR with the read value from the MMIO register.
+
+  @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+BeMmioOr64 (
+  IN  UINTN     Address,
+  IN  UINT64    OrData
+  )
+{
+  return MmioOr64 (Address, SwapBytes64 (OrData));
+}
+
+/**
+  MmioAnd8 for Big-Endian modules.
+
+  @param  Address The MMIO register to write.
+  @param  AndData The value to AND with the read value from the MMIO register.
+
+  @return The value written back to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+BeMmioAnd8 (
+  IN  UINTN     Address,
+  IN  UINT8     AndData
+  )
+{
+  return MmioAnd8 (Address, AndData);
+}
+
+/**
+  MmioAnd16 for Big-Endian modules.
+
+  @param  Address The MMIO register to write.
+  @param  AndData The value to AND with the read value from the MMIO register.
+
+  @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+BeMmioAnd16 (
+  IN  UINTN     Address,
+  IN  UINT16    AndData
+  )
+{
+  return MmioAnd16 (Address, SwapBytes16 (AndData));
+}
+
+/**
+  MmioAnd32 for Big-Endian modules.
+
+  @param  Address The MMIO register to write.
+  @param  AndData The value to AND with the read value from the MMIO register.
+
+  @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+BeMmioAnd32 (
+  IN  UINTN     Address,
+  IN  UINT32    AndData
+  )
+{
+  return MmioAnd32 (Address, SwapBytes32 (AndData));
+}
+
+/**
+  MmioAnd64 for Big-Endian modules.
+
+  @param  Address The MMIO register to write.
+  @param  AndData The value to AND with the read value from the MMIO register.
+
+  @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+BeMmioAnd64 (
+  IN  UINTN     Address,
+  IN  UINT64    AndData
+  )
+{
+  return MmioAnd64 (Address, SwapBytes64 (AndData));
+}
diff --git a/Platform/NXP/Library/BeIoLib/BeIoLib.inf b/Platform/NXP/Library/BeIoLib/BeIoLib.inf
new file mode 100644
index 0000000..7e8e32c
--- /dev/null
+++ b/Platform/NXP/Library/BeIoLib/BeIoLib.inf
@@ -0,0 +1,31 @@
+## @BeIoLib.inf
+
+#  Copyright 2017 NXP
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = BeIoLib
+  FILE_GUID                      = 28d77333-77eb-4faf-8735-130e5eb3e343
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = BeIoLib
+
+[Packages]
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+
+[LibraryClasses]
+  IoLib
+
+[Sources.common]
+  BeIoLib.c
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add support for Watchdog driver
  2017-11-27 10:51 [PATCH edk2-platforms] [PATCH v3 0/9] Platform/NXP Meenakshi Aggarwal
  2017-11-27 10:51 ` [PATCH edk2-platforms] [PATCH v3 1/9] Platform/NXP: Add support for Big Endian Mmio APIs Meenakshi Aggarwal
@ 2017-11-27 10:51 ` Meenakshi Aggarwal
  2017-12-04 14:35   ` Leif Lindholm
  2017-11-27 10:51 ` [PATCH edk2-platforms] [PATCH v3 3/9] SocLib : Add support for initialization of peripherals Meenakshi Aggarwal
                   ` (7 subsequent siblings)
  9 siblings, 1 reply; 25+ messages in thread
From: Meenakshi Aggarwal @ 2017-11-27 10:51 UTC (permalink / raw)
  To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel

Installs watchdog timer arch protocol

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
 Platform/NXP/Drivers/WatchDog/WatchDog.c      | 421 ++++++++++++++++++++++++++
 Platform/NXP/Drivers/WatchDog/WatchDog.h      |  37 +++
 Platform/NXP/Drivers/WatchDog/WatchDogDxe.inf |  47 +++
 3 files changed, 505 insertions(+)
 create mode 100644 Platform/NXP/Drivers/WatchDog/WatchDog.c
 create mode 100644 Platform/NXP/Drivers/WatchDog/WatchDog.h
 create mode 100644 Platform/NXP/Drivers/WatchDog/WatchDogDxe.inf

diff --git a/Platform/NXP/Drivers/WatchDog/WatchDog.c b/Platform/NXP/Drivers/WatchDog/WatchDog.c
new file mode 100644
index 0000000..a9c70ef
--- /dev/null
+++ b/Platform/NXP/Drivers/WatchDog/WatchDog.c
@@ -0,0 +1,421 @@
+/** WatchDog.c
+*
+*  Based on Watchdog driver implemenation available in
+*  ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.c
+*
+*  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+*  Copyright 2017 NXP
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/BeIoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/WatchdogTimer.h>
+
+#include "WatchDog.h"
+
+STATIC EFI_EVENT  EfiExitBootServicesEvent;
+
+STATIC
+UINT16
+EFIAPI
+WdogRead (
+  IN  UINTN     Address
+  )
+{
+  if (FixedPcdGetBool (PcdWdogBigEndian)) {
+    return BeMmioRead16 (Address);
+  } else {
+    return MmioRead16(Address);
+  }
+}
+
+STATIC
+UINT16
+EFIAPI
+WdogWrite (
+  IN  UINTN     Address,
+  IN  UINT16    Value
+  )
+{
+  if (FixedPcdGetBool (PcdWdogBigEndian)) {
+    return BeMmioWrite16 (Address, Value);
+  } else {
+    return MmioWrite16 (Address, Value);
+  }
+}
+
+STATIC
+UINT16
+EFIAPI
+WdogAndThenOr (
+  IN  UINTN     Address,
+  IN  UINT16    And,
+  IN  UINT16    Or
+  )
+{
+  if (FixedPcdGetBool (PcdWdogBigEndian)) {
+    return BeMmioAndThenOr16 (Address, And, Or);
+  } else {
+    return MmioAndThenOr16 (Address, And, Or);
+  }
+}
+
+STATIC
+UINT16
+EFIAPI
+WdogOr (
+  IN  UINTN     Address,
+  IN  UINT16    Or
+  )
+{
+  if (FixedPcdGetBool (PcdWdogBigEndian)) {
+    return BeMmioOr16 (Address, Or);
+  } else {
+    return MmioOr16 (Address, Or);
+  }
+}
+
+STATIC
+VOID
+WdogPing (
+  VOID
+  )
+{
+  //
+  // To reload a timeout value to the counter the proper service sequence begins by
+  // writing 0x_5555 followed by 0x_AAAA to the Watchdog Service Register (WDOG_WSR).
+  // This service sequence will reload the counter with the timeout value WT[7:0] of
+  // Watchdog Control Register (WDOG_WCR).
+  //
+
+  WdogWrite (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WSR_OFFSET,
+                     WDOG_SERVICE_SEQ1);
+  WdogWrite (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WSR_OFFSET,
+                     WDOG_SERVICE_SEQ2);
+}
+
+/**
+  Stop the Wdog watchdog timer from counting down.
+**/
+STATIC
+VOID
+WdogStop (
+  VOID
+  )
+{
+  // Watchdog cannot be disabled by software once started.
+  // At best, we can keep reload counter with maximum value
+
+  WdogAndThenOr (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WCR_OFFSET,
+                 (UINT16)(~WDOG_WCR_WT),
+                 (WD_COUNT (WT_MAX_TIME) & WD_COUNT_MASK));
+  WdogPing ();
+}
+
+/**
+  Starts the Wdog counting down by feeding Service register with
+  desired pattern.
+  The count down will start from the value stored in the Load register,
+  not from the value where it was previously stopped.
+**/
+STATIC
+VOID
+WdogStart (
+  VOID
+  )
+{
+  //Reload the timeout value
+  WdogPing ();
+}
+
+/**
+    On exiting boot services we must make sure the Wdog Watchdog Timer
+    is stopped.
+**/
+STATIC
+VOID
+EFIAPI
+ExitBootServicesEvent (
+  IN EFI_EVENT  Event,
+  IN VOID       *Context
+  )
+{
+  WdogStop ();
+}
+
+/**
+  This function registers the handler NotifyFunction so it is called every time
+  the watchdog timer expires.  It also passes the amount of time since the last
+  handler call to the NotifyFunction.
+  If NotifyFunction is not NULL and a handler is not already registered,
+  then the new handler is registered and EFI_SUCCESS is returned.
+  If NotifyFunction is NULL, and a handler is already registered,
+  then that handler is unregistered.
+  If an attempt is made to register a handler when a handler is already registered,
+  then EFI_ALREADY_STARTED is returned.
+  If an attempt is made to unregister a handler when a handler is not registered,
+  then EFI_INVALID_PARAMETER is returned.
+
+  @param  This             The EFI_TIMER_ARCH_PROTOCOL instance.
+  @param  NotifyFunction   The function to call when a timer interrupt fires. This
+                           function executes at TPL_HIGH_LEVEL. The DXE Core will
+                           register a handler for the timer interrupt, so it can know
+                           how much time has passed. This information is used to
+                           signal timer based events. NULL will unregister the handler.
+
+  @retval EFI_SUCCESS           The watchdog timer handler was registered.
+  @retval EFI_ALREADY_STARTED   NotifyFunction is not NULL, and a handler is already
+                                registered.
+  @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not
+                                previously registered.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+WdogRegisterHandler (
+  IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL   *This,
+  IN EFI_WATCHDOG_TIMER_NOTIFY          NotifyFunction
+  )
+{
+  // ERROR: This function is not supported.
+  // The hardware watchdog will reset the board
+  return EFI_INVALID_PARAMETER;
+}
+
+/**
+
+  This function adjusts the period of timer interrupts to the value specified
+  by TimerPeriod.  If the timer period is updated, then the selected timer
+  period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned.  If
+  the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.
+  If an error occurs while attempting to update the timer period, then the
+  timer hardware will be put back in its state prior to this call, and
+  EFI_DEVICE_ERROR is returned.  If TimerPeriod is 0, then the timer interrupt
+  is disabled.  This is not the same as disabling the CPU's interrupts.
+  Instead, it must either turn off the timer hardware, or it must adjust the
+  interrupt controller so that a CPU interrupt is not generated when the timer
+  interrupt fires.
+
+  @param  This             The EFI_TIMER_ARCH_PROTOCOL instance.
+  @param  TimerPeriod      The rate to program the timer interrupt in 100 nS units. If
+                           the timer hardware is not programmable, then EFI_UNSUPPORTED is
+                           returned. If the timer is programmable, then the timer period
+                           will be rounded up to the nearest timer period that is supported
+                           by the timer hardware. If TimerPeriod is set to 0, then the
+                           timer interrupts will be disabled.
+
+
+  @retval EFI_SUCCESS           The timer period was changed.
+  @retval EFI_UNSUPPORTED       The platform cannot change the period of the timer interrupt.
+  @retval EFI_DEVICE_ERROR      The timer period could not be changed due to a device error.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+WdogSetTimerPeriod (
+  IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL   *This,
+  IN UINT64                             TimerPeriod   // In 100ns units
+  )
+{
+  EFI_STATUS  Status;
+  UINT64      TimerPeriodInSec;
+  UINT16      Val;
+
+  Status = EFI_SUCCESS;
+
+  if (TimerPeriod == 0) {
+    // This is a watchdog stop request
+    WdogStop ();
+    return Status;
+  } else {
+    // Convert the TimerPeriod (in 100 ns unit) to an equivalent second value
+
+    TimerPeriodInSec = DivU64x32 (TimerPeriod, NANO_SECOND_BASE);
+
+    // The registers in the Wdog are only 32 bits
+    if (TimerPeriodInSec > WT_MAX_TIME) {
+      // We could load the watchdog with the maximum supported value but
+      // if a smaller value was requested, this could have the watchdog
+      // triggering before it was intended.
+      // Better generate an error to let the caller know.
+      Status = EFI_DEVICE_ERROR;
+      return Status;
+    }
+
+    // set the new timeout value in the WCR
+    // Convert the timeout value from Seconds to timer count
+    Val = ((WD_COUNT(TimerPeriodInSec) & WD_COUNT_MASK) << 8);
+
+    WdogAndThenOr (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WCR_OFFSET,
+                   (UINT16)(~WDOG_WCR_WT),
+                   Val);
+    // Start the watchdog
+    WdogStart ();
+  }
+
+  return Status;
+}
+
+/**
+  This function retrieves the period of timer interrupts in 100 ns units,
+  returns that value in TimerPeriod, and returns EFI_SUCCESS.  If TimerPeriod
+  is NULL, then EFI_INVALID_PARAMETER is returned.  If a TimerPeriod of 0 is
+  returned, then the timer is currently disabled.
+
+  @param  This             The EFI_TIMER_ARCH_PROTOCOL instance.
+  @param  TimerPeriod      A pointer to the timer period to retrieve in 100 ns units. If
+                           0 is returned, then the timer is currently disabled.
+
+
+  @retval EFI_SUCCESS           The timer period was returned in TimerPeriod.
+  @retval EFI_INVALID_PARAMETER TimerPeriod is NULL.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+WdogGetTimerPeriod (
+  IN  EFI_WATCHDOG_TIMER_ARCH_PROTOCOL   *This,
+  OUT UINT64                             *TimerPeriod
+  )
+{
+  EFI_STATUS  Status;
+  UINT64      ReturnValue;
+  UINT16      Val;
+
+  Status = EFI_SUCCESS;
+
+  if (TimerPeriod == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  // Check if the watchdog is stopped
+  if ((WdogRead (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WCR_OFFSET)
+              & WDOG_WCR_WDE) == 0 ) {
+    // It is stopped, so return zero.
+    ReturnValue = 0;
+  } else {
+    // Convert the Watchdog ticks into equivalent TimerPeriod second value.
+    Val = (WdogRead (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WCR_OFFSET)
+            & WDOG_WCR_WT ) >> 8;
+    ReturnValue = WD_SEC(Val);
+  }
+
+  *TimerPeriod = ReturnValue;
+  return Status;
+}
+
+/**
+  Interface structure for the Watchdog Architectural Protocol.
+
+  @par Protocol Description:
+  This protocol provides a service to set the amount of time to wait
+  before firing the watchdog timer, and it also provides a service to
+  register a handler that is invoked when the watchdog timer fires.
+
+  @par When the watchdog timer fires, control will be passed to a handler
+  if one has been registered.  If no handler has been registered,
+  or the registered handler returns, then the system will be
+  reset by calling the Runtime Service ResetSystem().
+
+  @param RegisterHandler
+  Registers a handler that will be called each time the
+  watchdogtimer interrupt fires.  TimerPeriod defines the minimum
+  time between timer interrupts, so TimerPeriod will also
+  be the minimum time between calls to the registered
+  handler.
+  NOTE: If the watchdog resets the system in hardware, then
+        this function will not have any chance of executing.
+
+  @param SetTimerPeriod
+  Sets the period of the timer interrupt in 100 nS units.
+  This function is optional, and may return EFI_UNSUPPORTED.
+  If this function is supported, then the timer period will
+  be rounded up to the nearest supported timer period.
+
+  @param GetTimerPeriod
+  Retrieves the period of the timer interrupt in 100 nS units.
+
+**/
+STATIC
+EFI_WATCHDOG_TIMER_ARCH_PROTOCOL  gWatchdogTimer = {
+  WdogRegisterHandler,
+  WdogSetTimerPeriod,
+  WdogGetTimerPeriod
+};
+
+/**
+  Initialize state information for the Watchdog Timer Architectural Protocol.
+
+  @param  ImageHandle   of the loaded driver
+  @param  SystemTable   Pointer to the System Table
+
+  @retval EFI_SUCCESS           Protocol registered
+  @retval EFI_OUT_OF_RESOURCES  Cannot allocate protocol data structure
+  @retval EFI_DEVICE_ERROR      Hardware problems
+
+**/
+EFI_STATUS
+EFIAPI
+WdogInitialize (
+  IN EFI_HANDLE         ImageHandle,
+  IN EFI_SYSTEM_TABLE   *SystemTable
+  )
+{
+  EFI_STATUS  Status;
+  EFI_HANDLE  Handle;
+
+  WdogAndThenOr (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WCR_OFFSET,
+                 (UINT16)(~WDOG_WCR_WT),
+                 (WD_COUNT (WT_MAX_TIME) & WD_COUNT_MASK));
+
+  WdogOr (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WCR_OFFSET, WDOG_WCR_WDE);
+
+  //
+  // Make sure the Watchdog Timer Architectural Protocol
+  // has not been installed in the system yet.
+  // This will avoid conflicts with the universal watchdog
+  //
+  ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiWatchdogTimerArchProtocolGuid);
+
+  // Register for an ExitBootServicesEvent
+  Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY,
+              ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent);
+  if (EFI_ERROR (Status)) {
+    Status = EFI_OUT_OF_RESOURCES;
+    return Status;
+  }
+
+  // Install the Timer Architectural Protocol onto a new handle
+  Handle = NULL;
+  Status = gBS->InstallMultipleProtocolInterfaces (
+                  &Handle,
+                  &gEfiWatchdogTimerArchProtocolGuid, &gWatchdogTimer,
+                  NULL
+                  );
+  if (EFI_ERROR (Status)) {
+    gBS->CloseEvent (EfiExitBootServicesEvent);
+    Status = EFI_OUT_OF_RESOURCES;
+    return Status;
+  }
+
+  WdogPing ();
+
+  return Status;
+}
diff --git a/Platform/NXP/Drivers/WatchDog/WatchDog.h b/Platform/NXP/Drivers/WatchDog/WatchDog.h
new file mode 100644
index 0000000..1de308b
--- /dev/null
+++ b/Platform/NXP/Drivers/WatchDog/WatchDog.h
@@ -0,0 +1,37 @@
+/** WatchDog.h
+*
+*  Copyright 2017 NXP
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __WATCHDOG_H__
+#define __WATCHDOG_H__
+
+#define WDOG_SIZE           0x1000
+#define WDOG_WCR_OFFSET     0
+#define WDOG_WSR_OFFSET     2
+#define WDOG_WRSR_OFFSET    4
+#define WDOG_WICR_OFFSET    6
+#define WDOG_WCR_WT         (0xFF << 8)
+#define WDOG_WCR_WDE        (1 << 2)
+#define WDOG_SERVICE_SEQ1   0x5555
+#define WDOG_SERVICE_SEQ2   0xAAAA
+#define WDOG_WCR_WDZST      0x1
+#define WDOG_WCR_WRE        (1 << 3)  /* -> WDOG Reset Enable */
+
+#define WT_MAX_TIME         128
+#define WD_COUNT(Sec)       (((Sec) * 2 - 1) << 8)
+#define WD_COUNT_MASK       0xff00
+#define WD_SEC(Cnt)         (((Cnt) + 1) / 2)
+
+#define NANO_SECOND_BASE    10000000
+
+#endif //__WATCHDOG_H__
diff --git a/Platform/NXP/Drivers/WatchDog/WatchDogDxe.inf b/Platform/NXP/Drivers/WatchDog/WatchDogDxe.inf
new file mode 100644
index 0000000..63b0816
--- /dev/null
+++ b/Platform/NXP/Drivers/WatchDog/WatchDogDxe.inf
@@ -0,0 +1,47 @@
+#  WatchDog.inf
+#
+#  Component description file for  WatchDog module
+#
+#  Copyright 2017 NXP
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = WatchDogDxe
+  FILE_GUID                      = 0358b544-ec65-4339-89cd-cad60a3dd787
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = WdogInitialize
+
+[Sources.common]
+  WatchDog.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  Platform/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+  BaseLib
+  BeIoLib
+  PcdLib
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+
+[Pcd]
+  gNxpQoriqLsTokenSpaceGuid.PcdWdog1BaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian
+
+[Protocols]
+  gEfiWatchdogTimerArchProtocolGuid
+
+[Depex]
+  TRUE
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [PATCH edk2-platforms] [PATCH v3 3/9] SocLib : Add support for initialization of peripherals
  2017-11-27 10:51 [PATCH edk2-platforms] [PATCH v3 0/9] Platform/NXP Meenakshi Aggarwal
  2017-11-27 10:51 ` [PATCH edk2-platforms] [PATCH v3 1/9] Platform/NXP: Add support for Big Endian Mmio APIs Meenakshi Aggarwal
  2017-11-27 10:51 ` [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add support for Watchdog driver Meenakshi Aggarwal
@ 2017-11-27 10:51 ` Meenakshi Aggarwal
  2017-11-27 10:51 ` [PATCH edk2-platforms] [PATCH v3 4/9] Platform/NXP : Add support for DUART library Meenakshi Aggarwal
                   ` (6 subsequent siblings)
  9 siblings, 0 replies; 25+ messages in thread
From: Meenakshi Aggarwal @ 2017-11-27 10:51 UTC (permalink / raw)
  To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel

Add SocInit function that initializes peripherals
and print board and soc information.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
 Platform/NXP/Include/Bitops.h             | 179 +++++++++++++
 Silicon/NXP/Chassis/Chassis.c             | 413 ++++++++++++++++++++++++++++++
 Silicon/NXP/Chassis/Chassis.h             | 144 +++++++++++
 Silicon/NXP/Chassis/Chassis2/Chassis2.dec |  19 ++
 Silicon/NXP/Chassis/Chassis2/SerDes.h     |  69 +++++
 Silicon/NXP/Chassis/Chassis2/Soc.c        | 145 +++++++++++
 Silicon/NXP/Chassis/Chassis2/Soc.h        | 376 +++++++++++++++++++++++++++
 Silicon/NXP/Chassis/LS1043aSocLib.inf     |  47 ++++
 Silicon/NXP/Chassis/SerDes.c              | 254 ++++++++++++++++++
 Silicon/NXP/LS1043A/Include/SocSerDes.h   |  55 ++++
 10 files changed, 1701 insertions(+)
 create mode 100644 Platform/NXP/Include/Bitops.h
 create mode 100644 Silicon/NXP/Chassis/Chassis.c
 create mode 100644 Silicon/NXP/Chassis/Chassis.h
 create mode 100644 Silicon/NXP/Chassis/Chassis2/Chassis2.dec
 create mode 100644 Silicon/NXP/Chassis/Chassis2/SerDes.h
 create mode 100644 Silicon/NXP/Chassis/Chassis2/Soc.c
 create mode 100644 Silicon/NXP/Chassis/Chassis2/Soc.h
 create mode 100644 Silicon/NXP/Chassis/LS1043aSocLib.inf
 create mode 100644 Silicon/NXP/Chassis/SerDes.c
 create mode 100644 Silicon/NXP/LS1043A/Include/SocSerDes.h

diff --git a/Platform/NXP/Include/Bitops.h b/Platform/NXP/Include/Bitops.h
new file mode 100644
index 0000000..3d6f111
--- /dev/null
+++ b/Platform/NXP/Include/Bitops.h
@@ -0,0 +1,179 @@
+/** Bitops.h
+  Header defining the general bitwise operations
+
+  Copyright 2017 NXP
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __BITOPS_H__
+#define __BITOPS_H__
+
+#include <Library/DebugLib.h>
+
+#define MASK_LOWER_16              0xFFFF0000
+#define MASK_UPPER_16              0x0000FFFF
+#define MASK_LOWER_8               0xFF000000
+#define MASK_UPPER_8               0x000000FF
+
+/*
+ * Returns the bit mask for a bit index from 0 to 31
+ */
+#define BIT(_BitIndex)         (0x1u << (_BitIndex))
+
+/**
+ * Upper32Bits - return bits 32-63 of a number
+ * @N: the number we're accessing
+ *
+ * A basic shift-right of a 64- or 32-bit quantity.  Use this to suppress
+ * the "right shift count >= width of type" warning when that quantity is
+ * 32-bits.
+ */
+#define Upper32Bits(N) ((UINT32)(((N) >> 16) >> 16))
+
+/**
+ * Lower32Bits - return bits 0-31 of a number
+ * @N: the number we're accessing
+ */
+#define Lower32Bits(N) ((UINT32)(N))
+
+
+/*
+ * Stores a value for a given bit field in 32-bit '_Container'
+ */
+
+#define SET_BIT_FIELD32(_Container, _BitShift, _BitWidth, _Value) \
+  __SET_BIT_FIELD32(_Container,                                   \
+      __GEN_BIT_FIELD_MASK32(_BitShift, _BitWidth),               \
+      _BitShift,                                                  \
+      _Value)
+
+#define __SET_BIT_FIELD32(_Container, _BitMask, _BitShift, _Value)      \
+  do {                                                                  \
+    (_Container) &= ~(_BitMask);                                        \
+    if ((_Value) != 0) {                                                \
+      ASSERT(((UINT32)(_Value) << (_BitShift)) <= (_BitMask));          \
+      (_Container) |=                                                   \
+      ((UINT32)(_Value) << (_BitShift)) & (_BitMask);                   \
+    }                                                                   \
+  } while (0)
+
+/*
+ * Extracts the value for a given bit field in 32-bit _Container
+ */
+
+#define GET_BIT_FIELD32(_Container, _BitShift, _BitWidth) \
+  __GET_BIT_FIELD32(_Container,                           \
+      __GEN_BIT_FIELD_MASK32(_BitShift, _BitWidth),       \
+      _BitShift)
+
+#define __GET_BIT_FIELD32(_Container, _BitMask, _BitShift)  \
+  (((UINT32)(_Container) & (_BitMask)) >> (_BitShift))
+
+#define __GEN_BIT_FIELD_MASK32(_BitShift, _BitWidth)        \
+  ((_BitWidth) < 32 ?                                       \
+   (((UINT32)1 << (_BitWidth)) - 1) << (_BitShift) :        \
+   ~(UINT32)0)
+
+/*
+ *Stores a value for a given bit field in 64-bit '_Container'
+ */
+#define SET_BIT_FIELD64(_Container, _BitShift, _BitWidth, _Value) \
+  __SET_BIT_FIELD64(_Container,                                   \
+      __GEN_BIT_FIELD_MASK64(_BitShift, _BitWidth),               \
+      _BitShift,                                                  \
+      _Value)
+
+#define __SET_BIT_FIELD64(_Container, _BitMask, _BitShift, _Value)  \
+  do {                                                              \
+    (_Container) &= ~(_BitMask);                                    \
+    if ((_Value) != 0) {                                            \
+      ASSERT(((UINT64)(_Value) << (_BitShift)) <= (_BitMask));      \
+      (_Container) |=                                               \
+      ((UINT64)(_Value) << (_BitShift)) & (_BitMask);               \
+    }                                                               \
+  } while (0)
+
+/*
+ * Extracts the value for a given bit field in 64-bit _Container
+ */
+#define GET_BIT_FIELD64(_Container, _BitShift, _BitWidth) \
+  __GET_BIT_FIELD64(_Container,                           \
+      __GEN_BIT_FIELD_MASK64(_BitShift, _BitWidth),       \
+      _BitShift)
+
+#define __GET_BIT_FIELD64(_Container, _BitMask, _BitShift) \
+  (((UINT64)(_Container) & (_BitMask)) >> (_BitShift))
+
+#define __GEN_BIT_FIELD_MASK64(_BitShift, _BitWidth)       \
+  ((_BitWidth) < 64 ?                                      \
+   (((UINT64)1 << (_BitWidth)) - 1) << (_BitShift) :       \
+   ~(UINT64)0)
+
+/**
+
+ Test If the Destination buffer sets (0->1) or clears (1->0) any bit in Source buffer ?
+
+ @param[in]  Source       Source Buffer Pointer
+ @param[in]  Destination  Destination Buffer Pointer
+ @param[in]  NumBytes     Bytes to Compare
+ @param[in]  Set          True : Test Weather Destination buffer sets any bit in Source buffer ?
+                          False : Test Weather Destination buffer clears any bit in Source buffer ?
+
+ @retval     TRUE         Destination buffer sets/clear a bit in source buffer.
+ @retval     FALSE        Destination buffer doesn't sets/clear bit in source buffer.
+
+**/
+STATIC
+inline
+BOOLEAN
+TestBitSetClear (
+  IN  VOID    *Source,
+  IN  VOID    *Destination,
+  IN  UINTN   NumBytes,
+  IN  BOOLEAN Set
+  )
+{
+  UINTN Index = 0;
+  VOID* Buffer;
+
+  if (Set) {
+    Buffer = Destination;
+  } else {
+    Buffer = Source;
+  }
+
+  while (Index < NumBytes) {
+    if ((NumBytes - Index) >= 8) {
+      if ((*((UINT64*)(Source+Index)) ^ *((UINT64*)(Destination+Index))) & *((UINT64*)(Buffer+Index))) {
+        return TRUE;
+      }
+      Index += 8;
+    } else if ((NumBytes - Index) >= 4) {
+      if ((*((UINT32*)(Source+Index)) ^ *((UINT32*)(Destination+Index))) & *((UINT32*)(Buffer+Index))) {
+        return TRUE;
+      }
+      Index += 4;
+    } else if ((NumBytes - Index) >= 2) {
+      if ((*((UINT16*)(Source+Index)) ^ *((UINT16*)(Destination+Index))) & *((UINT16*)(Buffer+Index))) {
+        return TRUE;
+      }
+      Index += 2;
+    } else if ((NumBytes - Index) >= 1) {
+      if ((*((UINT8*)(Source+Index)) ^ *((UINT8*)(Destination+Index))) & *((UINT8*)(Buffer+Index))) {
+        return TRUE;
+      }
+      Index += 1;
+    }
+  }
+  return FALSE;
+}
+
+#endif
diff --git a/Silicon/NXP/Chassis/Chassis.c b/Silicon/NXP/Chassis/Chassis.c
new file mode 100644
index 0000000..fb5c1c4
--- /dev/null
+++ b/Silicon/NXP/Chassis/Chassis.c
@@ -0,0 +1,413 @@
+/** @file
+  SoC specific Library containg functions to initialize various SoC components
+
+  Copyright (c) 2017 NXP
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution. The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Library/BaseLib.h>
+#include <Library/BeIoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PrintLib.h>
+#include <Library/SerialPortLib.h>
+
+#include <Soc.h>
+
+#include "Chassis.h"
+
+UINT32
+EFIAPI
+GurRead (
+  IN  UINTN     Address
+  )
+{
+  if (FixedPcdGetBool (PcdGurBigEndian)) {
+    return BeMmioRead32 (Address);
+  } else {
+    return MmioRead32 (Address);
+  }
+}
+
+/*
+ *  Structure to list available SOCs.
+ */
+STATIC CPU_TYPE CpuTypeList[] = {
+  CPU_TYPE_ENTRY (LS1043A, LS1043A, 4),
+};
+
+/*
+ * Return the number of bits set
+ */
+STATIC
+inline
+UINTN
+CountSetBits (
+  IN  UINTN  Num
+  )
+{
+  UINTN Count;
+
+  Count = 0;
+
+  while (Num) {
+    Count += Num & 1;
+    Num >>= 1;
+  }
+
+  return Count;
+}
+
+UINT32
+InitiatorType (
+  IN UINT32 Cluster,
+  IN UINTN  InitId
+  )
+{
+  CCSR_GUR *GurBase;
+  UINT32   Idx;
+  UINT32   Type;
+
+  GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+  Idx = (Cluster >> (InitId * 8)) & TP_CLUSTER_INIT_MASK;
+  Type = GurRead ((UINTN)&GurBase->TpItyp[Idx]);
+
+  if (Type & TP_ITYP_AV_MASK) {
+    return Type;
+  }
+
+  return 0;
+}
+
+/*
+ *  Return the mask for number of cores on this SOC.
+ */
+UINT32
+CpuMask (
+  VOID
+  )
+{
+  CCSR_GUR  *GurBase;
+  UINTN     ClusterIndex;
+  UINTN     Count;
+  UINT32    Cluster;
+  UINT32    Type;
+  UINT32    Mask;
+  UINTN     InitiatorIndex;
+
+  GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+  ClusterIndex = 0;
+  Count = 0;
+  Mask = 0;
+
+  do {
+    Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
+    for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
+      Type = InitiatorType (Cluster, InitiatorIndex);
+      if (Type) {
+        if (TP_ITYP_TYPE_MASK (Type) == TP_ITYP_TYPE_ARM)
+          Mask |= 1 << Count;
+        Count++;
+      }
+    }
+    ClusterIndex++;
+  } while (CHECK_CLUSTER (Cluster));
+
+  return Mask;
+}
+
+/*
+ *  Return the number of cores on this SOC.
+ */
+UINTN
+CpuNumCores (
+  VOID
+  )
+{
+    return CountSetBits (CpuMask ());
+}
+
+UINT32
+QoriqCoreToType (
+  IN UINTN Core
+  )
+{
+  CCSR_GUR  *GurBase;
+  UINTN     ClusterIndex;
+  UINTN     Count;
+  UINT32    Cluster;
+  UINT32    Type;
+  UINTN     InitiatorIndex;
+
+  GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+  ClusterIndex = 0;
+  Count = 0;
+
+  do {
+    Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
+    for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
+      Type = InitiatorType (Cluster, InitiatorIndex);
+      if (Type) {
+        if (Count == Core)
+          return Type;
+        Count++;
+      }
+    }
+    ClusterIndex++;
+  } while (CHECK_CLUSTER (Cluster));
+
+  return -1;      /* cannot identify the cluster */
+}
+
+/*
+ * Print CPU information
+ */
+VOID
+PrintCpuInfo (
+  VOID
+  )
+{
+  SYS_INFO SysInfo;
+  UINTN    CoreIndex;
+  UINTN    Core;
+  UINT32   Type;
+  CHAR8    Buffer[100];
+  UINTN    CharCount;
+
+  GetSysInfo (&SysInfo);
+  CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "Clock Configuration:");
+  SerialPortWrite ((UINT8 *) Buffer, CharCount);
+
+  ForEachCpu (CoreIndex, Core, CpuNumCores (), CpuMask ()) {
+    if (!(CoreIndex % 3)) {
+      CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "\n      ");
+      SerialPortWrite ((UINT8 *) Buffer, CharCount);
+    }
+
+    Type = TP_ITYP_VERSION (QoriqCoreToType (Core));
+    CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "CPU%d(%a):%-4d MHz  ", Core,
+        Type == TY_ITYP_VERSION_A7 ? "A7 " :
+        (Type == TY_ITYP_VERSION_A53 ? "A53" :
+         (Type == TY_ITYP_VERSION_A57 ? "A57" :
+          (Type == TY_ITYP_VERSION_A72 ? "A72" : " Unknown Core "))),
+        SysInfo.FreqProcessor[Core] / MEGA_HZ);
+    SerialPortWrite ((UINT8 *) Buffer, CharCount);
+  }
+
+  CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "\n      Bus:      %-4d MHz  ",
+                           SysInfo.FreqSystemBus / MEGA_HZ);
+  SerialPortWrite ((UINT8 *) Buffer, CharCount);
+  CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "DDR:      %-4d MT/s",
+                           SysInfo.FreqDdrBus / MEGA_HZ);
+  SerialPortWrite ((UINT8 *) Buffer, CharCount);
+
+  if (SysInfo.FreqFman[0] != 0) {
+    CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "\n      FMAN:     %-4d MHz  ",
+                             SysInfo.FreqFman[0] / MEGA_HZ);
+    SerialPortWrite ((UINT8 *) Buffer, CharCount);
+  }
+
+  CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "\n");
+  SerialPortWrite ((UINT8 *) Buffer, CharCount);
+}
+
+/*
+ * Return system bus frequency
+ */
+UINT64
+GetBusFrequency (
+   VOID
+  )
+{
+  SYS_INFO SocSysInfo;
+
+  GetSysInfo (&SocSysInfo);
+
+  return SocSysInfo.FreqSystemBus;
+}
+
+/*
+ * Return SDXC bus frequency
+ */
+UINT64
+GetSdxcFrequency (
+   VOID
+  )
+{
+  SYS_INFO SocSysInfo;
+
+  GetSysInfo (&SocSysInfo);
+
+  return SocSysInfo.FreqSdhc;
+}
+
+/*
+ * Print Soc information
+ */
+VOID
+PrintSoc (
+  VOID
+  )
+{
+  CHAR8    Buf[16];
+  CCSR_GUR *GurBase;
+  UINTN    Count;
+  UINTN    Svr;
+  UINTN    Ver;
+
+  GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+
+  Buf[0] = L'\0';
+  Svr = GurRead ((UINTN)&GurBase->Svr);
+  Ver = SVR_SOC_VER (Svr);
+
+  for (Count = 0; Count < ARRAY_SIZE (CpuTypeList); Count++)
+    if ((CpuTypeList[Count].SocVer & SVR_WO_E) == Ver) {
+      AsciiStrCpy (Buf, (CONST CHAR8 *)CpuTypeList[Count].Name);
+
+      if (IS_E_PROCESSOR (Svr)) {
+        AsciiStrCat (Buf, (CONST CHAR8 *)"E");
+      }
+      break;
+    }
+
+  if (Count == ARRAY_SIZE (CpuTypeList)) {
+    AsciiStrCpy (Buf, (CONST CHAR8 *)"unknown");
+  }
+
+  DEBUG ((DEBUG_INFO, "SoC: %a (0x%x); Rev %d.%d\n",
+         Buf, Svr, SVR_MAJOR (Svr), SVR_MINOR (Svr)));
+
+  return;
+}
+
+/*
+ * Dump RCW (Reset Control Word) on console
+ */
+VOID
+PrintRCW (
+  VOID
+  )
+{
+  CCSR_GUR *Base;
+  UINTN    Count;
+  CHAR8    Buffer[100];
+  UINTN    CharCount;
+
+  Base = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+
+  /*
+   * Display the RCW, so that no one gets confused as to what RCW
+   * we're actually using for this boot.
+   */
+
+  CharCount = AsciiSPrint (Buffer, sizeof (Buffer),
+               "Reset Configuration Word (RCW):");
+  SerialPortWrite ((UINT8 *) Buffer, CharCount);
+  for (Count = 0; Count < ARRAY_SIZE(Base->RcwSr); Count++) {
+    UINT32 Rcw = BeMmioRead32((UINTN)&Base->RcwSr[Count]);
+
+    if ((Count % 4) == 0) {
+      CharCount = AsciiSPrint (Buffer, sizeof (Buffer),
+                   "\n       %08x:", Count * 4);
+      SerialPortWrite ((UINT8 *) Buffer, CharCount);
+    }
+
+    CharCount = AsciiSPrint (Buffer, sizeof (Buffer), " %08x", Rcw);
+    SerialPortWrite ((UINT8 *) Buffer, CharCount);
+  }
+
+  CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "\n");
+  SerialPortWrite ((UINT8 *) Buffer, CharCount);
+}
+
+/*
+ * Setup SMMU in bypass mode
+ * and also set its pagesize
+ */
+VOID
+SmmuInit (
+  VOID
+  )
+{
+  UINT32 Value;
+
+  /* set pagesize as 64K and ssmu-500 in bypass mode */
+  Value = (MmioRead32 ((UINTN)SMMU_REG_SACR) | SACR_PAGESIZE_MASK);
+  MmioWrite32 ((UINTN)SMMU_REG_SACR, Value);
+
+  Value = (MmioRead32 ((UINTN)SMMU_REG_SCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
+  MmioWrite32 ((UINTN)SMMU_REG_SCR0, Value);
+
+  Value = (MmioRead32 ((UINTN)SMMU_REG_NSCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
+  MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value);
+}
+
+/*
+ * Return current Soc Name form CpuTypeList
+ */
+CHAR8 *
+GetSocName (
+  VOID
+  )
+{
+  UINT8     Count;
+  UINTN     Svr;
+  UINTN     Ver;
+  CCSR_GUR  *GurBase;
+
+  GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+
+  Svr = GurRead ((UINTN)&GurBase->Svr);
+  Ver = SVR_SOC_VER (Svr);
+
+  for (Count = 0; Count < ARRAY_SIZE (CpuTypeList); Count++) {
+    if ((CpuTypeList[Count].SocVer & SVR_WO_E) == Ver) {
+      return (CHAR8 *)CpuTypeList[Count].Name;
+    }
+  }
+
+  return NULL;
+}
+
+/*
+ * Return Baud divisor on basis of Baudrate
+ */
+UINT32
+CalculateBaudDivisor (
+  IN UINT64 BaudRate
+  )
+{
+  SYS_INFO SocSysInfo;
+  UINTN DUartClk;
+
+  GetSysInfo(&SocSysInfo);
+  DUartClk = SocSysInfo.FreqSystemBus/PcdGet32(PcdPlatformFreqDiv);
+
+  return ((DUartClk)/(BaudRate * 16));
+}
+
+/*
+ * Return I2c bus frequency
+ */
+UINT32
+CalculateI2cClockRate (
+  VOID
+  )
+{
+  SYS_INFO SocSysInfo;
+
+  GetSysInfo (&SocSysInfo);
+
+  return SocSysInfo.FreqSystemBus;
+}
diff --git a/Silicon/NXP/Chassis/Chassis.h b/Silicon/NXP/Chassis/Chassis.h
new file mode 100644
index 0000000..b75a9a0
--- /dev/null
+++ b/Silicon/NXP/Chassis/Chassis.h
@@ -0,0 +1,144 @@
+/** @file
+*  Header defining the Base addresses, sizes, flags etc for chassis 1
+*
+*  Copyright 2017 NXP
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __CHASSIS_H__
+#define __CHASSIS_H__
+
+#define TP_ITYP_AV_MASK            0x00000001  /* Initiator available */
+#define TP_ITYP_TYPE_MASK(x)       (((x) & 0x6) >> 1) /* Initiator Type */
+#define TP_ITYP_TYPE_ARM           0x0
+#define TP_ITYP_TYPE_PPC           0x1
+#define TP_ITYP_TYPE_OTHER         0x2  /* StarCore DSP */
+#define TP_ITYP_TYPE_HA            0x3  /* HW Accelerator */
+#define TP_ITYP_THDS(x)            (((x) & 0x18) >> 3)  /* # threads */
+#define TP_ITYP_VERSION(x)         (((x) & 0xe0) >> 5)  /* Initiator Version */
+#define TP_CLUSTER_INIT_MASK       0x0000003f  /* initiator mask */
+#define TP_INIT_PER_CLUSTER        4
+
+#define TY_ITYP_VERSION_A7         0x1
+#define TY_ITYP_VERSION_A53        0x2
+#define TY_ITYP_VERSION_A57        0x3
+#define TY_ITYP_VERSION_A72        0x4
+
+STATIC
+inline
+UINTN
+CpuMaskNext (
+  IN  UINTN  Cpu,
+  IN  UINTN  Mask
+  )
+{
+  for (Cpu++; !((1 << Cpu) & Mask); Cpu++)
+    ;
+
+  return Cpu;
+}
+
+#define ForEachCpu(Iter, Cpu, NumCpus, Mask) \
+  for (Iter = 0, Cpu = CpuMaskNext(-1, Mask); \
+    Iter < NumCpus; \
+    Iter++, Cpu = CpuMaskNext(Cpu, Mask)) \
+
+#define CPU_TYPE_ENTRY(N, V, NC) \
+           { .Name = #N, .SocVer = SVR_##V, .NumCores = (NC)}
+
+#define SVR_WO_E                    0xFFFFFE
+#define SVR_LS1043A                 0x879200
+
+#define SVR_MAJOR(svr)              (((svr) >> 4) & 0xf)
+#define SVR_MINOR(svr)              (((svr) >> 0) & 0xf)
+#define SVR_SOC_VER(svr)            (((svr) >> 8) & SVR_WO_E)
+#define IS_E_PROCESSOR(svr)         (!((svr >> 8) & 0x1))
+
+#define MEGA_HZ                     1000000
+
+typedef struct {
+  CHAR8  Name[16];
+  UINT32 SocVer;
+  UINT32 NumCores;
+} CPU_TYPE;
+
+typedef struct {
+  UINTN CpuClk;  /* CPU clock in Hz! */
+  UINTN BusClk;
+  UINTN MemClk;
+  UINTN PciClk;
+  UINTN SdhcClk;
+} SOC_CLOCK_INFO;
+
+/*
+ * Print Soc information
+ */
+VOID
+PrintSoc (
+  VOID
+  );
+
+/*
+ * Initialize Clock structure
+ */
+VOID
+ClockInit (
+  VOID
+  );
+
+/*
+ * Setup SMMU in bypass mode
+ * and also set its pagesize
+ */
+VOID
+SmmuInit (
+  VOID
+  );
+
+/*
+ * Print CPU information
+ */
+VOID
+PrintCpuInfo (
+  VOID
+  );
+
+/*
+ * Dump RCW (Reset Control Word) on console
+ */
+VOID
+PrintRCW (
+  VOID
+  );
+
+UINT32
+InitiatorType (
+  IN UINT32 Cluster,
+  IN UINTN InitId
+  );
+
+/*
+ *  Return the mask for number of cores on this SOC.
+ */
+UINT32
+CpuMask (
+  VOID
+  );
+
+/*
+ *  Return the number of cores on this SOC.
+ */
+UINTN
+CpuNumCores (
+  VOID
+  );
+
+#endif /* __CHASSIS_H__ */
diff --git a/Silicon/NXP/Chassis/Chassis2/Chassis2.dec b/Silicon/NXP/Chassis/Chassis2/Chassis2.dec
new file mode 100644
index 0000000..c7fc65b
--- /dev/null
+++ b/Silicon/NXP/Chassis/Chassis2/Chassis2.dec
@@ -0,0 +1,19 @@
+# @file
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+  DEC_SPECIFICATION              = 0x00010005
+
+[Includes]
+  .
diff --git a/Silicon/NXP/Chassis/Chassis2/SerDes.h b/Silicon/NXP/Chassis/Chassis2/SerDes.h
new file mode 100644
index 0000000..c27e7e6
--- /dev/null
+++ b/Silicon/NXP/Chassis/Chassis2/SerDes.h
@@ -0,0 +1,69 @@
+/** SerDes.h
+ The Header file of SerDes Module for Chassis 2
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __SERDES_H__
+#define __SERDES_H__
+
+#include <Uefi/UefiBaseType.h>
+
+#define SRDS_MAX_LANES     4
+
+typedef enum {
+  NONE = 0,
+  PCIE1,
+  PCIE2,
+  PCIE3,
+  SATA,
+  SGMII_FM1_DTSEC1,
+  SGMII_FM1_DTSEC2,
+  SGMII_FM1_DTSEC5,
+  SGMII_FM1_DTSEC6,
+  SGMII_FM1_DTSEC9,
+  SGMII_FM1_DTSEC10,
+  QSGMII_FM1_A,
+  XFI_FM1_MAC9,
+  XFI_FM1_MAC10,
+  SGMII_2500_FM1_DTSEC2,
+  SGMII_2500_FM1_DTSEC5,
+  SGMII_2500_FM1_DTSEC9,
+  SGMII_2500_FM1_DTSEC10,
+  SERDES_PRTCL_COUNT
+} SERDES_PROTOCOL;
+
+typedef enum {
+  SRDS_1  = 0,
+  SRDS_2,
+  SRDS_MAX_NUM
+} SERDES_NUMBER;
+
+typedef struct {
+  UINT16 Protocol;
+  UINT8  SrdsLane[SRDS_MAX_LANES];
+} SERDES_CONFIG;
+
+typedef
+VOID
+SERDES_PROBE_LANES_CALLBACK (
+  IN SERDES_PROTOCOL LaneProtocol,
+  IN VOID *Arg
+  );
+
+VOID
+SerDesProbeLanes(
+  IN SERDES_PROBE_LANES_CALLBACK *SerDesLaneProbeCallback,
+  IN VOID *Arg
+  );
+
+#endif /* __SERDES_H */
diff --git a/Silicon/NXP/Chassis/Chassis2/Soc.c b/Silicon/NXP/Chassis/Chassis2/Soc.c
new file mode 100644
index 0000000..ff9575a
--- /dev/null
+++ b/Silicon/NXP/Chassis/Chassis2/Soc.c
@@ -0,0 +1,145 @@
+/** @Soc.c
+  SoC specific Library containg functions to initialize various SoC components
+
+  Copyright 2017 NXP
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution. The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Chassis.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib/MemLibInternals.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PrintLib.h>
+#include <Library/SerialPortLib.h>
+
+#include "Soc.h"
+
+VOID
+GetSysInfo (
+  OUT SYS_INFO *PtrSysInfo
+  )
+{
+  CCSR_GUR     *GurBase;
+  CCSR_CLOCK   *ClkBase;
+  UINTN        CpuIndex;
+  UINT32       TempRcw;
+  UINT32       CPllSel;
+  UINT32       CplxPll;
+  CONST UINT8  CoreCplxPll[8] = {
+    [0] = 0,    /* CC1 PPL / 1 */
+    [1] = 0,    /* CC1 PPL / 2 */
+    [4] = 1,    /* CC2 PPL / 1 */
+    [5] = 1,    /* CC2 PPL / 2 */
+  };
+
+  CONST UINT8  CoreCplxPllDivisor[8] = {
+    [0] = 1,    /* CC1 PPL / 1 */
+    [1] = 2,    /* CC1 PPL / 2 */
+    [4] = 1,    /* CC2 PPL / 1 */
+    [5] = 2,    /* CC2 PPL / 2 */
+  };
+
+  UINTN        PllCount;
+  UINTN        FreqCPll[NUM_CC_PLLS];
+  UINTN        PllRatio[NUM_CC_PLLS];
+  UINTN        SysClk;
+
+  GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+  ClkBase = (VOID *)PcdGet64 (PcdClkBaseAddr);
+  SysClk = CLK_FREQ;
+
+  InternalMemZeroMem(PtrSysInfo, sizeof (SYS_INFO));
+
+  PtrSysInfo->FreqSystemBus = SysClk;
+  PtrSysInfo->FreqDdrBus = SysClk;
+
+  PtrSysInfo->FreqSystemBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
+                CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
+                CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
+  PtrSysInfo->FreqDdrBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
+                CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
+                CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
+
+  for (PllCount = 0; PllCount < NUM_CC_PLLS; PllCount++) {
+    PllRatio[PllCount] = (GurRead ((UINTN)&ClkBase->PllCgSr[PllCount].PllCnGSr) >> 1) & 0xff;
+    if (PllRatio[PllCount] > 4) {
+      FreqCPll[PllCount] = SysClk * PllRatio[PllCount];
+    } else {
+      FreqCPll[PllCount] = PtrSysInfo->FreqSystemBus * PllRatio[PllCount];
+    }
+  }
+
+  for (CpuIndex = 0; CpuIndex < MAX_CPUS; CpuIndex++) {
+    CPllSel = (GurRead ((UINTN)&ClkBase->ClkcSr[CpuIndex].ClkCnCSr) >> 27) & 0xf;
+    CplxPll = CoreCplxPll[CPllSel];
+
+    PtrSysInfo->FreqProcessor[CpuIndex] = FreqCPll[CplxPll] / CoreCplxPllDivisor[CPllSel];
+  }
+
+  TempRcw = GurRead ((UINTN)&GurBase->RcwSr[7]);
+  switch ((TempRcw & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
+  case 2:
+    PtrSysInfo->FreqFman[0] = FreqCPll[0] / 2;
+    break;
+  case 3:
+    PtrSysInfo->FreqFman[0] = FreqCPll[0] / 3;
+    break;
+  case 4:
+    PtrSysInfo->FreqFman[0] = FreqCPll[0] / 4;
+    break;
+  case 5:
+    PtrSysInfo->FreqFman[0] = PtrSysInfo->FreqSystemBus;
+    break;
+  case 6:
+    PtrSysInfo->FreqFman[0] = FreqCPll[1] / 2;
+    break;
+  case 7:
+    PtrSysInfo->FreqFman[0] = FreqCPll[1] / 3;
+    break;
+  default:
+    DEBUG ((DEBUG_WARN, "Error: Unknown FMan1 clock select!\n"));
+    break;
+  }
+  PtrSysInfo->FreqSdhc = PtrSysInfo->FreqSystemBus/PcdGet32 (PcdPlatformFreqDiv);
+  PtrSysInfo->FreqQman = PtrSysInfo->FreqSystemBus/PcdGet32 (PcdPlatformFreqDiv);
+}
+
+/**
+  Function to initialize SoC specific constructs
+  // CPU Info
+  // SoC Personality
+  // Board Personality
+  // RCW prints
+ **/
+VOID
+SocInit (
+  VOID
+  )
+{
+  CHAR8 Buffer[100];
+  UINTN CharCount;
+
+  SmmuInit ();
+
+  // Initialize the Serial Port
+  SerialPortInitialize ();
+  CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "\nUEFI firmware (version %s built at %a on %a)\n\r",
+    (CHAR16*)PcdGetPtr (PcdFirmwareVersionString), __TIME__, __DATE__);
+  SerialPortWrite ((UINT8 *) Buffer, CharCount);
+
+  PrintCpuInfo ();
+  PrintRCW ();
+
+  return;
+}
diff --git a/Silicon/NXP/Chassis/Chassis2/Soc.h b/Silicon/NXP/Chassis/Chassis2/Soc.h
new file mode 100644
index 0000000..f7bfab7
--- /dev/null
+++ b/Silicon/NXP/Chassis/Chassis2/Soc.h
@@ -0,0 +1,376 @@
+/** Soc.h
+*  Header defining the Base addresses, sizes, flags etc for chassis 1
+*
+*  Copyright 2017 NXP
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __SOC_H__
+#define __SOC_H__
+
+#define HWA_CGA_M1_CLK_SEL         0xe0000000
+#define HWA_CGA_M1_CLK_SHIFT       29
+
+#define TP_CLUSTER_EOC_MASK        0xc0000000  /* end of clusters mask */
+#define NUM_CC_PLLS                2
+#define CLK_FREQ                   100000000
+#define MAX_CPUS                   4
+#define NUM_FMAN                   1
+#define CHECK_CLUSTER(Cluster)    ((Cluster & TP_CLUSTER_EOC_MASK) == 0x0)
+
+/* RCW SERDES MACRO */
+#define RCWSR_INDEX                4
+#define RCWSR_SRDS1_PRTCL_MASK     0xffff0000
+#define RCWSR_SRDS1_PRTCL_SHIFT    16
+#define RCWSR_SRDS2_PRTCL_MASK     0x0000ffff
+#define RCWSR_SRDS2_PRTCL_SHIFT    0
+
+/* SMMU Defintions */
+#define SMMU_BASE_ADDR             0x09000000
+#define SMMU_REG_SCR0              (SMMU_BASE_ADDR + 0x0)
+#define SMMU_REG_SACR              (SMMU_BASE_ADDR + 0x10)
+#define SMMU_REG_IDR1              (SMMU_BASE_ADDR + 0x24)
+#define SMMU_REG_NSCR0             (SMMU_BASE_ADDR + 0x400)
+#define SMMU_REG_NSACR             (SMMU_BASE_ADDR + 0x410)
+
+#define SCR0_USFCFG_MASK           0x00000400
+#define SCR0_CLIENTPD_MASK         0x00000001
+#define SACR_PAGESIZE_MASK         0x00010000
+#define IDR1_PAGESIZE_MASK         0x80000000
+
+typedef struct {
+  UINTN FreqProcessor[MAX_CPUS];
+  UINTN FreqSystemBus;
+  UINTN FreqDdrBus;
+  UINTN FreqLocalBus;
+  UINTN FreqSdhc;
+  UINTN FreqFman[NUM_FMAN];
+  UINTN FreqQman;
+} SYS_INFO;
+
+typedef enum {
+  ARM_CLK = 0,
+  BUS_CLK,
+  UART_CLK,
+  ESDHC_CLK,
+  I2C_CLK,
+  DSPI_CLK,
+} PERIPHERAL_CLOCK;
+
+/* Device Configuration and Pin Control */
+typedef struct {
+  UINT32   PorSr1;         /* POR status 1 */
+#define CHASSIS2_CCSR_PORSR1_RCW_MASK  0xFF800000
+  UINT32   PorSr2;         /* POR status 2 */
+  UINT8    Res008[0x20-0x8];
+  UINT32   GppOrCr1;       /* General-purpose POR configuration */
+  UINT32   GppOrCr2;
+  UINT32   DcfgFuseSr;    /* Fuse status register */
+  UINT8    Res02c[0x70-0x2c];
+  UINT32   DevDisr;        /* Device disable control */
+  UINT32   DevDisr2;       /* Device disable control 2 */
+  UINT32   DevDisr3;       /* Device disable control 3 */
+  UINT32   DevDisr4;       /* Device disable control 4 */
+  UINT32   DevDisr5;       /* Device disable control 5 */
+  UINT32   DevDisr6;       /* Device disable control 6 */
+  UINT32   DevDisr7;       /* Device disable control 7 */
+  UINT8    Res08c[0x94-0x8c];
+  UINT32   CoreDisrU;      /* uppper portion for support of 64 cores */
+  UINT32   CoreDisrL;      /* lower portion for support of 64 cores */
+  UINT8    Res09c[0xa0-0x9c];
+  UINT32   Pvr;            /* Processor version */
+  UINT32   Svr;            /* System version */
+  UINT32   Mvr;            /* Manufacturing version */
+  UINT8    Res0ac[0xb0-0xac];
+  UINT32   RstCr;          /* Reset control */
+  UINT32   RstRqPblSr;     /* Reset request preboot loader status */
+  UINT8    Res0b8[0xc0-0xb8];
+  UINT32   RstRqMr1;       /* Reset request mask */
+  UINT8    Res0c4[0xc8-0xc4];
+  UINT32   RstRqSr1;       /* Reset request status */
+  UINT8    Res0cc[0xd4-0xcc];
+  UINT32   RstRqWdTmrL;     /* Reset request WDT mask */
+  UINT8    Res0d8[0xdc-0xd8];
+  UINT32   RstRqWdtSrL;     /* Reset request WDT status */
+  UINT8    Res0e0[0xe4-0xe0];
+  UINT32   BrrL;            /* Boot release */
+  UINT8    Res0e8[0x100-0xe8];
+  UINT32   RcwSr[16];      /* Reset control word status */
+#define CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT  25
+#define CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK  0x1f
+#define CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT  16
+#define CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK  0x3f
+  UINT8    Res140[0x200-0x140];
+  UINT32   ScratchRw[4];   /* Scratch Read/Write */
+  UINT8    Res210[0x300-0x210];
+  UINT32   ScratcHw1R[4];  /* Scratch Read (Write once) */
+  UINT8    Res310[0x400-0x310];
+  UINT32   CrstSr[12];
+  UINT8    Res430[0x500-0x430];
+  /* PCI Express n Logical I/O Device Number register */
+  UINT32   DcfgCcsrPex1LiodNr;
+  UINT32   DcfgCcsrPex2LiodNr;
+  UINT32   DcfgCcsrPex3LiodNr;
+  UINT32   DcfgCcsrPex4LiodNr;
+  /* RIO n Logical I/O Device Number register */
+  UINT32   DcfgCcsrRio1LiodNr;
+  UINT32   DcfgCcsrRio2LiodNr;
+  UINT32   DcfgCcsrRio3LiodNr;
+  UINT32   DcfgCcsrRio4LiodNr;
+  /* USB Logical I/O Device Number register */
+  UINT32   DcfgCcsrUsb1LiodNr;
+  UINT32   DcfgCcsrUsb2LiodNr;
+  UINT32   DcfgCcsrUsb3LiodNr;
+  UINT32   DcfgCcsrUsb4LiodNr;
+  /* SD/MMC Logical I/O Device Number register */
+  UINT32   DcfgCcsrSdMmc1LiodNr;
+  UINT32   DcfgCcsrSdMmc2LiodNr;
+  UINT32   DcfgCcsrSdMmc3LiodNr;
+  UINT32   DcfgCcsrSdMmc4LiodNr;
+  /* RIO Message Unit Logical I/O Device Number register */
+  UINT32   DcfgCcsrRiomaintLiodNr;
+  UINT8    Res544[0x550-0x544];
+  UINT32   SataLiodNr[4];
+  UINT8    Res560[0x570-0x560];
+  UINT32   DcfgCcsrMisc1LiodNr;
+  UINT32   DcfgCcsrMisc2LiodNr;
+  UINT32   DcfgCcsrMisc3LiodNr;
+  UINT32   DcfgCcsrMisc4LiodNr;
+  UINT32   DcfgCcsrDma1LiodNr;
+  UINT32   DcfgCcsrDma2LiodNr;
+  UINT32   DcfgCcsrDma3LiodNr;
+  UINT32   DcfgCcsrDma4LiodNr;
+  UINT32   DcfgCcsrSpare1LiodNr;
+  UINT32   DcfgCcsrSpare2LiodNr;
+  UINT32   DcfgCcsrSpare3LiodNr;
+  UINT32   DcfgCcsrSpare4LiodNr;
+  UINT8    Res5a0[0x600-0x5a0];
+  UINT32   DcfgCcsrPblSr;
+  UINT32   PamuBypENr;
+  UINT32   DmaCr1;
+  UINT8    Res60c[0x610-0x60c];
+  UINT32   DcfgCcsrGenSr1;
+  UINT32   DcfgCcsrGenSr2;
+  UINT32   DcfgCcsrGenSr3;
+  UINT32   DcfgCcsrGenSr4;
+  UINT32   DcfgCcsrGenCr1;
+  UINT32   DcfgCcsrGenCr2;
+  UINT32   DcfgCcsrGenCr3;
+  UINT32   DcfgCcsrGenCr4;
+  UINT32   DcfgCcsrGenCr5;
+  UINT32   DcfgCcsrGenCr6;
+  UINT32   DcfgCcsrGenCr7;
+  UINT8    Res63c[0x658-0x63c];
+  UINT32   DcfgCcsrcGenSr1;
+  UINT32   DcfgCcsrcGenSr0;
+  UINT8    Res660[0x678-0x660];
+  UINT32   DcfgCcsrcGenCr1;
+  UINT32   DcfgCcsrcGenCr0;
+  UINT8    Res680[0x700-0x680];
+  UINT32   DcfgCcsrSrIoPstecr;
+  UINT32   DcfgCcsrDcsrCr;
+  UINT8    Res708[0x740-0x708]; /* add more registers when needed */
+  UINT32   TpItyp[64];          /* Topology Initiator Type Register */
+  struct {
+    UINT32 Upper;
+    UINT32 Lower;
+  } TpCluster[16];
+  UINT8    Res8c0[0xa00-0x8c0]; /* add more registers when needed */
+  UINT32   DcfgCcsrQmBmWarmRst;
+  UINT8    Resa04[0xa20-0xa04]; /* add more registers when needed */
+  UINT32   DcfgCcsrReserved0;
+  UINT32   DcfgCcsrReserved1;
+} CCSR_GUR;
+
+/* Supplemental Configuration Unit */
+typedef struct {
+  UINT8  Res000[0x070-0x000];
+  UINT32 Usb1Prm1Cr;
+  UINT32 Usb1Prm2Cr;
+  UINT32 Usb1Prm3Cr;
+  UINT32 Usb2Prm1Cr;
+  UINT32 Usb2Prm2Cr;
+  UINT32 Usb2Prm3Cr;
+  UINT32 Usb3Prm1Cr;
+  UINT32 Usb3Prm2Cr;
+  UINT32 Usb3Prm3Cr;
+  UINT8  Res094[0x100-0x094];
+  UINT32 Usb2Icid;
+  UINT32 Usb3Icid;
+  UINT8  Res108[0x114-0x108];
+  UINT32 DmaIcid;
+  UINT32 SataIcid;
+  UINT32 Usb1Icid;
+  UINT32 QeIcid;
+  UINT32 SdhcIcid;
+  UINT32 EdmaIcid;
+  UINT32 EtrIcid;
+  UINT32 Core0SftRst;
+  UINT32 Core1SftRst;
+  UINT32 Core2SftRst;
+  UINT32 Core3SftRst;
+  UINT8  Res140[0x158-0x140];
+  UINT32 AltCBar;
+  UINT32 QspiCfg;
+  UINT8  Res160[0x180-0x160];
+  UINT32 DmaMcr;
+  UINT8  Res184[0x188-0x184];
+  UINT32 GicAlign;
+  UINT32 DebugIcid;
+  UINT8  Res190[0x1a4-0x190];
+  UINT32 SnpCnfGcr;
+#define CCSR_SCFG_SNPCNFGCR_SECRDSNP         BIT31
+#define CCSR_SCFG_SNPCNFGCR_SECWRSNP         BIT30
+#define CCSR_SCFG_SNPCNFGCR_SATARDSNP        BIT23
+#define CCSR_SCFG_SNPCNFGCR_SATAWRSNP        BIT22
+#define CCSR_SCFG_SNPCNFGCR_USB1RDSNP        BIT21
+#define CCSR_SCFG_SNPCNFGCR_USB1WRSNP        BIT20
+#define CCSR_SCFG_SNPCNFGCR_USB2RDSNP        BIT15
+#define CCSR_SCFG_SNPCNFGCR_USB2WRSNP        BIT16
+#define CCSR_SCFG_SNPCNFGCR_USB3RDSNP        BIT13
+#define CCSR_SCFG_SNPCNFGCR_USB3WRSNP        BIT14
+  UINT8  Res1a8[0x1ac-0x1a8];
+  UINT32 IntpCr;
+  UINT8  Res1b0[0x204-0x1b0];
+  UINT32 CoreSrEnCr;
+  UINT8  Res208[0x220-0x208];
+  UINT32 RvBar00;
+  UINT32 RvBar01;
+  UINT32 RvBar10;
+  UINT32 RvBar11;
+  UINT32 RvBar20;
+  UINT32 RvBar21;
+  UINT32 RvBar30;
+  UINT32 RvBar31;
+  UINT32 LpmCsr;
+  UINT8  Res244[0x400-0x244];
+  UINT32 QspIdQScr;
+  UINT32 EcgTxcMcr;
+  UINT32 SdhcIoVSelCr;
+  UINT32 RcwPMuxCr0;
+  /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
+  *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
+  *Setting RCW PinMux Register bits 25-27 to select USB3_DRVVBUS
+  Setting RCW PinMux Register bits 29-31 to select USB3_DRVVBUS*/
+#define CCSR_SCFG_RCWPMUXCRO_SELCR_USB      0x3333
+  /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
+  *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
+  *Setting RCW PinMux Register bits 25-27 to select IIC4_SCL
+  Setting RCW PinMux Register bits 29-31 to select IIC4_SDA*/
+#define CCSR_SCFG_RCWPMUXCRO_NOT_SELCR_USB  0x3300
+  UINT32 UsbDrvVBusSelCr;
+#define CCSR_SCFG_USBDRVVBUS_SELCR_USB1      0x00000000
+#define CCSR_SCFG_USBDRVVBUS_SELCR_USB2      0x00000001
+#define CCSR_SCFG_USBDRVVBUS_SELCR_USB3      0x00000003
+  UINT32 UsbPwrFaultSelCr;
+#define CCSR_SCFG_USBPWRFAULT_INACTIVE       0x00000000
+#define CCSR_SCFG_USBPWRFAULT_SHARED         0x00000001
+#define CCSR_SCFG_USBPWRFAULT_DEDICATED      0x00000002
+#define CCSR_SCFG_USBPWRFAULT_USB3_SHIFT     4
+#define CCSR_SCFG_USBPWRFAULT_USB2_SHIFT     2
+#define CCSR_SCFG_USBPWRFAULT_USB1_SHIFT     0
+  UINT32 UsbRefclkSelcr1;
+  UINT32 UsbRefclkSelcr2;
+  UINT32 UsbRefclkSelcr3;
+  UINT8  Res424[0x600-0x424];
+  UINT32 ScratchRw[4];
+  UINT8  Res610[0x680-0x610];
+  UINT32 CoreBCr;
+  UINT8  Res684[0x1000-0x684];
+  UINT32 Pex1MsiIr;
+  UINT32 Pex1MsiR;
+  UINT8  Res1008[0x2000-0x1008];
+  UINT32 Pex2;
+  UINT32 Pex2MsiR;
+  UINT8  Res2008[0x3000-0x2008];
+  UINT32 Pex3MsiIr;
+  UINT32 Pex3MsiR;
+} CCSR_SCFG;
+
+#define USB_TXVREFTUNE        0x9
+#define USB_SQRXTUNE          0xFC7FFFFF
+#define USB_PCSTXSWINGFULL    0x47
+#define USB_PHY_RX_EQ_VAL_1   0x0000
+#define USB_PHY_RX_EQ_VAL_2   0x8000
+#define USB_PHY_RX_EQ_VAL_3   0x8003
+#define USB_PHY_RX_EQ_VAL_4   0x800b
+
+/*USB_PHY_SS memory map*/
+typedef struct {
+  UINT16 IpIdcodeLo;
+  UINT16 SupIdcodeHi;
+  UINT8  Res4[0x0006-0x0004];
+  UINT16 RtuneDebug;
+  UINT16 RtuneStat;
+  UINT16 SupSsPhase;
+  UINT16 SsFreq;
+  UINT8  ResE[0x0020-0x000e];
+  UINT16 Ateovrd;
+  UINT16 MpllOvrdInLo;
+  UINT8  Res24[0x0026-0x0024];
+  UINT16 SscOvrdIn;
+  UINT8  Res28[0x002A-0x0028];
+  UINT16 LevelOvrdIn;
+  UINT8  Res2C[0x0044-0x002C];
+  UINT16 ScopeCount;
+  UINT8  Res46[0x0060-0x0046];
+  UINT16 MpllLoopCtl;
+  UINT8  Res62[0x006C-0x0062];
+  UINT16 SscClkCntrl;
+  UINT8  Res6E[0x2002-0x006E];
+  UINT16 Lane0TxOvrdInHi;
+  UINT16 Lane0TxOvrdDrvLo;
+  UINT8  Res2006[0x200C-0x2006];
+  UINT16 Lane0RxOvrdInHi;
+  UINT8  Res200E[0x2022-0x200E];
+  UINT16 Lane0TxCmWaitTimeOvrd;
+  UINT8  Res2024[0x202A-0x2024];
+  UINT16 Lane0TxLbertCtl;
+  UINT16 Lane0RxLbertCtl;
+  UINT16 Lane0RxLbertErr;
+  UINT8  Res2030[0x205A-0x2030];
+  UINT16 Lane0TxAltBlock;
+} CCSR_USB_PHY;
+
+/* Clocking */
+typedef struct {
+  struct {
+    UINT32 ClkCnCSr;    /* core cluster n clock control status */
+    UINT8  Res004[0x0c];
+    UINT32 ClkcGHwAcSr; /* Clock generator n hardware accelerator */
+    UINT8 Res014[0x0c];
+  } ClkcSr[4];
+  UINT8  Res040[0x780]; /* 0x100 */
+  struct {
+    UINT32 PllCnGSr;
+    UINT8  Res804[0x1c];
+  } PllCgSr[2];
+  UINT8  Res840[0x1c0];
+  UINT32 ClkPCSr;  /* 0xa00 Platform clock domain control/status */
+  UINT8  Resa04[0x1fc];
+  UINT32 PllPGSr;  /* 0xc00 Platform PLL General Status */
+  UINT8  Resc04[0x1c];
+  UINT32 PllDGSr;  /* 0xc20 DDR PLL General Status */
+  UINT8  Resc24[0x3dc];
+} CCSR_CLOCK;
+
+VOID
+GetSysInfo (
+  OUT SYS_INFO *
+  );
+
+UINT32
+EFIAPI
+GurRead (
+  IN  UINTN     Address
+  );
+
+#endif /* __SOC_H__ */
diff --git a/Silicon/NXP/Chassis/LS1043aSocLib.inf b/Silicon/NXP/Chassis/LS1043aSocLib.inf
new file mode 100644
index 0000000..a7c6ee5
--- /dev/null
+++ b/Silicon/NXP/Chassis/LS1043aSocLib.inf
@@ -0,0 +1,47 @@
+#  @file
+#
+#  Copyright 2017 NXP
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = SocLib
+  FILE_GUID                      = e868c5ca-9729-43ae-bff4-438c67de8c68
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = SocLib
+
+[Packages]
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Platform/NXP/NxpQoriqLs.dec
+  Silicon/NXP/Chassis/Chassis2/Chassis2.dec
+  Silicon/NXP/LS1043A/LS1043A.dec
+
+[LibraryClasses]
+  BaseLib
+  BeIoLib
+  DebugLib
+  SerialPortLib
+
+[Sources.common]
+  Chassis.c
+  Chassis2/Soc.c
+  SerDes.c
+
+[FixedPcd]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
+  gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
+  gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled
+  gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
+  gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr
diff --git a/Silicon/NXP/Chassis/SerDes.c b/Silicon/NXP/Chassis/SerDes.c
new file mode 100644
index 0000000..55e95fb
--- /dev/null
+++ b/Silicon/NXP/Chassis/SerDes.c
@@ -0,0 +1,254 @@
+/** SerDes.c
+  Provides the basic interfaces for SerDes Module
+
+  Copyright 2017 NXP
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution. The full text of the license may be found
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Bitops.h>
+#include <Library/DebugLib.h>
+#include <SerDes.h>
+#include <SocSerDes.h>
+#include <Soc.h>
+#include <Uefi.h>
+
+/**
+  Function to get serdes Lane protocol corresponding to
+  serdes protocol.
+
+  @param  SerDes    Serdes number.
+  @param  Cfg       Serdes Protocol.
+  @param  Lane      Serdes Lane number.
+
+  @return           Serdes Lane protocol.
+
+**/
+STATIC
+SERDES_PROTOCOL
+GetSerDesPrtcl (
+  IN  INTN          SerDes,
+  IN  INTN          Cfg,
+  IN  INTN          Lane
+  )
+{
+  SERDES_CONFIG     *Config;
+
+  if (SerDes >= ARRAY_SIZE (SerDesConfigTbl)) {
+    return 0;
+  }
+
+  Config = SerDesConfigTbl[SerDes];
+  while (Config->Protocol) {
+    if (Config->Protocol == Cfg) {
+      return Config->SrdsLane[Lane];
+    }
+    Config++;
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Function to check if inputted protocol is a valid serdes protocol.
+
+  @param  SerDes                   Serdes number.
+  @param  Prtcl                    Serdes Protocol to be verified.
+
+  @return EFI_INVALID_PARAMETER    Input parameter in invalid.
+  @return EFI_NOT_FOUND            Serdes Protocol not a valid protocol.
+  @return EFI_SUCCESS              Serdes Protocol is a valid protocol.
+
+**/
+STATIC
+EFI_STATUS
+CheckSerDesPrtclValid (
+  IN  INTN      SerDes,
+  IN  UINT32    Prtcl
+  )
+{
+  SERDES_CONFIG *Config;
+  INTN          Cnt;
+
+  if (SerDes >= ARRAY_SIZE (SerDesConfigTbl)) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Config = SerDesConfigTbl[SerDes];
+  while (Config->Protocol) {
+    if (Config->Protocol == Prtcl) {
+      DEBUG ((DEBUG_INFO, "Protocol: %x Matched with the one in Table\n", Prtcl));
+      break;
+    }
+    Config++;
+  }
+
+  if (!Config->Protocol) {
+    return EFI_NOT_FOUND;
+  }
+
+  for (Cnt = 0; Cnt < SRDS_MAX_LANES; Cnt++) {
+    if (Config->SrdsLane[Cnt] != NONE) {
+      return EFI_SUCCESS;
+    }
+  }
+
+  return EFI_NOT_FOUND;
+}
+
+/**
+  Function to fill serdes map information.
+
+  @param  Srds                  Serdes number.
+  @param  SerdesProtocolMask    Serdes Protocol Mask.
+  @param  SerdesProtocolShift   Serdes Protocol shift value.
+  @param  SerDesPrtclMap        Pointer to Serdes Protocol map.
+
+**/
+STATIC
+VOID
+LSSerDesMap (
+  IN  UINT32                    Srds,
+  IN  UINT32                    SerdesProtocolMask,
+  IN  UINT32                    SerdesProtocolShift,
+  OUT UINT64                    *SerDesPrtclMap
+  )
+{
+  CCSR_GUR                      *Gur;
+  UINT32                        SrdsProt;
+  INTN                          Lane;
+  UINT32                        Flag;
+
+  Gur = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+  *SerDesPrtclMap = 0x0;
+  Flag = 0;
+
+  SrdsProt = GurRead ((UINTN)&Gur->RcwSr[RCWSR_INDEX]) & SerdesProtocolMask;
+  SrdsProt >>= SerdesProtocolShift;
+
+  DEBUG ((DEBUG_INFO, "Using SERDES%d Protocol: %d (0x%x)\n",
+                                   Srds + 1, SrdsProt, SrdsProt));
+
+  if (EFI_SUCCESS != CheckSerDesPrtclValid (Srds, SrdsProt)) {
+    DEBUG ((DEBUG_ERROR, "SERDES%d[PRTCL] = 0x%x is not valid\n",
+                                   Srds + 1, SrdsProt));
+    Flag++;
+  }
+
+  for (Lane = 0; Lane < SRDS_MAX_LANES; Lane++) {
+    SERDES_PROTOCOL LanePrtcl = GetSerDesPrtcl (Srds, SrdsProt, Lane);
+    if (LanePrtcl >= SERDES_PRTCL_COUNT) {
+      DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n", LanePrtcl));
+      Flag++;
+    } else {
+      *SerDesPrtclMap |= BIT (LanePrtcl);
+    }
+  }
+
+  if (Flag) {
+    DEBUG ((DEBUG_ERROR, "Could not configure SerDes module!!\n"));
+  } else {
+    DEBUG ((DEBUG_INFO, "Successfully configured SerDes module!!\n"));
+  }
+}
+
+STATIC
+VOID
+SerDesInstanceProbeLanes (
+  IN  UINT32                      Srds,
+  IN  UINT32                      SerdesProtocolMask,
+  IN  UINT32                      SerdesProtocolShift,
+  IN  SERDES_PROBE_LANES_CALLBACK *SerDesLaneProbeCallback,
+  IN  VOID                        *Arg
+  )
+{
+
+  CCSR_GUR                        *Gur;
+  UINT32                          SrdsProt;
+  INTN                            Lane;
+
+  Gur = (VOID *)PcdGet64 (PcdGutsBaseAddr);;
+
+  SrdsProt = GurRead ((UINTN)&Gur->RcwSr[RCWSR_INDEX]) & SerdesProtocolMask;
+  SrdsProt >>= SerdesProtocolShift;
+
+  /*
+   * Invoke callback for all lanes in the SerDes instance:
+   */
+  for (Lane = 0; Lane < SRDS_MAX_LANES; Lane++) {
+    SERDES_PROTOCOL LanePrtcl = GetSerDesPrtcl (Srds, SrdsProt, Lane);
+    if (LanePrtcl >= SERDES_PRTCL_COUNT || LanePrtcl < NONE) {
+      DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n", LanePrtcl));
+    }
+    else if (LanePrtcl != NONE) {
+      SerDesLaneProbeCallback (LanePrtcl, Arg);
+    }
+  }
+}
+
+VOID
+SerDesProbeLanes (
+  IN SERDES_PROBE_LANES_CALLBACK *SerDesLaneProbeCallback,
+  IN VOID                        *Arg
+  )
+{
+  SerDesInstanceProbeLanes (SRDS_1,
+                            RCWSR_SRDS1_PRTCL_MASK,
+                            RCWSR_SRDS1_PRTCL_SHIFT,
+                            SerDesLaneProbeCallback,
+                            Arg);
+
+  if (PcdGetBool (PcdSerdes2Enabled)) {
+   SerDesInstanceProbeLanes (SRDS_2,
+                             RCWSR_SRDS2_PRTCL_MASK,
+                             RCWSR_SRDS2_PRTCL_SHIFT,
+                             SerDesLaneProbeCallback,
+                             Arg);
+  }
+}
+
+/**
+  Function to return Serdes protocol map for all serdes available on board.
+
+  @param  SerDesPrtclMap   Pointer to Serdes protocl map.
+
+**/
+VOID
+GetSerdesProtocolMaps (
+  OUT UINT64               *SerDesPrtclMap
+  )
+{
+  LSSerDesMap (SRDS_1,
+               RCWSR_SRDS1_PRTCL_MASK,
+               RCWSR_SRDS1_PRTCL_SHIFT,
+               SerDesPrtclMap);
+
+  if (PcdGetBool (PcdSerdes2Enabled)) {
+    LSSerDesMap (SRDS_2,
+                 RCWSR_SRDS2_PRTCL_MASK,
+                 RCWSR_SRDS2_PRTCL_SHIFT,
+                 SerDesPrtclMap);
+  }
+
+}
+
+BOOLEAN
+IsSerDesLaneProtocolConfigured (
+  IN UINT64          SerDesPrtclMap,
+  IN SERDES_PROTOCOL Device
+  )
+{
+  if (Device >= SERDES_PRTCL_COUNT || Device < NONE) {
+    ASSERT (Device > NONE && Device < SERDES_PRTCL_COUNT);
+    DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol Device %d\n", Device));
+  }
+
+  return (SerDesPrtclMap & BIT (Device)) != 0 ;
+}
diff --git a/Silicon/NXP/LS1043A/Include/SocSerDes.h b/Silicon/NXP/LS1043A/Include/SocSerDes.h
new file mode 100644
index 0000000..cee0da9
--- /dev/null
+++ b/Silicon/NXP/LS1043A/Include/SocSerDes.h
@@ -0,0 +1,55 @@
+/** @file
+ The Header file of SerDes Module for LS1043A
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __SOC_SERDES_H__
+#define __SOC_SERDES_H__
+
+#include <SerDes.h>
+
+SERDES_CONFIG SerDes1ConfigTbl[] = {
+        /* SerDes 1 */
+  {0x1555, {XFI_FM1_MAC9, PCIE1, PCIE2, PCIE3 } },
+  {0x2555, {SGMII_2500_FM1_DTSEC9, PCIE1, PCIE2, PCIE3 } },
+  {0x4555, {QSGMII_FM1_A, PCIE1, PCIE2, PCIE3 } },
+  {0x4558, {QSGMII_FM1_A,  PCIE1, PCIE2, SATA } },
+  {0x1355, {XFI_FM1_MAC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } },
+  {0x2355, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } },
+  {0x3335, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, PCIE3 } },
+  {0x3355, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } },
+  {0x3358, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, SATA } },
+  {0x3555, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, PCIE3 } },
+  {0x3558, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, SATA } },
+  {0x7000, {PCIE1, PCIE1, PCIE1, PCIE1 } },
+  {0x9998, {PCIE1, PCIE2, PCIE3, SATA } },
+  {0x6058, {PCIE1, PCIE1, PCIE2, SATA } },
+  {0x1455, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE2, PCIE3 } },
+  {0x2455, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3 } },
+  {0x2255, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC2, PCIE2, PCIE3 } },
+  {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
+  {0x1460, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE3, PCIE3 } },
+  {0x2460, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE3, PCIE3 } },
+  {0x3460, {SGMII_FM1_DTSEC9, QSGMII_FM1_A, PCIE3, PCIE3 } },
+  {0x3455, {SGMII_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3 } },
+  {0x9960, {PCIE1, PCIE2, PCIE3, PCIE3 } },
+  {0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
+  {0x2533, {SGMII_2500_FM1_DTSEC9, PCIE1, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
+  {}
+};
+
+SERDES_CONFIG *SerDesConfigTbl[] = {
+  SerDes1ConfigTbl
+};
+
+#endif /* __SOC_SERDES_H */
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [PATCH edk2-platforms] [PATCH v3 4/9] Platform/NXP : Add support for DUART library
  2017-11-27 10:51 [PATCH edk2-platforms] [PATCH v3 0/9] Platform/NXP Meenakshi Aggarwal
                   ` (2 preceding siblings ...)
  2017-11-27 10:51 ` [PATCH edk2-platforms] [PATCH v3 3/9] SocLib : Add support for initialization of peripherals Meenakshi Aggarwal
@ 2017-11-27 10:51 ` Meenakshi Aggarwal
  2017-11-27 10:51 ` [PATCH edk2-platforms] [PATCH v3 5/9] Platform/NXP: Add support for I2c driver Meenakshi Aggarwal
                   ` (5 subsequent siblings)
  9 siblings, 0 replies; 25+ messages in thread
From: Meenakshi Aggarwal @ 2017-11-27 10:51 UTC (permalink / raw)
  To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
 Platform/NXP/Library/DUartPortLib/DUart.h          | 128 ++++++++
 Platform/NXP/Library/DUartPortLib/DUartPortLib.c   | 331 +++++++++++++++++++++
 Platform/NXP/Library/DUartPortLib/DUartPortLib.inf |  39 +++
 3 files changed, 498 insertions(+)
 create mode 100644 Platform/NXP/Library/DUartPortLib/DUart.h
 create mode 100644 Platform/NXP/Library/DUartPortLib/DUartPortLib.c
 create mode 100644 Platform/NXP/Library/DUartPortLib/DUartPortLib.inf

diff --git a/Platform/NXP/Library/DUartPortLib/DUart.h b/Platform/NXP/Library/DUartPortLib/DUart.h
new file mode 100644
index 0000000..5ad198d
--- /dev/null
+++ b/Platform/NXP/Library/DUartPortLib/DUart.h
@@ -0,0 +1,128 @@
+/** DUart.h
+*  Header defining the DUART constants (Base addresses, sizes, flags)
+*
+*  Based on Serial I/O Port library headers available in PL011Uart.h
+*
+*  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+*  Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+*  Copyright 2017 NXP
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __DUART_H__
+#define __DUART_H__
+
+// FIFO Control Register
+#define DUART_FCR_FIFO_EN          0x01 /* Fifo enable */
+#define DUART_FCR_CLEAR_RCVR       0x02 /* Clear the RCVR FIFO */
+#define DUART_FCR_CLEAR_XMIT       0x04 /* Clear the XMIT FIFO */
+#define DUART_FCR_DMA_SELECT       0x08 /* For DMA applications */
+#define DUART_FCR_TRIGGER_MASK     0xC0 /* Mask for the FIFO trigger range */
+#define DUART_FCR_TRIGGER_1        0x00 /* Mask for trigger set at 1 */
+#define DUART_FCR_TRIGGER_4        0x40 /* Mask for trigger set at 4 */
+#define DUART_FCR_TRIGGER_8        0x80 /* Mask for trigger set at 8 */
+#define DUART_FCR_TRIGGER_14       0xC0 /* Mask for trigger set at 14 */
+#define DUART_FCR_RXSR             0x02 /* Receiver soft reset */
+#define DUART_FCR_TXSR             0x04 /* Transmitter soft reset */
+
+// Modem Control Register
+#define DUART_MCR_DTR              0x01 /* Reserved  */
+#define DUART_MCR_RTS              0x02 /* RTS   */
+#define DUART_MCR_OUT1             0x04 /* Reserved */
+#define DUART_MCR_OUT2             0x08 /* Reserved */
+#define DUART_MCR_LOOP             0x10 /* Enable loopback test mode */
+#define DUART_MCR_AFE              0x20 /* AFE (Auto Flow Control) */
+#define DUART_MCR_DMA_EN           0x04
+#define DUART_MCR_TX_DFR           0x08
+
+// Line Control Register
+/*
+* Note: if the word length is 5 bits (DUART_LCR_WLEN5), then setting
+* DUART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
+*/
+#define DUART_LCR_WLS_MSK          0x03 /* character length select mask */
+#define DUART_LCR_WLS_5            0x00 /* 5 bit character length */
+#define DUART_LCR_WLS_6            0x01 /* 6 bit character length */
+#define DUART_LCR_WLS_7            0x02 /* 7 bit character length */
+#define DUART_LCR_WLS_8            0x03 /* 8 bit character length */
+#define DUART_LCR_STB              0x04 /* # stop Bits, off=1, on=1.5 or 2) */
+#define DUART_LCR_PEN              0x08 /* Parity eneble */
+#define DUART_LCR_EPS              0x10 /* Even Parity Select */
+#define DUART_LCR_STKP             0x20 /* Stick Parity */
+#define DUART_LCR_SBRK             0x40 /* Set Break */
+#define DUART_LCR_BKSE             0x80 /* Bank select enable */
+#define DUART_LCR_DLAB             0x80 /* Divisor latch access bit */
+
+// Line Status Register
+#define DUART_LSR_DR               0x01 /* Data ready */
+#define DUART_LSR_OE               0x02 /* Overrun */
+#define DUART_LSR_PE               0x04 /* Parity error */
+#define DUART_LSR_FE               0x08 /* Framing error */
+#define DUART_LSR_BI               0x10 /* Break */
+#define DUART_LSR_THRE             0x20 /* Xmit holding register empty */
+#define DUART_LSR_TEMT             0x40 /* Xmitter empty */
+#define DUART_LSR_ERR              0x80 /* Error */
+
+// Modem Status Register
+#define DUART_MSR_DCTS             0x01 /* Delta CTS */
+#define DUART_MSR_DDSR             0x02 /* Reserved */
+#define DUART_MSR_TERI             0x04 /* Reserved */
+#define DUART_MSR_DDCD             0x08 /* Reserved */
+#define DUART_MSR_CTS              0x10 /* Clear to Send */
+#define DUART_MSR_DSR              0x20 /* Reserved */
+#define DUART_MSR_RI               0x40 /* Reserved */
+#define DUART_MSR_DCD              0x80 /* Reserved */
+
+// Interrupt Identification Register
+#define DUART_IIR_NO_INT           0x01 /* No interrupts pending */
+#define DUART_IIR_ID               0x06 /* Mask for the interrupt ID */
+#define DUART_IIR_MSI              0x00 /* Modem status interrupt */
+#define DUART_IIR_THRI             0x02 /* Transmitter holding register empty */
+#define DUART_IIR_RDI              0x04 /* Receiver data interrupt */
+#define DUART_IIR_RLSI             0x06 /* Receiver line status interrupt */
+
+//  Interrupt Enable Register
+#define DUART_IER_MSI              0x08 /* Enable Modem status interrupt */
+#define DUART_IER_RLSI             0x04 /* Enable receiver line status interrupt */
+#define DUART_IER_THRI             0x02 /* Enable Transmitter holding register int. */
+#define DUART_IER_RDI              0x01 /* Enable receiver data interrupt */
+
+// LCR defaults
+#define DUART_LCR_8N1              0x03
+#define DUART_LCRVAL               DUART_LCR_8N1          /* 8 data, 1 stop, no parity */
+#define DUART_MCRVAL               (DUART_MCR_DTR | \
+                                   DUART_MCR_RTS)         /* RTS/DTR */
+#define DUART_FCRVAL               (DUART_FCR_FIFO_EN | \
+                                   DUART_FCR_RXSR |    \
+                                   DUART_FCR_TXSR)        /* Clear & enable FIFOs */
+
+#define URBR         0x0
+#define UTHR         0x0
+#define UDLB         0x0
+#define UDMB         0x1
+#define UIER         0x1
+#define UIIR         0x2
+#define UFCR         0x2
+#define UAFR         0x2
+#define ULCR         0x3
+#define UMCR         0x4
+#define ULSR         0x5
+#define UMSR         0x6
+#define USCR         0x7
+#define UDSR         0x10
+
+extern
+UINT32
+CalculateBaudDivisor (
+  IN  UINT64 BaudRate
+  );
+
+#endif /* __DUART_H__ */
diff --git a/Platform/NXP/Library/DUartPortLib/DUartPortLib.c b/Platform/NXP/Library/DUartPortLib/DUartPortLib.c
new file mode 100644
index 0000000..ad416de
--- /dev/null
+++ b/Platform/NXP/Library/DUartPortLib/DUartPortLib.c
@@ -0,0 +1,331 @@
+/** DuartPortLib.c
+  DUART (NS16550) library functions
+
+  Based on Serial I/O Port library functions available in PL011SerialPortLib.c
+
+  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+  Copyright (c) 2012 - 2013, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+  Copyright 2017 NXP
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/SerialPortLib.h>
+
+#include "DUart.h"
+
+STATIC CONST UINT32 mInvalidControlBits = (EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE | \
+                                           EFI_SERIAL_DATA_TERMINAL_READY);
+
+/**
+  Assert or deassert the control signals on a serial port.
+  The following control signals are set according their bit settings :
+  . Request to Send
+  . Data Terminal Ready
+
+  @param[in]  Control     The following bits are taken into account :
+                          . EFI_SERIAL_REQUEST_TO_SEND : assert/deassert the
+                            "Request To Send" control signal if this bit is
+                            equal to one/zero.
+                          . EFI_SERIAL_DATA_TERMINAL_READY : assert/deassert
+                            the "Data Terminal Ready" control signal if this
+                            bit is equal to one/zero.
+                          . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : enable/disable
+                            the hardware loopback if this bit is equal to
+                            one/zero.
+                          . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : not supported.
+                          . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : enable/
+                            disable the hardware flow control based on CTS (Clear
+                            To Send) and RTS (Ready To Send) control signals.
+
+  @retval  EFI_SUCCESS      The new control bits were set on the device.
+  @retval  EFI_UNSUPPORTED  The device does not support this operation.
+
+**/
+EFI_STATUS
+EFIAPI
+SerialPortSetControl (
+  IN  UINT32  Control
+  )
+{
+  UINT32  McrBits;
+  UINTN   UartBase;
+
+  UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
+
+  if (Control & (mInvalidControlBits)) {
+    return EFI_UNSUPPORTED;
+  }
+
+  McrBits = MmioRead8 (UartBase + UMCR);
+
+  if (Control & EFI_SERIAL_REQUEST_TO_SEND) {
+    McrBits |= DUART_MCR_RTS;
+  } else {
+    McrBits &= ~DUART_MCR_RTS;
+  }
+
+  if (Control & EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE) {
+    McrBits |= DUART_MCR_LOOP;
+  } else {
+    McrBits &= ~DUART_MCR_LOOP;
+  }
+
+  if (Control & EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE) {
+    McrBits |= DUART_MCR_AFE;
+  } else {
+    McrBits &= ~DUART_MCR_AFE;
+  }
+
+  MmioWrite32 (UartBase + UMCR, McrBits);
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Retrieve the status of the control bits on a serial device.
+
+  @param[out]  Control     Status of the control bits on a serial device :
+
+                         . EFI_SERIAL_DATA_CLEAR_TO_SEND,
+                           EFI_SERIAL_DATA_SET_READY,
+                           EFI_SERIAL_RING_INDICATE,
+                           EFI_SERIAL_CARRIER_DETECT,
+                           EFI_SERIAL_REQUEST_TO_SEND,
+                           EFI_SERIAL_DATA_TERMINAL_READY
+                           are all related to the DTE (Data Terminal Equipment)
+                           and DCE (Data Communication Equipment) modes of
+                           operation of the serial device.
+                         . EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if the
+                           receive buffer is empty, 0 otherwise.
+                         . EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one if the
+                           transmit buffer is empty, 0 otherwise.
+                         . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to one if
+                           the hardware loopback is enabled (the ouput feeds the
+                           receive buffer), 0 otherwise.
+                         . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to one if
+                           a loopback is accomplished by software, 0 otherwise.
+                         . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal to
+                           one if the hardware flow control based on CTS (Clear
+                           To Send) and RTS (Ready To Send) control signals is
+                           enabled, 0 otherwise.
+
+  @retval EFI_SUCCESS      The control bits were read from the serial device.
+
+**/
+EFI_STATUS
+EFIAPI
+SerialPortGetControl (
+  OUT  UINT32   *Control
+  )
+{
+  UINT32        MsrRegister;
+  UINT32        McrRegister;
+  UINT32        LsrRegister;
+  UINTN         UartBase;
+
+  UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
+
+  MsrRegister = MmioRead8 (UartBase + UMSR);
+  McrRegister = MmioRead8 (UartBase + UMCR);
+  LsrRegister = MmioRead8 (UartBase + ULSR);
+
+  *Control = 0;
+
+  if ((MsrRegister & DUART_MSR_CTS) == DUART_MSR_CTS) {
+    *Control |= EFI_SERIAL_CLEAR_TO_SEND;
+  }
+
+  if ((McrRegister & DUART_MCR_RTS) == DUART_MCR_RTS) {
+    *Control |= EFI_SERIAL_REQUEST_TO_SEND;
+  }
+
+  if ((LsrRegister & DUART_LSR_TEMT) == DUART_LSR_TEMT) {
+    *Control |= EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
+  }
+
+  if ((McrRegister & DUART_MCR_AFE) == DUART_MCR_AFE) {
+    *Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;
+  }
+
+  if ((McrRegister & DUART_MCR_LOOP) == DUART_MCR_LOOP) {
+    *Control |= EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE;
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Programmed hardware of Serial port.
+
+  @return    Always return EFI_SUCCESS.
+
+**/
+EFI_STATUS
+EFIAPI
+SerialPortInitialize (
+  VOID
+  )
+{
+  UINT64  BaudRate;
+  UINT32  BaudDivisor;
+  UINTN   UartBase;
+
+  UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
+  BaudRate = (UINTN)PcdGet64 (PcdUartDefaultBaudRate);
+
+  BaudDivisor = CalculateBaudDivisor (BaudRate);
+
+  while (!(MmioRead8 (UartBase + ULSR) & DUART_LSR_TEMT));
+
+  //
+  // Enable and assert interrupt when new data is available on
+  // external device,
+  // setup data format, setup baud divisor
+  //
+  MmioWrite8 (UartBase + UIER, 0x1);
+  MmioWrite8 (UartBase + ULCR, DUART_LCR_BKSE | DUART_LCRVAL);
+  MmioWrite8 (UartBase + UDLB, 0);
+  MmioWrite8 (UartBase + UDMB, 0);
+  MmioWrite8 (UartBase + ULCR, DUART_LCRVAL);
+  MmioWrite8 (UartBase + UMCR, DUART_MCRVAL);
+  MmioWrite8 (UartBase + UFCR, DUART_FCRVAL);
+  MmioWrite8 (UartBase + ULCR, DUART_LCR_BKSE | DUART_LCRVAL);
+  MmioWrite8 (UartBase + UDLB, BaudDivisor & 0xff);
+  MmioWrite8 (UartBase + UDMB, (BaudDivisor >> 8) & 0xff);
+  MmioWrite8 (UartBase + ULCR, DUART_LCRVAL);
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Write data to serial device.
+
+  @param  Buffer           Point of data buffer which need to be written.
+  @param  NumberOfBytes    Number of output bytes which are cached in Buffer.
+
+  @retval 0                Write data failed.
+  @retval !0               Actual number of bytes written to serial device.
+
+**/
+UINTN
+EFIAPI
+SerialPortWrite (
+  IN  UINT8     *Buffer,
+  IN  UINTN     NumberOfBytes
+  )
+{
+  UINT8         *Final;
+  UINTN         UartBase;
+
+  Final = &Buffer[NumberOfBytes];
+  UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
+
+  while (Buffer < Final) {
+    while ((MmioRead8 (UartBase + ULSR) & DUART_LSR_THRE) == 0);
+    MmioWrite8 (UartBase + UTHR, *Buffer++);
+  }
+
+  return NumberOfBytes;
+}
+
+/**
+  Read data from serial device and save the data in buffer.
+
+  @param  Buffer           Point of data buffer which need to be written.
+  @param  NumberOfBytes    Number of output bytes which are cached in Buffer.
+
+  @retval 0                Read data failed.
+  @retval !0               Actual number of bytes read from serial device.
+
+**/
+UINTN
+EFIAPI
+SerialPortRead (
+  OUT UINT8     *Buffer,
+  IN  UINTN     NumberOfBytes
+  )
+{
+  UINTN   Count;
+  UINTN   UartBase;
+
+  UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
+
+  for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {
+     // Loop while waiting for a new char(s) to arrive in the
+     // RxFIFO
+    while ((MmioRead8 (UartBase + ULSR) & DUART_LSR_DR) == 0);
+
+    *Buffer = MmioRead8 (UartBase + URBR);
+  }
+
+  return NumberOfBytes;
+}
+
+/**
+  Check to see if any data is available to be read from the debug device.
+
+  @retval EFI_SUCCESS       At least one byte of data is available to be read
+  @retval EFI_NOT_READY     No data is available to be read
+  @retval EFI_DEVICE_ERROR  The serial device is not functioning properly
+
+**/
+BOOLEAN
+EFIAPI
+SerialPortPoll (
+  VOID
+  )
+{
+  UINTN   UartBase;
+
+  UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
+
+  return ((MmioRead8 (UartBase + ULSR) & DUART_LSR_DR) != 0);
+}
+
+/**
+  Set new attributes to LS1043a.
+
+  @param  BaudRate                The baud rate of the serial device. If the baud rate is not supported,
+                                  the speed will be reduced down to the nearest supported one and the
+                                  variable's value will be updated accordingly.
+  @param  ReceiveFifoDepth        The number of characters the device will buffer on input. If the specified
+                                  value is not supported, the variable's value will be reduced down to the
+                                  nearest supported one.
+  @param  Timeout                 If applicable, the number of microseconds the device will wait
+                                  before timing out a Read or a Write operation.
+  @param  Parity                  If applicable, this is the EFI_PARITY_TYPE that is computed or checked
+                                  as each character is transmitted or received. If the device does not
+                                  support parity, the value is the default parity value.
+  @param  DataBits                The number of data bits in each character
+  @param  StopBits                If applicable, the EFI_STOP_BITS_TYPE number of stop bits per character.
+                                  If the device does not support stop bits, the value is the default stop
+                                  bit value.
+
+  @retval EFI_SUCCESS             All attributes were set correctly on the serial device.
+
+**/
+EFI_STATUS
+EFIAPI
+SerialPortSetAttributes (
+  IN  OUT  UINT64              *BaudRate,
+  IN  OUT  UINT32              *ReceiveFifoDepth,
+  IN  OUT  UINT32              *Timeout,
+  IN  OUT  EFI_PARITY_TYPE     *Parity,
+  IN  OUT  UINT8               *DataBits,
+  IN  OUT  EFI_STOP_BITS_TYPE  *StopBits
+  )
+{
+  return SerialPortInitialize ();
+}
diff --git a/Platform/NXP/Library/DUartPortLib/DUartPortLib.inf b/Platform/NXP/Library/DUartPortLib/DUartPortLib.inf
new file mode 100644
index 0000000..7eb02ce
--- /dev/null
+++ b/Platform/NXP/Library/DUartPortLib/DUartPortLib.inf
@@ -0,0 +1,39 @@
+#  DUartPortLib.inf
+#
+#  Component description file for DUartPortLib module
+#
+#  Copyright (c) 2013, Freescale Ltd. All rights reserved.
+#  Copyright 2017 NXP
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = DUartPortLib
+  FILE_GUID                      = c42dfe79-8de5-429e-a055-2d0a58591498
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = SerialPortLib
+
+[Sources.common]
+  DUartPortLib.c
+
+[LibraryClasses]
+  PcdLib
+  SocLib
+
+[Packages]
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+
+[Pcd]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [PATCH edk2-platforms] [PATCH v3 5/9] Platform/NXP: Add support for I2c driver
  2017-11-27 10:51 [PATCH edk2-platforms] [PATCH v3 0/9] Platform/NXP Meenakshi Aggarwal
                   ` (3 preceding siblings ...)
  2017-11-27 10:51 ` [PATCH edk2-platforms] [PATCH v3 4/9] Platform/NXP : Add support for DUART library Meenakshi Aggarwal
@ 2017-11-27 10:51 ` Meenakshi Aggarwal
  2017-11-27 10:51 ` [PATCH edk2-platforms] [PATCH v3 6/9] Silicon/Maxim : Add support for DS1307 RTC library Meenakshi Aggarwal
                   ` (4 subsequent siblings)
  9 siblings, 0 replies; 25+ messages in thread
From: Meenakshi Aggarwal @ 2017-11-27 10:51 UTC (permalink / raw)
  To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel

I2C driver produces gEfiI2cMasterProtocolGuid which can be
used by other modules.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
 Platform/NXP/Drivers/I2cDxe/I2cDxe.c   | 728 +++++++++++++++++++++++++++++++++
 Platform/NXP/Drivers/I2cDxe/I2cDxe.h   |  64 +++
 Platform/NXP/Drivers/I2cDxe/I2cDxe.inf |  57 +++
 3 files changed, 849 insertions(+)
 create mode 100644 Platform/NXP/Drivers/I2cDxe/I2cDxe.c
 create mode 100644 Platform/NXP/Drivers/I2cDxe/I2cDxe.h
 create mode 100644 Platform/NXP/Drivers/I2cDxe/I2cDxe.inf

diff --git a/Platform/NXP/Drivers/I2cDxe/I2cDxe.c b/Platform/NXP/Drivers/I2cDxe/I2cDxe.c
new file mode 100644
index 0000000..30eb6f4
--- /dev/null
+++ b/Platform/NXP/Drivers/I2cDxe/I2cDxe.c
@@ -0,0 +1,728 @@
+/** I2cDxe.c
+  I2c driver APIs for read, write, initialize, set speed and reset
+
+  Copyright NXP 2017
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution. The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/TimerLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+
+#include <Protocol/I2cMaster.h>
+
+#include "I2cDxe.h"
+
+STATIC CONST EFI_PHYSICAL_ADDRESS I2cAddrArr[FixedPcdGet32 (PcdNumI2cController)] = {
+  FixedPcdGet64 (PcdI2c0BaseAddr),
+  FixedPcdGet64 (PcdI2c1BaseAddr),
+  FixedPcdGet64 (PcdI2c2BaseAddr),
+  FixedPcdGet64 (PcdI2c3BaseAddr)
+};
+
+STATIC CONST UINT16 ClkDiv[60][2] = {
+  { 20,  0x00 }, { 22, 0x01 },  { 24, 0x02 },  { 26, 0x03 },
+  { 28,  0x04 }, { 30,  0x05 }, { 32,  0x09 }, { 34, 0x06 },
+  { 36,  0x0A }, { 40, 0x07 },  { 44, 0x0C },  { 48, 0x0D },
+  { 52,  0x43 }, { 56,  0x0E }, { 60, 0x45 },  { 64, 0x12 },
+  { 68,  0x0F }, { 72,  0x13 }, { 80,  0x14 }, { 88,  0x15 },
+  { 96,  0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
+  { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
+  { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
+  { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
+  { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
+  { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
+  { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 },{ 1280, 0x35 },
+  { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
+  { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
+  { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
+};
+
+/**
+  Calculate and set proper clock divider
+
+  @param  Rate       clock rate
+
+  @retval ClkDiv     Value used to get frequency divider value
+
+**/
+STATIC
+UINT8
+GetClk (
+  IN  UINT32         Rate
+  )
+{
+  UINTN              ClkRate;
+  UINT32             Div;
+  UINT8              ClkDivx;
+
+  ClkRate = CalculateI2cClockRate ();
+
+  Div = (ClkRate + Rate - 1) / Rate;
+
+  if (Div < ClkDiv[0][0]) {
+    ClkDivx = 0;
+  } else if (Div > ClkDiv[ARRAY_SIZE (ClkDiv) - 1][0]){
+    ClkDivx = ARRAY_SIZE (ClkDiv) - 1;
+  } else {
+    for (ClkDivx = 0; ClkDiv[ClkDivx][0] < Div; ClkDivx++);
+  }
+
+  return ClkDivx;
+}
+
+/**
+  Function used to check if i2c is in mentioned state or not
+
+  @param   I2cRegs        Pointer to I2C registers
+  @param   State          i2c state need to be checked
+
+  @retval  EFI_NOT_READY  Arbitration was lost
+  @retval  EFI_TIMEOUT    Timeout occured
+  @retval  CurrState      Value of state register
+
+**/
+STATIC
+EFI_STATUS
+WaitForI2cState (
+  IN  I2C_REGS            *I2cRegs,
+  IN  UINT32              State
+  )
+{
+  UINT8                   CurrState;
+  UINT64                  Cnt;
+
+  for (Cnt = 0; Cnt < 50000; Cnt++) {
+    MemoryFence ();
+    CurrState = MmioRead8 ((UINTN)&I2cRegs->I2cSr);
+    if (CurrState & I2C_SR_IAL) {
+       MmioWrite8 ((UINTN)&I2cRegs->I2cSr, CurrState | I2C_SR_IAL);
+        return EFI_NOT_READY;
+    }
+
+    if ((CurrState & (State >> 8)) == (UINT8)State) {
+      return CurrState;
+    }
+  }
+
+  return EFI_TIMEOUT;
+}
+
+/**
+  Function to transfer byte on i2c
+
+  @param   I2cRegs        Pointer to i2c registers
+  @param   Byte           Byte to be transferred on i2c bus
+
+  @retval  EFI_NOT_READY  Arbitration was lost
+  @retval  EFI_TIMEOUT    Timeout occured
+  @retval  EFI_NOT_FOUND  ACK was not recieved
+  @retval  EFI_SUCCESS    Data transfer was succesful
+
+**/
+STATIC
+EFI_STATUS
+TransferByte (
+  IN  I2C_REGS            *I2cRegs,
+  IN  UINT8               Byte
+  )
+{
+  EFI_STATUS              Ret;
+
+  MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
+  MmioWrite8 ((UINTN)&I2cRegs->I2cDr, Byte);
+
+  Ret = WaitForI2cState (I2cRegs, IIF);
+  if ((Ret == EFI_TIMEOUT) || (Ret == EFI_NOT_READY)) {
+    return Ret;
+  }
+
+  if (Ret & I2C_SR_RX_NO_AK) {
+    return EFI_NOT_FOUND;
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Function to stop transaction on i2c bus
+
+  @param   I2cRegs          Pointer to i2c registers
+
+  @retval  EFI_NOT_READY    Arbitration was lost
+  @retval  EFI_TIMEOUT      Timeout occured
+  @retval  EFI_SUCCESS      Stop operation was successful
+
+**/
+STATIC
+EFI_STATUS
+I2cStop (
+  IN  I2C_REGS             *I2cRegs
+  )
+{
+  INT32                    Ret;
+  UINT32                   Temp;
+
+  Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
+
+  Temp &= ~(I2C_CR_MSTA | I2C_CR_MTX);
+  MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
+
+  Ret = WaitForI2cState (I2cRegs, BUS_IDLE);
+
+  if (Ret < 0) {
+    return Ret;
+  } else {
+    return EFI_SUCCESS;
+  }
+}
+
+/**
+  Function to send start signal, Chip Address and
+  memory offset
+
+  @param   I2cRegs         Pointer to i2c base registers
+  @param   Chip            Chip Address
+  @param   Offset          Slave memory's offset
+  @param   Alen            length of chip address
+
+  @retval  EFI_NOT_READY   Arbitration lost
+  @retval  EFI_TIMEOUT     Failed to initialize data transfer in predefined time
+  @retval  EFI_NOT_FOUND   ACK was not recieved
+  @retval  EFI_SUCCESS     Read was successful
+
+**/
+STATIC
+EFI_STATUS
+InitTransfer (
+  IN  I2C_REGS             *I2cRegs,
+  IN  UINT8                Chip,
+  IN  UINT32               Offset,
+  IN  INT32                Alen
+  )
+{
+  UINT32                   Temp;
+  EFI_STATUS               Ret;
+
+  // Enable I2C controller
+  if (MmioRead8 ((UINTN)&I2cRegs->I2cCr) & I2C_CR_IDIS) {
+    MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IEN);
+  }
+
+  if (MmioRead8 ((UINTN)&I2cRegs->I2cAdr) == (Chip << 1)) {
+    MmioWrite8 ((UINTN)&I2cRegs->I2cAdr, (Chip << 1) ^ 2);
+  }
+
+  MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
+  Ret = WaitForI2cState (I2cRegs, BUS_IDLE);
+  if ((Ret == EFI_TIMEOUT) || (Ret == EFI_NOT_READY)) {
+    return Ret;
+  }
+
+  // Start I2C transaction
+  Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
+  // set to master mode
+  Temp |= I2C_CR_MSTA;
+  MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
+
+  Ret = WaitForI2cState (I2cRegs, BUS_BUSY);
+  if ((Ret == EFI_TIMEOUT) || (Ret == EFI_NOT_READY)) {
+    return Ret;
+  }
+
+  Temp |= I2C_CR_MTX | I2C_CR_TX_NO_AK;
+  MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
+
+  // write slave Address
+  Ret = TransferByte (I2cRegs, Chip << 1);
+  if (Ret != EFI_SUCCESS) {
+    return Ret;
+  }
+
+  if (Alen >= 0) {
+    while (Alen--) {
+      Ret = TransferByte (I2cRegs, (Offset >> (Alen * 8)) & 0xff);
+      if (Ret != EFI_SUCCESS)
+        return Ret;
+    }
+  }
+  return EFI_SUCCESS;
+}
+
+/**
+  Function to check if i2c bus is idle
+
+  @param   Base          Pointer to base address of I2c controller
+
+  @retval  EFI_SUCCESS
+
+**/
+STATIC
+INT32
+I2cBusIdle (
+  IN  VOID               *Base
+  )
+{
+  return EFI_SUCCESS;
+}
+
+/**
+  Function to initiate data transfer on i2c bus
+
+  @param   I2cRegs         Pointer to i2c base registers
+  @param   Chip            Chip Address
+  @param   Offset          Slave memory's offset
+  @param   Alen            length of chip address
+
+  @retval  EFI_NOT_READY   Arbitration lost
+  @retval  EFI_TIMEOUT     Failed to initialize data transfer in predefined time
+  @retval  EFI_NOT_FOUND   ACK was not recieved
+  @retval  EFI_SUCCESS     Read was successful
+
+**/
+STATIC
+EFI_STATUS
+InitDataTransfer (
+  IN  I2C_REGS             *I2cRegs,
+  IN  UINT8                Chip,
+  IN  UINT32               Offset,
+  IN  INT32                Alen
+  )
+{
+  EFI_STATUS               Status;
+  INT32                    Retry;
+
+  for (Retry = 0; Retry < 3; Retry++) {
+    Status = InitTransfer (I2cRegs, Chip, Offset, Alen);
+    if (Status == EFI_SUCCESS) {
+      return EFI_SUCCESS;
+    }
+
+    I2cStop (I2cRegs);
+
+    if (EFI_NOT_FOUND == Status) {
+      return Status;
+    }
+
+    // Disable controller
+    if (Status != EFI_NOT_READY) {
+      MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IDIS);
+    }
+
+    if (I2cBusIdle (I2cRegs) < 0) {
+      break;
+    }
+  }
+  return Status;
+}
+
+/**
+  Function to read data using i2c bus
+
+  @param   I2cBus          I2c Controller number
+  @param   Chip            Address of slave device from where data to be read
+  @param   Offset          Offset of slave memory
+  @param   Alen            Address length of slave
+  @param   Buffer          A pointer to the destination buffer for the data
+  @param   Len             Length of data to be read
+
+  @retval  EFI_NOT_READY   Arbitration lost
+  @retval  EFI_TIMEOUT     Failed to initialize data transfer in predefined time
+  @retval  EFI_NOT_FOUND   ACK was not recieved
+  @retval  EFI_SUCCESS     Read was successful
+
+**/
+STATIC
+EFI_STATUS
+I2cDataRead (
+  IN  UINT32               I2cBus,
+  IN  UINT8                Chip,
+  IN  UINT32               Offset,
+  IN  UINT32               Alen,
+  IN  UINT8                *Buffer,
+  IN  UINT32               Len
+  )
+{
+  EFI_STATUS               Status;
+  UINT32                   Temp;
+  INT32                    I;
+  I2C_REGS                 *I2cRegs;
+
+  I2cRegs = (I2C_REGS *)I2cAddrArr[I2cBus];
+
+  Status = InitDataTransfer (I2cRegs, Chip, Offset, Alen);
+  if (Status != EFI_SUCCESS) {
+    return Status;
+  }
+
+  Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
+  Temp |= I2C_CR_RSTA;
+  MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
+
+  Status = TransferByte (I2cRegs, (Chip << 1) | 1);
+  if (Status != EFI_SUCCESS) {
+    I2cStop (I2cRegs);
+    return Status;
+  }
+
+  // setup bus to read data
+  Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
+  Temp &= ~(I2C_CR_MTX | I2C_CR_TX_NO_AK);
+  if (Len == 1) {
+    Temp |= I2C_CR_TX_NO_AK;
+  }
+
+  MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
+  MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
+
+  // Dummy Read to initiate recieve operation
+  MmioRead8 ((UINTN)&I2cRegs->I2cDr);
+
+  for (I = 0; I < Len; I++) {
+    Status = WaitForI2cState (I2cRegs, IIF);
+    if ((Status == EFI_TIMEOUT) || (Status == EFI_NOT_READY)) {
+       I2cStop (I2cRegs);
+       return Status;
+    }
+    //
+    // It must generate STOP before read I2DR to prevent
+    // controller from generating another clock cycle
+    //
+    if (I == (Len - 1)) {
+      I2cStop (I2cRegs);
+    } else if (I == (Len - 2)) {
+      Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
+      Temp |= I2C_CR_TX_NO_AK;
+      MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
+    }
+    MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
+    Buffer[I] = MmioRead8 ((UINTN)&I2cRegs->I2cDr);
+  }
+
+  I2cStop (I2cRegs);
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Function to write data using i2c bus
+
+  @param   I2cBus          I2c Controller number
+  @param   Chip            Address of slave device where data to be written
+  @param   Offset          Offset of slave memory
+  @param   Alen            Address length of slave
+  @param   Buffer          A pointer to the source buffer for the data
+  @param   Len             Length of data to be write
+
+  @retval  EFI_NOT_READY   Arbitration lost
+  @retval  EFI_TIMEOUT     Failed to initialize data transfer in predefined time
+  @retval  EFI_NOT_FOUND   ACK was not recieved
+  @retval  EFI_SUCCESS     Read was successful
+
+**/
+STATIC
+EFI_STATUS
+I2cDataWrite (
+  IN  UINT32               I2cBus,
+  IN  UINT8                Chip,
+  IN  UINT32               Offset,
+  IN  INT32                Alen,
+  OUT UINT8                *Buffer,
+  IN  INT32                Len
+  )
+{
+  EFI_STATUS               Status;
+  I2C_REGS                 *I2cRegs;
+  INT32                    I;
+
+  I2cRegs = (I2C_REGS *)I2cAddrArr[I2cBus];
+
+  Status = InitDataTransfer (I2cRegs, Chip, Offset, Alen);
+  if (Status != EFI_SUCCESS) {
+    return Status;
+  }
+
+  // Write operation
+  for (I = 0; I < Len; I++) {
+    Status = TransferByte (I2cRegs, Buffer[I]);
+    if (Status != EFI_SUCCESS) {
+      break;
+    }
+  }
+
+  I2cStop (I2cRegs);
+  return Status;
+}
+
+/**
+  Function to set i2c bus frequency
+
+  @param   This            Pointer to I2c master protocol
+  @param   BusClockHertz   value to be set
+
+  @retval EFI_SUCCESS      Operation successfull
+**/
+
+EFI_STATUS
+EFIAPI
+SetBusFrequency (
+  IN CONST EFI_I2C_MASTER_PROTOCOL   *This,
+  IN OUT UINTN                       *BusClockHertz
+ )
+{
+  I2C_REGS                 *I2cRegs;
+  UINT8                    ClkId;
+  UINT8                    SpeedId;
+
+  I2cRegs = (I2C_REGS *)I2cAddrArr[PcdGet32 (PcdI2cBus)];
+
+  ClkId = GetClk (*BusClockHertz);
+  SpeedId = ClkDiv[ClkId][1];
+
+  // Store divider value
+  MmioWrite8 ((UINTN)&I2cRegs->I2cFdr, SpeedId);
+
+  MemoryFence ();
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Function to reset I2c Controller
+
+  @param  This             Pointer to I2c master protocol
+
+  @return EFI_SUCCESS      Operation successfull
+**/
+EFI_STATUS
+EFIAPI
+Reset (
+  IN CONST EFI_I2C_MASTER_PROTOCOL *This
+  )
+{
+  I2C_REGS                         *I2cRegs;
+
+  I2cRegs = (I2C_REGS *)I2cAddrArr[PcdGet32 (PcdI2cBus)];
+
+  // Reset module
+  MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IDIS);
+  MmioWrite8 ((UINTN)&I2cRegs->I2cSr, 0);
+
+  MemoryFence ();
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+StartRequest (
+  IN CONST EFI_I2C_MASTER_PROTOCOL *This,
+  IN UINTN                         SlaveAddress,
+  IN EFI_I2C_REQUEST_PACKET        *RequestPacket,
+  IN EFI_EVENT                     Event            OPTIONAL,
+  OUT EFI_STATUS                   *I2cStatus       OPTIONAL
+  )
+{
+  UINT32                           Count;
+  INT32                            Ret;
+  UINT32                           Length;
+  UINT8                            *Buffer;
+  UINT32                           Flag;
+  UINT8                            RegAddress;
+
+  RegAddress = 0;
+
+  if (RequestPacket->OperationCount <= 0) {
+    DEBUG ((DEBUG_ERROR,"%a: Operation count is not valid %d\n",
+           __FUNCTION__, RequestPacket->OperationCount));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  for (Count = 0; Count < RequestPacket->OperationCount; Count++) {
+    Flag = RequestPacket->Operation[Count].Flags;
+    Length = RequestPacket->Operation[Count].LengthInBytes;
+    Buffer = RequestPacket->Operation[Count].Buffer;
+
+    if (Length <= 0) {
+      DEBUG ((DEBUG_ERROR,"%a: Invalid length of buffer %d\n",
+             __FUNCTION__, Length));
+      return EFI_INVALID_PARAMETER;
+    }
+
+    if (Flag == I2C_FLAG_WRITE && Count == 0) {
+      RegAddress = *Buffer;
+      continue;
+    } else if (Flag == I2C_FLAG_READ) {
+      Ret = I2cDataRead (PcdGet32 (PcdI2cBus), SlaveAddress,
+              RegAddress, sizeof(SlaveAddress)/8, Buffer, Length);
+      if (Ret != EFI_SUCCESS) {
+        DEBUG ((DEBUG_ERROR,"%a: I2c read operation failed (error %d)\n",
+               __FUNCTION__, Ret));
+        return Ret;
+      }
+    } else if (Flag == I2C_FLAG_WRITE) {
+      Ret = I2cDataWrite (PcdGet32 (PcdI2cBus), SlaveAddress,
+              RegAddress, sizeof(SlaveAddress)/8, Buffer, Length);
+      if (Ret != EFI_SUCCESS) {
+        DEBUG ((DEBUG_ERROR,"%a: I2c write operation failed (error %d)\n",
+               __FUNCTION__, Ret));
+        return Ret;
+      }
+    } else {
+      DEBUG ((DEBUG_ERROR,"%a: Invalid Flag %d\n",
+             __FUNCTION__, Flag));
+      return EFI_INVALID_PARAMETER;
+    }
+  }
+
+  return EFI_SUCCESS;
+}
+
+CONST EFI_I2C_CONTROLLER_CAPABILITIES I2cControllerCapabilities = {
+  0,
+  0,
+  0,
+  0
+};
+
+STATIC EFI_I2C_MASTER_PROTOCOL gI2c = {
+  ///
+  /// Set the clock frequency for the I2C bus.
+  ///
+  SetBusFrequency,
+  ///
+  /// Reset the I2C host controller.
+  ///
+  Reset,
+  ///
+  /// Start an I2C transaction in master mode on the host controller.
+  ///
+  StartRequest,
+  ///
+  /// Pointer to an EFI_I2C_CONTROLLER_CAPABILITIES data structure containing
+  /// the capabilities of the I2C host controller.
+  ///
+  &I2cControllerCapabilities
+};
+
+STATIC I2C_DEVICE_PATH gDevicePath = {
+  {
+    {
+      HARDWARE_DEVICE_PATH, HW_VENDOR_DP,
+      {
+        sizeof (VENDOR_DEVICE_PATH), 0
+      }
+    },
+    EFI_CALLER_ID_GUID
+  },
+  {
+    END_DEVICE_PATH_TYPE,
+    END_ENTIRE_DEVICE_PATH_SUBTYPE,
+    {
+      sizeof (EFI_DEVICE_PATH_PROTOCOL), 0
+    }
+  }
+};
+
+/**
+  The Entry Point for I2C driver.
+
+  @param[in] ImageHandle    The firmware allocated handle for the EFI image.
+  @param[in] SystemTable    A pointer to the EFI System Table.
+
+  @retval EFI_SUCCESS       The entry point is executed successfully.
+  @retval other             Some error occurs when executing this entry point.
+
+**/
+EFI_STATUS
+EFIAPI
+I2cDxeEntryPoint (
+  IN EFI_HANDLE             ImageHandle,
+  IN EFI_SYSTEM_TABLE       *SystemTable
+  )
+{
+  EFI_STATUS                Status;
+
+  //
+  // Install I2c Master protocol on this controller
+  //
+  Status = gBS->InstallMultipleProtocolInterfaces (
+                &ImageHandle,
+                &gEfiI2cMasterProtocolGuid,
+                (VOID**)&gI2c,
+                &gEfiDevicePathProtocolGuid,
+                &gDevicePath,
+                NULL
+                );
+
+  ASSERT_EFI_ERROR (Status);
+
+  return Status;
+}
+
+/**
+  Unload function for the I2c Driver.
+
+  @param  ImageHandle[in]        The allocated handle for the EFI image
+
+  @retval EFI_SUCCESS            The driver was unloaded successfully
+  @retval EFI_INVALID_PARAMETER  ImageHandle is not a valid image handle.
+
+**/
+EFI_STATUS
+EFIAPI
+I2cDxeUnload (
+  IN EFI_HANDLE                  ImageHandle
+  )
+{
+  EFI_STATUS                     Status;
+  EFI_HANDLE                     *HandleBuffer;
+  UINTN                          HandleCount;
+  UINTN                          Index;
+
+  //
+  // Retrieve all I2c handles in the handle database
+  //
+  Status = gBS->LocateHandleBuffer (ByProtocol,
+                                    &gEfiI2cMasterProtocolGuid,
+                                    NULL,
+                                    &HandleCount,
+                                    &HandleBuffer);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  //
+  // Disconnect the driver from the handles in the handle database
+  //
+  for (Index = 0; Index < HandleCount; Index++) {
+    Status = gBS->DisconnectController (HandleBuffer[Index],
+                                        gImageHandle,
+                                        NULL);
+  }
+
+  //
+  // Free the handle array
+  //
+  gBS->FreePool (HandleBuffer);
+
+  //
+  // Uninstall protocols installed by the driver in its entrypoint
+  //
+  Status = gBS->UninstallMultipleProtocolInterfaces (ImageHandle,
+                  &gEfiI2cMasterProtocolGuid, &gI2c,
+                  &gEfiDevicePathProtocolGuid, &gDevicePath,
+                  NULL);
+
+  return Status;
+}
diff --git a/Platform/NXP/Drivers/I2cDxe/I2cDxe.h b/Platform/NXP/Drivers/I2cDxe/I2cDxe.h
new file mode 100644
index 0000000..604396c
--- /dev/null
+++ b/Platform/NXP/Drivers/I2cDxe/I2cDxe.h
@@ -0,0 +1,64 @@
+/** I2cDxe.h
+  Header defining the constant, base address amd function for I2C controller
+
+  Copyright 2017 NXP
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __I2C_DXE_H___
+#define __I2C_DXE_H__
+
+#include <Uefi.h>
+
+#define I2C_CR_IIEN           (1 << 6)
+#define I2C_CR_MSTA           (1 << 5)
+#define I2C_CR_MTX            (1 << 4)
+#define I2C_CR_TX_NO_AK       (1 << 3)
+#define I2C_CR_RSTA           (1 << 2)
+
+#define I2C_SR_ICF            (1 << 7)
+#define I2C_SR_IBB            (1 << 5)
+#define I2C_SR_IAL            (1 << 4)
+#define I2C_SR_IIF            (1 << 1)
+#define I2C_SR_RX_NO_AK       (1 << 0)
+
+#define I2C_CR_IEN            (0 << 7)
+#define I2C_CR_IDIS           (1 << 7)
+#define I2C_SR_IIF_CLEAR      (1 << 1)
+
+#define BUS_IDLE              (0 | (I2C_SR_IBB << 8))
+#define BUS_BUSY              (I2C_SR_IBB | (I2C_SR_IBB << 8))
+#define IIF                   (I2C_SR_IIF | (I2C_SR_IIF << 8))
+
+#define I2C_FLAG_WRITE        0x0
+
+typedef struct {
+  VENDOR_DEVICE_PATH        Guid;
+  EFI_DEVICE_PATH_PROTOCOL  End;
+} I2C_DEVICE_PATH;
+
+/**
+  Record defining i2c registers
+**/
+typedef struct {
+  UINT8     I2cAdr;
+  UINT8     I2cFdr;
+  UINT8     I2cCr;
+  UINT8     I2cSr;
+  UINT8     I2cDr;
+} I2C_REGS ;
+
+UINT32
+CalculateI2cClockRate (
+  VOID
+  );
+
+#endif
diff --git a/Platform/NXP/Drivers/I2cDxe/I2cDxe.inf b/Platform/NXP/Drivers/I2cDxe/I2cDxe.inf
new file mode 100644
index 0000000..d6496cf
--- /dev/null
+++ b/Platform/NXP/Drivers/I2cDxe/I2cDxe.inf
@@ -0,0 +1,57 @@
+#  @file
+#
+#  Component description file for I2c driver
+#
+#  Copyright (c) 2015, Freescale Semiconductor, Inc. All rights reserved.
+#  Copyright NXP 2017
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = I2cDxe
+  FILE_GUID                      = 5f2927ba-1b04-4d5f-8bef-2b50c635d1e7
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = I2cDxeEntryPoint
+  UNLOAD                         = I2cDxeUnload
+
+[Sources.common]
+  I2cDxe.c
+
+[LibraryClasses]
+  ArmLib
+  IoLib
+  MemoryAllocationLib
+  PcdLib
+  SocLib
+  TimerLib
+  UefiDriverEntryPoint
+  UefiLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  Platform/NXP/NxpQoriqLs.dec
+
+[Protocols]
+  gEfiI2cMasterProtocolGuid
+
+[Pcd]
+  gNxpQoriqLsTokenSpaceGuid.PcdI2cBus
+  gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed
+  gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdI2c1BaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdI2c2BaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdI2c3BaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController
+
+[Depex]
+  TRUE
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [PATCH edk2-platforms] [PATCH v3 6/9] Silicon/Maxim : Add support for DS1307 RTC library
  2017-11-27 10:51 [PATCH edk2-platforms] [PATCH v3 0/9] Platform/NXP Meenakshi Aggarwal
                   ` (4 preceding siblings ...)
  2017-11-27 10:51 ` [PATCH edk2-platforms] [PATCH v3 5/9] Platform/NXP: Add support for I2c driver Meenakshi Aggarwal
@ 2017-11-27 10:51 ` Meenakshi Aggarwal
  2017-11-27 10:51 ` [PATCH edk2-platforms] [PATCH v3 7/9] Platform/NXP: Add support for ArmPlatformLib Meenakshi Aggarwal
                   ` (3 subsequent siblings)
  9 siblings, 0 replies; 25+ messages in thread
From: Meenakshi Aggarwal @ 2017-11-27 10:51 UTC (permalink / raw)
  To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel

Real time clock Apis on top of I2C Apis

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h     |  59 ++++
 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c  | 327 +++++++++++++++++++++
 .../Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec    |  26 ++
 .../Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf    |  45 +++
 4 files changed, 457 insertions(+)
 create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h
 create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
 create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
 create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf

diff --git a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h
new file mode 100644
index 0000000..636be88
--- /dev/null
+++ b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h
@@ -0,0 +1,59 @@
+/** Ds1307Rtc.h
+*
+*  Copyright 2017 NXP
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __DS1307RTC_H__
+#define __DS1307RTC_H__
+
+/*
+ * RTC time register
+ */
+#define DS1307_SEC_REG_ADDR        0x00
+#define DS1307_MIN_REG_ADDR        0x01
+#define DS1307_HR_REG_ADDR         0x02
+#define DS1307_DAY_REG_ADDR        0x03
+#define DS1307_DATE_REG_ADDR       0x04
+#define DS1307_MON_REG_ADDR        0x05
+#define DS1307_YR_REG_ADDR         0x06
+
+#define DS1307_SEC_BIT_CH          0x80  /* Clock Halt (in Register 0)   */
+
+/*
+ * RTC control register
+ */
+#define DS1307_CTL_REG_ADDR        0x07
+
+#define START_YEAR                 1970
+#define END_YEAR                   2070
+
+/*
+ * TIME MASKS
+ */
+#define MASK_SEC                   0x7F
+#define MASK_MIN                   0x7F
+#define MASK_HOUR                  0x3F
+#define MASK_DAY                   0x3F
+#define MASK_MONTH                 0x1F
+
+/*
+ * I2C FLAGS
+ */
+#define I2C_REG_ADDRESS            0x2
+
+typedef struct {
+  UINTN                           OperationCount;
+  EFI_I2C_OPERATION               SetAddressOp;
+  EFI_I2C_OPERATION               GetSetDateTimeOp;
+} RTC_I2C_REQUEST;
+
+#endif // __DS1307RTC_H__
diff --git a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
new file mode 100644
index 0000000..b09c0bf
--- /dev/null
+++ b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
@@ -0,0 +1,327 @@
+/** Ds1307RtcLib.c
+  Implement EFI RealTimeClock via RTC Lib for DS1307 RTC.
+
+  Based on RTC implementation available in
+  EmbeddedPkg/Library/TemplateRealTimeClockLib/RealTimeClockLib.c
+
+  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+  Copyright 2017 NXP
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiDxe.h>
+#include <Base.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/RealTimeClockLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Protocol/I2cMaster.h>
+
+#include "Ds1307Rtc.h"
+
+STATIC VOID                       *mDriverEventRegistration;
+STATIC EFI_I2C_MASTER_PROTOCOL    *mI2cMaster;
+
+/**
+  Read RTC register.
+
+  @param  RtcRegAddr       Register offset of RTC to be read.
+
+  @retval                  Register Value read
+
+**/
+
+STATIC
+UINT8
+RtcRead (
+  IN  UINT8                RtcRegAddr
+  )
+{
+  RTC_I2C_REQUEST          Req;
+  EFI_STATUS               Status;
+  UINT8                    Val;
+
+  Val = 0;
+
+  Req.OperationCount = 2;
+
+  Req.SetAddressOp.Flags = 0;
+  Req.SetAddressOp.LengthInBytes = sizeof (RtcRegAddr);
+  Req.SetAddressOp.Buffer = &RtcRegAddr;
+
+  Req.GetSetDateTimeOp.Flags = I2C_FLAG_READ;
+  Req.GetSetDateTimeOp.LengthInBytes = sizeof (Val);
+  Req.GetSetDateTimeOp.Buffer = &Val;
+
+  Status = mI2cMaster->StartRequest (mI2cMaster, FixedPcdGet8 (PcdI2cSlaveAddress),
+                                     (VOID *)&Req,
+                                     NULL,  NULL);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "RTC read error at Addr:0x%x\n", RtcRegAddr));
+  }
+
+  return Val;
+}
+
+/**
+  Write RTC register.
+
+  @param  RtcRegAddr       Register offset of RTC to write.
+  @param  Val              Value to be written
+
+**/
+
+STATIC
+VOID
+RtcWrite (
+  IN  UINT8                RtcRegAddr,
+  IN  UINT8                Val
+  )
+{
+  RTC_I2C_REQUEST          Req;
+  EFI_STATUS               Status;
+
+  Req.OperationCount = 2;
+
+  Req.SetAddressOp.Flags = 0;
+  Req.SetAddressOp.LengthInBytes = sizeof (RtcRegAddr);
+  Req.SetAddressOp.Buffer = &RtcRegAddr;
+
+  Req.GetSetDateTimeOp.Flags = 0;
+  Req.GetSetDateTimeOp.LengthInBytes = sizeof (Val);
+  Req.GetSetDateTimeOp.Buffer = &Val;
+
+  Status = mI2cMaster->StartRequest (mI2cMaster, FixedPcdGet8 (PcdI2cSlaveAddress),
+                                     (VOID *)&Req,
+                                     NULL,  NULL);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "RTC write error at Addr:0x%x\n", RtcRegAddr));
+  }
+}
+
+/**
+  Returns the current time and date information, and the time-keeping capabilities
+  of the hardware platform.
+
+  @param  Time                  A pointer to storage to receive a snapshot of the current time.
+  @param  Capabilities          An optional pointer to a buffer to receive the real time clock
+                                device's capabilities.
+
+  @retval EFI_SUCCESS           The operation completed successfully.
+  @retval EFI_INVALID_PARAMETER Time is NULL.
+  @retval EFI_DEVICE_ERROR      The time could not be retrieved due to hardware error.
+
+**/
+
+EFI_STATUS
+EFIAPI
+LibGetTime (
+  OUT  EFI_TIME                 *Time,
+  OUT  EFI_TIME_CAPABILITIES    *Capabilities
+  )
+{
+  EFI_STATUS                    Status;
+  UINT8                         Second;
+  UINT8                         Minute;
+  UINT8                         Hour;
+  UINT8                         Day;
+  UINT8                         Month;
+  UINT8                         Year;
+
+  if (mI2cMaster == NULL) {
+    return EFI_DEVICE_ERROR;
+  }
+
+  Status = EFI_SUCCESS;
+
+  Second = RtcRead (DS1307_SEC_REG_ADDR);
+  Minute = RtcRead (DS1307_MIN_REG_ADDR);
+  Hour = RtcRead (DS1307_HR_REG_ADDR);
+  Day = RtcRead (DS1307_DATE_REG_ADDR);
+  Month = RtcRead (DS1307_MON_REG_ADDR);
+  Year = RtcRead (DS1307_YR_REG_ADDR);
+
+  if (Second & DS1307_SEC_BIT_CH) {
+    DEBUG ((DEBUG_ERROR, "### Warning: RTC oscillator has stopped\n"));
+    /* clear the CH flag */
+    RtcWrite (DS1307_SEC_REG_ADDR,
+              RtcRead (DS1307_SEC_REG_ADDR) & ~DS1307_SEC_BIT_CH);
+    Status = EFI_DEVICE_ERROR;
+  }
+
+  Time->Second  = BcdToDecimal8 (Second & MASK_SEC);
+  Time->Minute  = BcdToDecimal8 (Minute & MASK_MIN);
+  Time->Hour = BcdToDecimal8 (Hour & MASK_HOUR);
+  Time->Day = BcdToDecimal8 (Day & MASK_DAY);
+  Time->Month  = BcdToDecimal8 (Month & MASK_MONTH);
+
+  //
+  // RTC can save year 1970 to 2069
+  // On writing Year, save year % 100
+  // On Reading reversing the operation e.g. 2012
+  // write = 12 (2012 % 100)
+  // read = 2012 (12 + 2000)
+  //
+  Time->Year = BcdToDecimal8 (Year) +
+               (BcdToDecimal8 (Year) >= 70 ? START_YEAR - 70 : END_YEAR -70);
+
+  return Status;
+}
+
+/**
+  Sets the current local time and date information.
+
+  @param  Time                  A pointer to the current time.
+
+  @retval EFI_SUCCESS           The operation completed successfully.
+  @retval EFI_INVALID_PARAMETER A time field is out of range.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetTime (
+  IN  EFI_TIME                *Time
+  )
+{
+  if (mI2cMaster == NULL) {
+    return EFI_DEVICE_ERROR;
+  }
+
+  if (Time->Year < START_YEAR || Time->Year >= END_YEAR){
+    DEBUG ((DEBUG_ERROR, "WARNING: Year should be between 1970 and 2069!\n"));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  RtcWrite (DS1307_YR_REG_ADDR, DecimalToBcd8 (Time->Year % 100));
+  RtcWrite (DS1307_MON_REG_ADDR, DecimalToBcd8 (Time->Month));
+  RtcWrite (DS1307_DATE_REG_ADDR, DecimalToBcd8 (Time->Day));
+  RtcWrite (DS1307_HR_REG_ADDR, DecimalToBcd8 (Time->Hour));
+  RtcWrite (DS1307_MIN_REG_ADDR, DecimalToBcd8 (Time->Minute));
+  RtcWrite (DS1307_SEC_REG_ADDR, DecimalToBcd8 (Time->Second));
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Returns the current wakeup alarm clock setting.
+
+  @param  Enabled               Indicates if the alarm is currently enabled or disabled.
+  @param  Pending               Indicates if the alarm signal is pending and requires acknowledgement.
+  @param  Time                  The current alarm setting.
+
+  @retval EFI_SUCCESS           The alarm settings were returned.
+  @retval EFI_INVALID_PARAMETER Any parameter is NULL.
+  @retval EFI_DEVICE_ERROR      The wakeup time could not be retrieved due to a hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+LibGetWakeupTime (
+  OUT  BOOLEAN                  *Enabled,
+  OUT  BOOLEAN                  *Pending,
+  OUT  EFI_TIME                 *Time
+  )
+{
+  // Not a required feature
+  return EFI_UNSUPPORTED;
+}
+
+/**
+  Sets the system wakeup alarm clock time.
+
+  @param  Enabled               Enable or disable the wakeup alarm.
+  @param  Time                  If Enable is TRUE, the time to set the wakeup alarm for.
+
+  @retval EFI_SUCCESS           If Enable is TRUE, then the wakeup alarm was enabled. If
+                                Enable is FALSE, then the wakeup alarm was disabled.
+  @retval EFI_INVALID_PARAMETER A time field is out of range.
+  @retval EFI_DEVICE_ERROR      The wakeup time could not be set due to a hardware error.
+  @retval EFI_UNSUPPORTED       A wakeup timer is not supported on this platform.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetWakeupTime (
+  IN BOOLEAN                    Enabled,
+  OUT EFI_TIME                  *Time
+  )
+{
+  // Not a required feature
+  return EFI_UNSUPPORTED;
+}
+
+STATIC
+VOID
+I2cDriverRegistrationEvent (
+  IN  EFI_EVENT                 Event,
+  IN  VOID                      *Context
+  )
+{
+  EFI_STATUS                    Status;
+  EFI_I2C_MASTER_PROTOCOL       *I2cMaster;
+  UINTN                         BusFrequency;
+
+  Status = gBS->LocateProtocol (&gEfiI2cMasterProtocolGuid, NULL, (VOID **)&I2cMaster);
+
+  gBS->CloseEvent (Event);
+
+  ASSERT_EFI_ERROR (Status);
+
+  Status = I2cMaster->Reset (I2cMaster);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "%a: I2CMaster->Reset () failed - %r\n",
+      __FUNCTION__, Status));
+    return;
+  }
+
+  BusFrequency = FixedPcdGet16 (PcdI2cBusFrequency);
+  Status = I2cMaster->SetBusFrequency (I2cMaster, &BusFrequency);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "%a: I2CMaster->SetBusFrequency () failed - %r\n",
+      __FUNCTION__, Status));
+    return;
+  }
+
+  mI2cMaster = I2cMaster;
+}
+
+/**
+  This is the declaration of an EFI image entry point. This can be the entry point to an application
+  written to this specification, an EFI boot service driver.
+
+  @param  ImageHandle           Handle that identifies the loaded image.
+  @param  SystemTable           System Table for this image.
+
+  @retval EFI_SUCCESS           The operation completed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+LibRtcInitialize (
+  IN EFI_HANDLE                 ImageHandle,
+  IN EFI_SYSTEM_TABLE           *SystemTable
+  )
+{
+  //
+  // Register a protocol registration notification callback on the driver
+  // binding protocol so we can attempt to connect our I2C master to it
+  // as soon as it appears.
+  //
+  EfiCreateProtocolNotifyEvent (
+    &gEfiI2cMasterProtocolGuid,
+    TPL_CALLBACK,
+    I2cDriverRegistrationEvent,
+    NULL,
+    &mDriverEventRegistration);
+
+  return EFI_SUCCESS;
+}
diff --git a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
new file mode 100644
index 0000000..5312551
--- /dev/null
+++ b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
@@ -0,0 +1,26 @@
+#/** @file
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution.  The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  DEC_SPECIFICATION              = 0x0001001A
+  PACKAGE_NAME                   = Ds1307RtcLib
+  PACKAGE_GUID                   = 0c095cf6-834d-4fa2-a5a0-31ac35591ad2
+  PACKAGE_VERSION                = 0.1
+
+[Guids]
+  gDs1307RtcLibTokenSpaceGuid = { 0xd939eb84, 0xa95a, 0x46a0, { 0xa8, 0x2b, 0xb9, 0x64, 0x30, 0xcf, 0xf5, 0x99 }}
+
+[PcdsFixedAtBuild]
+  gDs1307RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0|UINT8|0x00000001
+  gDs1307RtcLibTokenSpaceGuid.PcdI2cBusFrequency|0|UINT32|0x00000002
diff --git a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
new file mode 100644
index 0000000..c0f1268
--- /dev/null
+++ b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
@@ -0,0 +1,45 @@
+#  @Ds1307RtcLib.inf
+#
+#  Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+#  Copyright (c) 2017 NXP
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = Ds1307RtcLib
+  FILE_GUID                      = 7112fb46-8dda-4a41-ac40-bf212fedfc08
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = RealTimeClockLib
+
+[Sources.common]
+  Ds1307RtcLib.c
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
+
+[LibraryClasses]
+  DebugLib
+  UefiBootServicesTableLib
+  UefiLib
+
+[Protocols]
+  gEfiDriverBindingProtocolGuid        ## CONSUMES
+  gEfiI2cMasterProtocolGuid            ## CONSUMES
+
+[FixedPcd]
+  gDs1307RtcLibTokenSpaceGuid.PcdI2cSlaveAddress
+  gDs1307RtcLibTokenSpaceGuid.PcdI2cBusFrequency
+
+[Depex]
+  gEfiI2cMasterProtocolGuid
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [PATCH edk2-platforms] [PATCH v3 7/9] Platform/NXP: Add support for ArmPlatformLib
  2017-11-27 10:51 [PATCH edk2-platforms] [PATCH v3 0/9] Platform/NXP Meenakshi Aggarwal
                   ` (5 preceding siblings ...)
  2017-11-27 10:51 ` [PATCH edk2-platforms] [PATCH v3 6/9] Silicon/Maxim : Add support for DS1307 RTC library Meenakshi Aggarwal
@ 2017-11-27 10:51 ` Meenakshi Aggarwal
  2017-11-27 10:51 ` [PATCH edk2-platforms] [PATCH v3 8/9] Compilation : Add the fdf, dsc and dec files Meenakshi Aggarwal
                   ` (2 subsequent siblings)
  9 siblings, 0 replies; 25+ messages in thread
From: Meenakshi Aggarwal @ 2017-11-27 10:51 UTC (permalink / raw)
  To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
 .../Library/PlatformLib/ArmPlatformLib.c           | 105 ++++++++++++
 .../Library/PlatformLib/ArmPlatformLib.inf         |  70 ++++++++
 .../Library/PlatformLib/NxpQoriqLsHelper.S         |  38 +++++
 .../Library/PlatformLib/NxpQoriqLsMem.c            | 184 +++++++++++++++++++++
 4 files changed, 397 insertions(+)
 create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
 create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
 create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
 create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c

diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
new file mode 100644
index 0000000..21f5215
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
@@ -0,0 +1,105 @@
+/** ArmPlatformLib.c
+*
+*  Contains board initialization functions.
+*
+*  Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoard.c
+*
+*  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+*  Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+*  Copyright 2017 NXP
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Ppi/ArmMpCoreInfo.h>
+
+extern VOID SocInit (VOID);
+
+/**
+  Return the current Boot Mode
+
+  This function returns the boot reason on the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+  VOID
+  )
+{
+  return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+ Placeholder for Platform Initialization
+**/
+EFI_STATUS
+ArmPlatformInitialize (
+  IN  UINTN   MpId
+  )
+{
+ SocInit ();
+
+ return EFI_SUCCESS;
+}
+
+ARM_CORE_INFO LS1043aMpCoreInfoCTA53x4[] = {
+  {
+    // Cluster 0, Core 0
+    0x0, 0x0,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (EFI_PHYSICAL_ADDRESS)0,
+    (EFI_PHYSICAL_ADDRESS)0,
+    (EFI_PHYSICAL_ADDRESS)0,
+    (UINT64)0xFFFFFFFF
+  },
+};
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+  OUT UINTN                   *CoreCount,
+  OUT ARM_CORE_INFO           **ArmCoreTable
+  )
+{
+  *CoreCount    = sizeof (LS1043aMpCoreInfoCTA53x4) / sizeof (ARM_CORE_INFO);
+  *ArmCoreTable = LS1043aMpCoreInfoCTA53x4;
+
+  return EFI_SUCCESS;
+}
+
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR      gPlatformPpiTable[] = {
+  {
+    EFI_PEI_PPI_DESCRIPTOR_PPI,
+    &gArmMpCoreInfoPpiGuid,
+    &mMpCoreInfoPpi
+  }
+};
+
+VOID
+ArmPlatformGetPlatformPpiList (
+  OUT UINTN                   *PpiListSize,
+  OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList
+  )
+{
+  *PpiListSize = sizeof (gPlatformPpiTable);
+  *PpiList = gPlatformPpiTable;
+}
+
+
+UINTN
+ArmPlatformGetCorePosition (
+  IN UINTN MpId
+  )
+{
+  return 1;
+}
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
new file mode 100644
index 0000000..e4ec451
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
@@ -0,0 +1,70 @@
+#  @file
+#
+#  Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+#  Copyright 2017 NXP
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = PlatformLib
+  FILE_GUID                      = 736343a0-1d96-11e0-aaaa-0002a5d5c51b
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = ArmPlatformLib
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  Platform/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+  ArmLib
+  SocLib
+
+[Sources.common]
+  NxpQoriqLsHelper.S    | GCC
+  NxpQoriqLsMem.c
+  ArmPlatformLib.c
+
+[Ppis]
+  gArmMpCoreInfoPpiGuid
+
+[FeaturePcd]
+  gEmbeddedTokenSpaceGuid.PcdCacheEnable
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdArmPrimaryCore
+  gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
+  gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size
+  gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size
+  gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize
+  gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize
+  gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize
+  gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize
+  gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize
+  gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdDram1Size
+  gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdDram2Size
+  gNxpQoriqLsTokenSpaceGuid.PcdDram3BaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdDram3Size
+  gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
new file mode 100644
index 0000000..2e085c9
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
@@ -0,0 +1,38 @@
+#  @file
+#
+#  Copyright (c) 2012-2013, ARM Limited. All rights reserved.
+#  Copyright 2017 NXP
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+#include <AsmMacroIoLibV8.h>
+#include <AutoGen.h>
+
+.text
+.align 2
+
+GCC_ASM_IMPORT(ArmReadMpidr)
+
+ASM_FUNC(ArmPlatformIsPrimaryCore)
+  tst x0, #3
+  cset x0, eq
+  ret
+
+ASM_FUNC(ArmPlatformPeiBootAction)
+EL1_OR_EL2(x0)
+1:
+2:
+  ret
+
+ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
+  MOV32 (x0, FixedPcdGet32(PcdArmPrimaryCore))
+  ldrh   w0, [x0]
+  ret
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
new file mode 100644
index 0000000..72be71a
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
@@ -0,0 +1,184 @@
+/** NxpQoriqLsMem.c
+*
+*  Board memory specific Library.
+*
+*  Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c
+*
+*  Copyright (c) 2011, ARM Limited. All rights reserved.
+*  Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+*  Copyright 2017 NXP
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution. The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS          25
+
+#define CCSR_BASE_ADDR            FixedPcdGet64 (PcdCcsrBaseAddr)
+#define CCSR_SIZE                 FixedPcdGet64 (PcdCcsrSize)
+#define IFC_REGION1_BASE_ADDR     FixedPcdGet64 (PcdIfcRegion1BaseAddr)
+#define IFC_REGION1_SIZE          FixedPcdGet64 (PcdIfcRegion1Size)
+#define IFC_REGION2_BASE_ADDR     FixedPcdGet64 (PcdIfcRegion2BaseAddr)
+#define IFC_REGION2_SIZE          FixedPcdGet64 (PcdIfcRegion2Size)
+#define QMAN_SWP_BASE_ADDR        FixedPcdGet64 (PcdQmanSwpBaseAddr)
+#define QMAN_SWP_SIZE             FixedPcdGet64 (PcdQmanSwpSize)
+#define BMAN_SWP_BASE_ADDR        FixedPcdGet64 (PcdBmanSwpBaseAddr)
+#define BMAN_SWP_SIZE             FixedPcdGet64 (PcdBmanSwpSize)
+#define PCI_EXP1_BASE_ADDR        FixedPcdGet64 (PcdPciExp1BaseAddr)
+#define PCI_EXP1_BASE_SIZE        FixedPcdGet64 (PcdPciExp1BaseSize)
+#define PCI_EXP2_BASE_ADDR        FixedPcdGet64 (PcdPciExp2BaseAddr)
+#define PCI_EXP2_BASE_SIZE        FixedPcdGet64 (PcdPciExp2BaseSize)
+#define PCI_EXP3_BASE_ADDR        FixedPcdGet64 (PcdPciExp3BaseAddr)
+#define PCI_EXP3_BASE_SIZE        FixedPcdGet64 (PcdPciExp3BaseSize)
+#define DRAM1_BASE_ADDR           FixedPcdGet64 (PcdDram1BaseAddr)
+#define DRAM1_SIZE                FixedPcdGet64 (PcdDram1Size)
+#define DRAM2_BASE_ADDR           FixedPcdGet64 (PcdDram2BaseAddr)
+#define DRAM2_SIZE                FixedPcdGet64 (PcdDram2Size)
+#define DRAM3_BASE_ADDR           FixedPcdGet64 (PcdDram3BaseAddr)
+#define DRAM3_SIZE                FixedPcdGet64 (PcdDram3Size)
+#define QSPI_REGION_BASE_ADDR     FixedPcdGet64 (PcdQspiRegionBaseAddr)
+#define QSPI_REGION_SIZE          FixedPcdGet64 (PcdQspiRegionSize)
+
+/**
+  Return the Virtual Memory Map of your platform
+
+  This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
+
+  @param  VirtualMemoryMap     Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
+                               Virtual Memory mapping. This array must be ended by a zero-filled
+                               entry
+
+**/
+
+VOID
+ArmPlatformGetVirtualMemoryMap (
+  IN  ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap
+  )
+{
+  ARM_MEMORY_REGION_ATTRIBUTES     CacheAttributes;
+  UINTN                            Index;
+  ARM_MEMORY_REGION_DESCRIPTOR     *VirtualMemoryTable;
+
+  Index = 0;
+
+  ASSERT (VirtualMemoryMap != NULL);
+
+  VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages (
+          EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
+
+  if (VirtualMemoryTable == NULL) {
+    return;
+  }
+
+  if (FeaturePcdGet (PcdCacheEnable) == TRUE) {
+    CacheAttributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+  } else {
+    CacheAttributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+  }
+
+  // DRAM1 (Must be 1st entry)
+  VirtualMemoryTable[Index].PhysicalBase = DRAM1_BASE_ADDR;
+  VirtualMemoryTable[Index].VirtualBase  = DRAM1_BASE_ADDR;
+  VirtualMemoryTable[Index].Length       = DRAM1_SIZE;
+  VirtualMemoryTable[Index].Attributes   = CacheAttributes;
+
+  // CCSR Space
+  VirtualMemoryTable[++Index].PhysicalBase = CCSR_BASE_ADDR;
+  VirtualMemoryTable[Index].VirtualBase  = CCSR_BASE_ADDR;
+  VirtualMemoryTable[Index].Length       = CCSR_SIZE;
+  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+  // IFC region 1
+  //
+  // A-009241   : Unaligned write transactions to IFC may result in corruption of data
+  // Affects    : IFC
+  // Description: 16 byte unaligned write from system bus to IFC may result in extra unintended
+  //              writes on external IFC interface that can corrupt data on external flash.
+  // Impact     : Data corruption on external flash may happen in case of unaligned writes to
+  //              IFC memory space.
+  // Workaround: Following are the workarounds:
+  //             For write transactions from core, IFC interface memories (including IFC SRAM)
+  //                should be configured as device type memory in MMU.
+  //             For write transactions from non-core masters (like system DMA), the address
+  //                should be 16 byte aligned and the data size should be multiple of 16 bytes.
+  //
+  VirtualMemoryTable[++Index].PhysicalBase = IFC_REGION1_BASE_ADDR;
+  VirtualMemoryTable[Index].VirtualBase  = IFC_REGION1_BASE_ADDR;
+  VirtualMemoryTable[Index].Length       = IFC_REGION1_SIZE;
+  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+  // QMAN SWP
+  VirtualMemoryTable[++Index].PhysicalBase = QMAN_SWP_BASE_ADDR;
+  VirtualMemoryTable[Index].VirtualBase  = QMAN_SWP_BASE_ADDR;
+  VirtualMemoryTable[Index].Length       = QMAN_SWP_SIZE;
+  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+
+  // BMAN SWP
+  VirtualMemoryTable[++Index].PhysicalBase = BMAN_SWP_BASE_ADDR;
+  VirtualMemoryTable[Index].VirtualBase  = BMAN_SWP_BASE_ADDR;
+  VirtualMemoryTable[Index].Length       = BMAN_SWP_SIZE;
+  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+
+  // IFC region 2
+  VirtualMemoryTable[++Index].PhysicalBase = IFC_REGION2_BASE_ADDR;
+  VirtualMemoryTable[Index].VirtualBase  = IFC_REGION2_BASE_ADDR;
+  VirtualMemoryTable[Index].Length       = IFC_REGION2_SIZE;
+  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+  // DRAM2
+  VirtualMemoryTable[++Index].PhysicalBase = DRAM2_BASE_ADDR;
+  VirtualMemoryTable[Index].VirtualBase  = DRAM2_BASE_ADDR;
+  VirtualMemoryTable[Index].Length       = DRAM2_SIZE;
+  VirtualMemoryTable[Index].Attributes   = CacheAttributes;
+
+  // PCIe1
+  VirtualMemoryTable[++Index].PhysicalBase = PCI_EXP1_BASE_ADDR;
+  VirtualMemoryTable[Index].VirtualBase  = PCI_EXP1_BASE_ADDR;
+  VirtualMemoryTable[Index].Length       = PCI_EXP1_BASE_SIZE;
+  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+  // PCIe2
+  VirtualMemoryTable[++Index].PhysicalBase = PCI_EXP2_BASE_ADDR;
+  VirtualMemoryTable[Index].VirtualBase  = PCI_EXP2_BASE_ADDR;
+  VirtualMemoryTable[Index].Length       = PCI_EXP2_BASE_SIZE;
+  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+  // PCIe3
+  VirtualMemoryTable[++Index].PhysicalBase = PCI_EXP3_BASE_ADDR;
+  VirtualMemoryTable[Index].VirtualBase  = PCI_EXP3_BASE_ADDR;
+  VirtualMemoryTable[Index].Length       = PCI_EXP3_BASE_SIZE;
+  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+  // DRAM3
+  VirtualMemoryTable[++Index].PhysicalBase = DRAM3_BASE_ADDR;
+  VirtualMemoryTable[Index].VirtualBase  = DRAM3_BASE_ADDR;
+  VirtualMemoryTable[Index].Length       = DRAM3_SIZE;
+  VirtualMemoryTable[Index].Attributes   = CacheAttributes;
+
+  // QSPI region
+  VirtualMemoryTable[++Index].PhysicalBase = QSPI_REGION_BASE_ADDR;
+  VirtualMemoryTable[Index].VirtualBase  = QSPI_REGION_BASE_ADDR;
+  VirtualMemoryTable[Index].Length       = QSPI_REGION_SIZE;
+  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+
+  // End of Table
+  VirtualMemoryTable[++Index].PhysicalBase = 0;
+  VirtualMemoryTable[Index].VirtualBase  = 0;
+  VirtualMemoryTable[Index].Length       = 0;
+  VirtualMemoryTable[Index].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)0;
+
+  ASSERT ((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
+
+  *VirtualMemoryMap = VirtualMemoryTable;
+}
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [PATCH edk2-platforms] [PATCH v3 8/9] Compilation : Add the fdf, dsc and dec files.
  2017-11-27 10:51 [PATCH edk2-platforms] [PATCH v3 0/9] Platform/NXP Meenakshi Aggarwal
                   ` (6 preceding siblings ...)
  2017-11-27 10:51 ` [PATCH edk2-platforms] [PATCH v3 7/9] Platform/NXP: Add support for ArmPlatformLib Meenakshi Aggarwal
@ 2017-11-27 10:51 ` Meenakshi Aggarwal
  2017-11-27 10:51 ` [PATCH edk2-platforms] [PATCH v3 9/9] Build : Add build script and environment script Meenakshi Aggarwal
  2017-11-27 12:05 ` [PATCH edk2-platforms] [PATCH v3 0/9] Platform/NXP Leif Lindholm
  9 siblings, 0 replies; 25+ messages in thread
From: Meenakshi Aggarwal @ 2017-11-27 10:51 UTC (permalink / raw)
  To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel

The firmware device, description and declaration files.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec |  29 ++
 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc |  77 +++++
 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 281 +++++++++++++++++
 Platform/NXP/NxpQoriqLs.dec                  | 248 +++++++++++++++
 Platform/NXP/NxpQoriqLs.dsc                  | 453 +++++++++++++++++++++++++++
 Silicon/NXP/LS1043A/LS1043A.dec              |  22 ++
 Silicon/NXP/LS1043A/LS1043A.dsc              |  82 +++++
 7 files changed, 1192 insertions(+)
 create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec
 create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
 create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
 create mode 100644 Platform/NXP/NxpQoriqLs.dec
 create mode 100644 Platform/NXP/NxpQoriqLs.dsc
 create mode 100644 Silicon/NXP/LS1043A/LS1043A.dec
 create mode 100644 Silicon/NXP/LS1043A/LS1043A.dsc

diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec
new file mode 100644
index 0000000..af40169
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec
@@ -0,0 +1,29 @@
+#  LS1043aRdbPkg.dec
+#  LS1043a board package.
+#
+#  Copyright 2017 NXP
+#
+#  This program and the accompanying materials are licensed and made available under
+#  the terms and conditions of the BSD License which accompanies this distribution.
+#  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+  PACKAGE_NAME                   = LS1043aRdbPkg
+  PACKAGE_GUID                   = 6eba6648-d853-4eb3-9761-528b82d5ab04
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+#                   Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+[Includes.common]
+  Include                        # Root include for the package
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
new file mode 100644
index 0000000..19d4d30
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -0,0 +1,77 @@
+#  LS1043aRdbPkg.dsc
+#
+#  LS1043ARDB Board package.
+#
+#  Copyright 2017 NXP
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  #
+  # Defines for default states.  These can be changed on the command line.
+  # -D FLAG=VALUE
+  #
+  PLATFORM_NAME                  = LS1043aRdbPkg
+  PLATFORM_GUID                  = 60169ec4-d2b4-44f8-825e-f8684fd42e4f
+  OUTPUT_DIRECTORY               = Build/LS1043aRdbPkg
+  FLASH_DEFINITION               = edk2-platforms/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
+
+!include ../NxpQoriqLs.dsc
+!include ../../../Silicon/NXP/LS1043A/LS1043A.dsc
+
+[LibraryClasses.common]
+  ArmPlatformLib|edk2-platforms/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
+  ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
+  SerialPortLib|edk2-platforms/Platform/NXP/Library/DUartPortLib/DUartPortLib.inf
+  BeIoLib|edk2-platforms/Platform/NXP/Library/BeIoLib/BeIoLib.inf
+  SocLib|edk2-platforms/Silicon/NXP/Chassis/LS1043aSocLib.inf
+  RealTimeClockLib|edk2-platforms/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
+
+[PcdsFixedAtBuild.common]
+  gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"LS1043a RDB board"
+
+  #
+  # Board Specific Pcds
+  #
+  gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE
+  gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1
+
+  #
+  # Big Endian IPs
+  #
+  gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
+  gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|TRUE
+
+  #
+  # I2C controller Pcds
+  #
+  gNxpQoriqLsTokenSpaceGuid.PcdI2cBus|0
+
+  #
+  # RTC Pcds
+  #
+  gDs1307RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0x68
+  gDs1307RtcLibTokenSpaceGuid.PcdI2cBusFrequency|100000
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+  edk2-platforms/Platform/NXP/Drivers/WatchDog/WatchDogDxe.inf
+  edk2-platforms/Platform/NXP/Drivers/I2cDxe/I2cDxe.inf
+
+ ##
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
new file mode 100644
index 0000000..9a8f242
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
@@ -0,0 +1,281 @@
+#  LS1043aRdbPkg.fdf
+#
+#  FLASH layout file for LS1043a board.
+#
+#  Copyright (c) 2016, Freescale Ltd. All rights reserved.
+#  Copyright 2017 NXP
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into  the Flash Device Image.  Each FD section
+# defines one flash "device" image.  A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash"  image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.LS1043ARDB_EFI]
+BaseAddress   = 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress  #The base address of the FLASH Device.
+Size          = 0x000EC890|gArmTokenSpaceGuid.PcdFdSize         #The size in bytes of the FLASH Device
+ErasePolarity = 1
+BlockSize     = 0x1
+NumBlocks     = 0xEC890
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+0x00000000|0x000EC890
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = FVMAIN_COMPACT
+
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file.  This section also defines order the components and modules are positioned
+# within the image.  The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+FvNameGuid         = 1037c42b-8452-4c41-aac7-41e6c31468da
+BlockSize          = 0x1
+NumBlocks          = 0         # This FV gets compressed so make it just big enough
+FvAlignment        = 8         # FV alignment and FV attributes setting.
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  INF MdeModulePkg/Core/Dxe/DxeMain.inf
+  INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+  #
+  # PI DXE Drivers producing Architectural Protocols (EFI Services)
+  #
+  INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+
+  INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+  INF edk2-platforms/Platform/NXP/Drivers/WatchDog/WatchDogDxe.inf
+  INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+  INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+  INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+  INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+  INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+
+  #
+  # Multiple Console IO support
+  #
+  INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+  INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+  INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+  INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
+
+  #
+  # Network modules
+  #
+  INF  MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+  INF  MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+  INF  MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+  INF  MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+  INF  MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+  INF  MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+  INF  MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+  INF  MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+  INF  MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+  INF  MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+  INF  MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+!if $(NETWORK_IP6_ENABLE) == TRUE
+  INF  NetworkPkg/Ip6Dxe/Ip6Dxe.inf
+  INF  NetworkPkg/TcpDxe/TcpDxe.inf
+  INF  NetworkPkg/Udp6Dxe/Udp6Dxe.inf
+  INF  NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
+  INF  NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
+  INF  NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
+!else
+  INF  MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+!endif
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+  INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  INF FatPkg/FatPei/FatPei.inf
+  INF FatPkg/EnhancedFatDxe/Fat.inf
+
+  #
+  # UEFI application (Shell Embedded Boot Loader)
+  #
+  INF ShellPkg/Application/Shell/Shell.inf
+
+  #
+  # Bds
+  #
+  INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+  INF edk2-platforms/Platform/NXP/Drivers/I2cDxe/I2cDxe.inf
+
+[FV.FVMAIN_COMPACT]
+FvAlignment        = 8
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  INF ArmPlatformPkg/PrePi/PeiUniCore.inf
+
+  FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+      SECTION FV_IMAGE = FVMAIN
+    }
+  }
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+[Rule.Common.SEC]
+  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+    TE  TE    Align = 32                $(INF_OUTPUT)/$(MODULE_NAME).efi
+  }
+
+[Rule.Common.PEI_CORE]
+  FILE PEI_CORE = $(NAMED_GUID) {
+    TE     TE                           $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI     STRING ="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.PEIM]
+  FILE PEIM = $(NAMED_GUID) {
+     PEI_DEPEX PEI_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex
+     PE32      PE32                     $(INF_OUTPUT)/$(MODULE_NAME).efi
+     UI       STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.PEIM.TIANOCOMPRESSED]
+  FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
+    PEI_DEPEX PEI_DEPEX Optional        $(INF_OUTPUT)/$(MODULE_NAME).depex
+    GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
+      PE32      PE32                    $(INF_OUTPUT)/$(MODULE_NAME).efi
+      UI        STRING="$(MODULE_NAME)" Optional
+    }
+  }
+
+[Rule.Common.DXE_CORE]
+  FILE DXE_CORE = $(NAMED_GUID) {
+    PE32     PE32                       $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI       STRING="$(MODULE_NAME)" Optional
+  }
+
+
+[Rule.Common.UEFI_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.DXE_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.UEFI_APPLICATION]
+  FILE APPLICATION = $(NAMED_GUID) {
+    UI     STRING ="$(MODULE_NAME)" Optional
+    PE32   PE32                         $(INF_OUTPUT)/$(MODULE_NAME).efi
+  }
+
+[Rule.Common.UEFI_DRIVER.BINARY]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX DXE_DEPEX Optional      |.depex
+    PE32      PE32                    |.efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.UEFI_APPLICATION.BINARY]
+  FILE APPLICATION = $(NAMED_GUID) {
+    PE32      PE32                    |.efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
diff --git a/Platform/NXP/NxpQoriqLs.dec b/Platform/NXP/NxpQoriqLs.dec
new file mode 100644
index 0000000..4af35a1
--- /dev/null
+++ b/Platform/NXP/NxpQoriqLs.dec
@@ -0,0 +1,248 @@
+#  @file.
+#
+#  Copyright 2017 NXP
+#
+#  This program and the accompanying materials are licensed and made available under
+#  the terms and conditions of the BSD License which accompanies this distribution.
+#  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+  DEC_SPECIFICATION              = 0x00010005
+  PACKAGE_VERSION                = 0.1
+
+[Includes]
+  .
+  Include
+
+[Guids.common]
+  gNxpQoriqLsTokenSpaceGuid      = {0x98657342, 0x4aee, 0x4fc6, {0xbc, 0xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}}
+
+[PcdsFixedAtBuild.common]
+  #
+  # Pcds for I2C Controller
+  #
+  gNxpQoriqLsTokenSpaceGuid.PcdI2cBus|0|UINT32|0x00000001
+  gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed|0|UINT32|0x00000002
+  gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|0|UINT32|0x00000003
+
+  #
+  # Pcds for base address and size
+  #
+  gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x0|UINT64|0x00000100
+  gNxpQoriqLsTokenSpaceGuid.PcdPiFdSize|0x0|UINT32|0x00000101
+  gNxpQoriqLsTokenSpaceGuid.PcdPiFdBaseAddress|0x0|UINT64|0x00000102
+  gNxpQoriqLsTokenSpaceGuid.PcdDspiBaseAddr|0|UINT64|0x00000103
+  gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x0|UINT64|0x00000104
+  gNxpQoriqLsTokenSpaceGuid.PcdWdog1BaseAddr|0x0|UINT64|0x00000105
+  gNxpQoriqLsTokenSpaceGuid.PcdWdog2BaseAddr|0x0|UINT64|0x00000106
+  gNxpQoriqLsTokenSpaceGuid.PcdWdog3BaseAddr|0x0|UINT64|0x00000107
+  gNxpQoriqLsTokenSpaceGuid.PcdWdog4BaseAddr|0x0|UINT64|0x00000108
+  gNxpQoriqLsTokenSpaceGuid.PcdWdog5BaseAddr|0x0|UINT64|0x00000109
+  gNxpQoriqLsTokenSpaceGuid.PcdDdrBaseAddr|0x0|UINT64|0x0000010A
+  gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0|UINT64|0x0000010B
+  gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0|UINT64|0x0000010C
+  gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0|UINT64|0x0000010D
+  gNxpQoriqLsTokenSpaceGuid.PcdI2c1BaseAddr|0|UINT64|0x0000010E
+  gNxpQoriqLsTokenSpaceGuid.PcdI2c2BaseAddr|0|UINT64|0x0000010F
+  gNxpQoriqLsTokenSpaceGuid.PcdI2c3BaseAddr|0|UINT64|0x00000110
+  gNxpQoriqLsTokenSpaceGuid.PcdSataController1BaseAddress|0x0|UINT32|0x00000111
+  gNxpQoriqLsTokenSpaceGuid.PcdSataController2BaseAddress|0x0|UINT32|0x00000112
+  gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000|UINT64|0x00000113
+  gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000|UINT64|0x00000114
+  gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000|UINT64|0x00000115
+  gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0080000000|UINT64|0x00000116
+  gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x0|UINT64|0x00000117
+  gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x0|UINT64|0x00000118
+  gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x0|UINT64|0x00000119
+  gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x0|UINT64|0x0000011A
+  gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x0|UINT64|0x0000011B
+  gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x0|UINT64|0x0000011C
+  gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr|0x3800000000|UINT64|0x000011D
+  gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseSize|0x800000000|UINT64|0x000011E
+  gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr|0x0080000000|UINT64|0x0000011F
+  gNxpQoriqLsTokenSpaceGuid.PcdDram1Size|0x0080000000|UINT64|0x00000120
+  gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr|0x0880000000|UINT64|0x00000121
+  gNxpQoriqLsTokenSpaceGuid.PcdDram2Size|0x0780000000|UINT64|0x00000122
+  gNxpQoriqLsTokenSpaceGuid.PcdDram3BaseAddr|0x8800000000|UINT64|0x00000123
+  gNxpQoriqLsTokenSpaceGuid.PcdDram3Size|0x7800000000|UINT64|0x00000124
+  gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000|UINT64|0x00000125
+  gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000|UINT64|0x00000126
+  gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2BaseAddr|0x0|UINT64|0x00000127
+  gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2Size|0x0|UINT64|0x00000128
+  gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExBase|0|UINT64|0x00000129
+  gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExSize|0|UINT64|0x0000012A
+  gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr|0|UINT32|0x0000012B
+  gNxpQoriqLsTokenSpaceGuid.PcdUsbSize|0|UINT32|0x0000012C
+  gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000|UINT64|0x0000012D
+  gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000|UINT64|0x0000012E
+  gNxpQoriqLsTokenSpaceGuid.PcdDramMemSize|0x0|UINT64|0x0000012F
+
+  #
+  # DSPI Pcds
+  #
+  gNxpQoriqLsTokenSpaceGuid.PcdDspiSpeed|0|UINT32|0x00000150
+  gNxpQoriqLsTokenSpaceGuid.PcdDspiMode|0|UINT32|0x00000151
+  gNxpQoriqLsTokenSpaceGuid.PcdDspiBusNumber|0|UINT32|0x00000152
+  gNxpQoriqLsTokenSpaceGuid.PcdDspiCs|0|UINT32|0x00000153
+
+  #
+  # IFC PCDs
+  #
+  gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x60000000|UINT64|0x00000190
+  gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x20000000|UINT64|0x00000191
+  gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0620000000|UINT64|0x00000192
+  gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x00E0000000|UINT64|0x00000193
+  gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x0|UINT32|0x00000194
+  gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x0|UINT64|0x00000195
+  gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x0|UINT64|0x00000196
+
+  #
+  # PCI PCDs
+  #
+  gNxpQoriqLsTokenSpaceGuid.PcdPciMaxPayloadFixup|FALSE|BOOLEAN|0x000001C0
+  gNxpQoriqLsTokenSpaceGuid.PcdKludgeMapPciMmioAsCached|FALSE|BOOLEAN|0x000001C1
+  gNxpQoriqLsTokenSpaceGuid.PcdPciBusMin|0|UINT64|0x000001C2
+  gNxpQoriqLsTokenSpaceGuid.PcdPciBusMax|255|UINT64|0x000001C3
+  gNxpQoriqLsTokenSpaceGuid.PcdPci1Mmio64Base|0x0|UINT64|0x000001C4
+  gNxpQoriqLsTokenSpaceGuid.PcdPci2Mmio64Base|0x0|UINT64|0x000001C5
+  gNxpQoriqLsTokenSpaceGuid.PcdPci3Mmio64Base|0x0|UINT64|0x000001C6
+  gNxpQoriqLsTokenSpaceGuid.PcdPci4Mmio64Base|0x0|UINT64|0x000001C7
+  gNxpQoriqLsTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x000001C8
+  gNxpQoriqLsTokenSpaceGuid.PcdPciExp1SysAddr|0x0|UINT64|0x000001C9
+  gNxpQoriqLsTokenSpaceGuid.PcdPciExp2SysAddr|0x0|UINT64|0x000001CA
+  gNxpQoriqLsTokenSpaceGuid.PcdPciExp3SysAddr|0x0|UINT64|0x000001CB
+  gNxpQoriqLsTokenSpaceGuid.PcdPciExp4SysAddr|0x0|UINT64|0x000001CC
+  gNxpQoriqLsTokenSpaceGuid.PcdPciDebug|FALSE|BOOLEAN|0x000001CD
+  gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|0|UINT32|0x000001CE
+  gNxpQoriqLsTokenSpaceGuid.PcdPciMemOneTransaction|0x0|UINT64|0x000001CF
+  gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x0|UINT64|0x000001D0
+  gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x0|UINT64|0x000001D1
+
+  #
+  # NV Pcd
+  #
+  gNxpQoriqLsTokenSpaceGuid.PcdNvFdBase|0x0|UINT64|0x00000210
+  gNxpQoriqLsTokenSpaceGuid.PcdNvFdSize|0x0|UINT64|0x00000211
+
+  #
+  # QSPI PCDs
+  #
+  gNxpQoriqLsTokenSpaceGuid.PcdQspiFdtCompatible|""|VOID*|0x00000220
+  gNxpQoriqLsTokenSpaceGuid.PcdFdtAddress|0|UINT64|0x00000221
+
+  #
+  # Platform PCDs
+  #
+  gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0|UINT32|0x00000250
+  gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE|BOOLEAN|0x00000251
+  gNxpQoriqLsTokenSpaceGuid.PcdIfcNorEnabled|0x0|UINT64|0x00000252
+  gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3|FALSE|BOOLEAN|0x00000253
+
+  #
+  # Erratum PCDs
+  #
+  gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x00000270
+  gNxpQoriqLsTokenSpaceGuid.PcdUsbErratumA009007|FALSE|BOOLEAN|0x00000271
+  gNxpQoriqLsTokenSpaceGuid.PcdErratumA008751|FALSE|BOOLEAN|0x00000272
+  gNxpQoriqLsTokenSpaceGuid.PcdErratumA009008|FALSE|BOOLEAN|0x00000273
+  gNxpQoriqLsTokenSpaceGuid.PcdErratumA009798|FALSE|BOOLEAN|0x00000274
+  gNxpQoriqLsTokenSpaceGuid.PcdErratumA008514|FALSE|BOOLEAN|0x00000275
+  gNxpQoriqLsTokenSpaceGuid.PcdErratumA008336|FALSE|BOOLEAN|0x00000276
+  gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA009185|FALSE|BOOLEAN|0x00000277
+
+  #
+  # Test PCDs
+  #
+  gNxpQoriqLsTokenSpaceGuid.PcdDspiTest|FALSE|BOOLEAN|0x00000290
+
+  #
+  # Clock PCDs
+  #
+  gNxpQoriqLsTokenSpaceGuid.PcdSysClk|0x0|UINT64|0x000002A0
+  gNxpQoriqLsTokenSpaceGuid.PcdDdrClk|0x0|UINT64|0x000002A1
+
+  #
+  # DPAA1 PCDs
+  #
+  # Valid values for PcdDpaa1DebugFlags:
+  # - 0x1      Enable DPAA1 debugging messages
+  # - 0x2      Dump values of RAM words or registers
+  # - 0x4      Perform extra checks
+  # - 0x8      Trace sent/received network packets
+  #
+  gNxpQoriqLsTokenSpaceGuid.PcdDpaa1Initialize|FALSE|BOOLEAN|0x000002B0
+  gNxpQoriqLsTokenSpaceGuid.PcdDpaa1DebugFlags|0x0|UINT32|0x000002B1
+  gNxpQoriqLsTokenSpaceGuid.PcdFManFwFlashAddr|0x0|UINT32|0x000002B2
+  gNxpQoriqLsTokenSpaceGuid.PcdSgmiiPrtclInit|FALSE|BOOLEAN|0x000002B3
+  #
+  # Bit mask to indicate the DPAA1 MEMACs to be used.
+  # MeMaci is selected to be used, if bit 'i - 1' is set in the bit mask,
+  # where i is the range '1 .. #Memacs'. For example, if we want MEMAC5
+  # to be used, the value of the mask needs to be 0x10 (bit 4 set)
+  #
+  gNxpQoriqLsTokenSpaceGuid.PcdDpaa1UsedMemacsMask|0x0|UINT64|0x000002B4
+  gNxpQoriqLsTokenSpaceGuid.PcdDpaa1FmanMdio1Addr|0x0|UINT64|0x000002B5
+  gNxpQoriqLsTokenSpaceGuid.PcdDpaa1FmanMdio2Addr|0x0|UINT64|0x000002B6
+  gNxpQoriqLsTokenSpaceGuid.PcdDpaa1FmanAddr|0x0|UINT64|0x000002B7
+
+  #
+  # DPAA2 PCDs
+  #
+  gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McPortalBaseAddr|0x0|UINT64|0x000002D0
+  gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McPortalSize|0x0|UINT64|0x000002D1
+  gNxpQoriqLsTokenSpaceGuid.PcdDpaa2NiPortalsBaseAddr|0x0|UINT64|0x000002D2
+  gNxpQoriqLsTokenSpaceGuid.PcdDpaa2NiPortalsSize|0x0|UINT64|0x000002D3
+  gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalsBaseAddr|0x0|UINT64|0x000002D4
+  gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalSize|0x0|UINT64|0x000002D5
+  gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalsCacheSize|0x0|UINT64|0x000002D6
+  gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McRamSize|0x0|UINT64|0x000002D7
+  gNxpQoriqLsTokenSpaceGuid.PcdDpaa2Initialize|FALSE|BOOLEAN|0x000002D8
+  gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McFwSrc|0x0|UINT8|0x000002D9
+  gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McFwNorAddr|0x0|UINT64|0x000002DA
+  gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McDpcNorAddr|0x0|UINT64|0x000002DB
+  gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McDplNorAddr|0x0|UINT64|0x000002DC
+  gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McDpcMaxLen|0x0|UINT32|0x000002DD
+  gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McDpcMcDramOffset|0x0|UINT32|0x000002DE
+  gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McDplMaxLen|0x0|UINT32|0x000002DF
+  gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McDplMcDramOffset|0x0|UINT32|0x000002E0
+  gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McPrivateRamSize|0x0|UINT32|0x000002E1
+  gNxpQoriqLsTokenSpaceGuid.PcdDpaa2StreamIdStart|0x0|UINT32|0x000002E2
+  gNxpQoriqLsTokenSpaceGuid.PcdDpaa2StreamIdEnd|0x0|UINT32|0x000002E3
+  gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McBootTimeoutMs|0x0|UINT32|0x000002E4
+  gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McLogMcDramOffset|0x0|UINT32|0x000002E5
+  gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McLogLevel|0x0|UINT8|0x000002E6
+  gNxpQoriqLsTokenSpaceGuid.PcdDpaa2DebugFlags|0x0|UINT32|0x000002E7
+  gNxpQoriqLsTokenSpaceGuid.PcdDpaa2CortinaFwSrc|0x0|UINT8|0x000002E8
+  gNxpQoriqLsTokenSpaceGuid.PcdDpaa2CortinaFwNorAddr|0x0|UINT64|0x000002E9
+  gNxpQoriqLsTokenSpaceGuid.PcdDpaa2CortinaFwMaxLen|0x0|UINT32|0x000002EA
+  gNxpQoriqLsTokenSpaceGuid.PcdDpaa2UsedDpmacsMask|0x0|UINT64|0x000002EB
+  gNxpQoriqLsTokenSpaceGuid.PcdMacDeviceDisableRegAddr|0x0|UINT64|0x000002EC
+  gNxpQoriqLsTokenSpaceGuid.PcdBypassAmqMask|0x0|UINT32|0x000002ED
+  gNxpQoriqLsTokenSpaceGuid.PcdMdioBustCount|0x0|UINT8|0x000002EE
+  gNxpQoriqLsTokenSpaceGuid.PcdDpaa2Wriop1Mdio1Addr|0x0|UINT64|0x000002EF
+  gNxpQoriqLsTokenSpaceGuid.PcdDpaa2Wriop1Mdio2Addr|0x0|UINT64|0x000002F0
+
+  #
+  # USB Pcds
+  #
+  gNxpQoriqLsTokenSpaceGuid.PcdNumUsbController|0|UINT32|0x00000300
+
+  #
+  # Pcds to support Big Endian IPs
+  #
+  gNxpQoriqLsTokenSpaceGuid.PcdMmcBigEndian|FALSE|BOOLEAN|0x0000310
+  gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|FALSE|BOOLEAN|0x0000311
+  gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x00000312
+  gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|FALSE|BOOLEAN|0x00000313
+
+  #
+  # System ID Eeprom Pcds
+  #
+  gNxpQoriqLsTokenSpaceGuid.PcdSysEepromI2cBus|0|UINT32|0x0000330
+  gNxpQoriqLsTokenSpaceGuid.PcdSysEepromI2cAddress|0|UINT32|0x0000331
diff --git a/Platform/NXP/NxpQoriqLs.dsc b/Platform/NXP/NxpQoriqLs.dsc
new file mode 100644
index 0000000..2ea3757
--- /dev/null
+++ b/Platform/NXP/NxpQoriqLs.dsc
@@ -0,0 +1,453 @@
+#  @file
+#
+#  Copyright (c) 2017 NXP.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  #
+  # Defines for default states.  These can be changed on the command line.
+  # -D FLAG=VALUE
+  #
+  PLATFORM_VERSION               = 0.1
+  DSC_SPECIFICATION              = 0x00010005
+  SUPPORTED_ARCHITECTURES        = AARCH64
+  BUILD_TARGETS                  = DEBUG|RELEASE
+  SKUID_IDENTIFIER               = DEFAULT
+
+[LibraryClasses.common]
+  ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+  ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
+  ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
+  ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
+  TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+  ArmTrustZoneLib|ArmPlatformPkg/Drivers/ArmTrustZone/ArmTrustZone.inf
+  ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
+  HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+  UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+  FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+  BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
+  PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+  UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+  CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+
+  # Networking Requirements
+  NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+  DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+  UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
+  IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
+
+  # ARM GIC400 General Interrupt Driver
+  ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
+  ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
+  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+  DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+  BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+  SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+  PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+  PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+  EfiFileLib|EmbeddedPkg/Library/EfiFileLib/EfiFileLib.inf
+  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+  PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
+  CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
+  DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
+  CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
+  PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
+  SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf
+  IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+  UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+  UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+  DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+  UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+  DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+  UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+  UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+  PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
+  CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+  ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
+  DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+  DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf
+  BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
+  FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
+  ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+  ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+  FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+  ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf
+  SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+  NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+  HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+  BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+  TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
+  AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
+  VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
+  NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
+  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+
+[LibraryClasses.common.SEC]
+  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
+  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+  ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
+  LzmaDecompressLib|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+  HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
+  PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
+  MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
+  PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+  PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
+  MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf
+
+  # 1/123 faster than Stm or Vstm version
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+
+  # Uncomment to turn on GDB stub in SEC.
+  #DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf
+
+[LibraryClasses.common.PEIM]
+  PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+  PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
+  PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+  PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+  HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+  MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+
+[LibraryClasses.common.DXE_CORE]
+  HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
+  MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
+  DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+  ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+  PeCoffLib|EmbeddedPkg/Library/DxeHobPeCoffLib/DxeHobPeCoffLib.inf
+  PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
+
+[LibraryClasses.common.DXE_DRIVER]
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+  SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
+  PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+  MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf
+
+[LibraryClasses.common.UEFI_APPLICATION]
+  PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+  UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+  PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+
+[LibraryClasses.common.UEFI_DRIVER]
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+  UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+  ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+  PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+  PeCoffLib|EmbeddedPkg/Library/DxeHobPeCoffLib/DxeHobPeCoffLib.inf
+
+[LibraryClasses.AARCH64]
+  #
+  # It is not possible to prevent the ARM compiler for generic intrinsic functions.
+  # This library provides the instrinsic functions generate by a given compiler.
+  # [LibraryClasses.ARM] and NULL mean link this library into all ARM images.
+  #
+  NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+
+[BuildOptions]
+  XCODE:*_*_ARM_PLATFORM_FLAGS == -arch armv7
+  GCC:*_*_ARM_PLATFORM_FLAGS == -march=armv7-a
+  RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu cortex-a9
+
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
+  GCC:*_*_ARM_DLINK_FLAGS = -z common-page-size=0x1000
+  GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+  ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
+  #  It could be set FALSE to save size.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE
+  gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE
+  gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE
+  gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE
+  gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE
+
+  #
+  # Control what commands are supported from the UI
+  # Turn these on and off to add features or save size
+  #
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedMacBoot|TRUE
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedDirCmd|TRUE
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedHobCmd|TRUE
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedHwDebugCmd|TRUE
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedPciDebugCmd|TRUE
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedIoEnable|FALSE
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedScriptCmd|FALSE
+  gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE
+
+  # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress
+  gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE
+  gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
+  gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
+
+[PcdsDynamicDefault.common]
+  #
+  # Set video resolution for boot options and for text setup.
+  # PlatformDxe can set the former at runtime.
+  #
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480
+
+[PcdsDynamicHii.common.DEFAULT]
+  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|10
+
+[PcdsFixedAtBuild.common]
+  gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000
+  gEmbeddedTokenSpaceGuid.PcdTimerPeriod|10000 # expressed in 100ns units, 100,000 x 100 ns = 10,000,000 ns = 10 ms
+  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800
+  gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }
+  gArmPlatformTokenSpaceGuid.PcdCoreCount|1 # Only one core
+  gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
+  gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|2000000
+  gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
+  gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
+  gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
+  gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1
+  gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
+  gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
+
+!if $(TARGET) == RELEASE
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x81000000
+!else
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x81000044
+!endif
+
+  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedAutomaticBootCommand|""
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000
+
+  #
+  # Optional feature to help prevent EFI memory map fragments
+  # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
+  # Values are in EFI Pages (4K). DXE Core will make sure that
+  # at least this much of each type of memory can be allocated
+  # from a single memory range. This way you only end up with
+  # maximum of two fragements for each type in the memory map
+  # (the memory used, and the free memory that was prereserved
+  # but not used).
+  #
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|80
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|40
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|3000
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|10
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
+
+  # Serial Terminal
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
+  gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
+
+  # Size of the region reserved for fixed address allocations (Reserved 32MB)
+  gArmTokenSpaceGuid.PcdArmLinuxKernelMaxOffset|0x08000000
+  gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x08000000
+  gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x0
+  gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x94A00000
+  gArmTokenSpaceGuid.PcdCpuResetAddress|0x94A00000
+
+  # Timer
+  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0
+
+  # We want to use the Shell Libraries but don't want it to initialise
+  # automatically. We initialise the libraries when the command is called by the
+  # Shell.
+  gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+
+  # Use the serial console for both ConIn & ConOut
+  gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi();"
+  gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()"
+  gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+  gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|16000
+!ifdef $(NO_SHELL_PROFILES)
+  gEfiShellPkgTokenSpaceGuid.PcdShellProfileMask|0x00
+!endif #$(NO_SHELL_PROFILES)
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+  #
+  # SEC
+  #
+  ArmPlatformPkg/PrePi/PeiUniCore.inf
+  MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  }
+
+  #
+  # DXE
+  #
+  MdeModulePkg/Core/Dxe/DxeMain.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+      NULL|EmbeddedPkg/Library/LzmaHobCustomDecompressLib/LzmaHobCustomDecompressLib.inf
+  }
+  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  }
+
+  #
+  # Architectural Protocols
+  #
+  ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+  MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+  EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+
+  # FDT installation
+  EmbeddedPkg/Drivers/FdtPlatformDxe/FdtPlatformDxe.inf
+  MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+  MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+  MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+  EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+  ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+  ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
+
+  #
+  # Networking stack
+  #
+  MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+  MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+  MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+  MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+  MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+  MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+  MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+  MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+  MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+  MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+  MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+!if $(NETWORK_IP6_ENABLE) == TRUE
+  NetworkPkg/Ip6Dxe/Ip6Dxe.inf
+  NetworkPkg/TcpDxe/TcpDxe.inf
+  NetworkPkg/Udp6Dxe/Udp6Dxe.inf
+  NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
+  NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
+  NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
+!else
+  MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+!endif
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  FatPkg/FatPei/FatPei.inf
+  FatPkg/EnhancedFatDxe/Fat.inf
+
+  #
+  # Bds
+  #
+  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  MdeModulePkg/Application/UiApp/UiApp.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
+  }
+  MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+  #
+  # Example Application
+  #
+  MdeModulePkg/Application/HelloWorld/HelloWorld.inf
+  ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+  ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+  ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+  ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+  ShellPkg/Library/UefiDpLib/UefiDpLib.inf {
+    <LibraryClasses>
+      TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf
+      PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+      DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+  }
+  ShellPkg/Application/Shell/Shell.inf {
+    <LibraryClasses>
+      NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+!ifndef $(NO_SHELL_PROFILES)
+      NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf
+!ifdef $(INCLUDE_DP)
+      NULL|ShellPkg/Library/UefiDpLib/UefiDpLib.inf
+!endif #$(INCLUDE_DP)
+!ifdef $(INCLUDE_TFTP_COMMAND)
+      NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf
+!endif #$(INCLUDE_TFTP_COMMAND)
+!endif #$(NO_SHELL_PROFILES)
+  }
+
+  ##
diff --git a/Silicon/NXP/LS1043A/LS1043A.dec b/Silicon/NXP/LS1043A/LS1043A.dec
new file mode 100644
index 0000000..0648327
--- /dev/null
+++ b/Silicon/NXP/LS1043A/LS1043A.dec
@@ -0,0 +1,22 @@
+# LS1043A.dec
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+  DEC_SPECIFICATION              = 0x00010005
+
+[Guids.common]
+  gNxpLs1043ATokenSpaceGuid      = {0x6834fe45, 0x4aee, 0x4fc6, {0xbc, 0xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}}
+
+[Includes]
+  Include
diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc b/Silicon/NXP/LS1043A/LS1043A.dsc
new file mode 100644
index 0000000..e2c19bf
--- /dev/null
+++ b/Silicon/NXP/LS1043A/LS1043A.dsc
@@ -0,0 +1,82 @@
+#  LS1043A.dsc
+#  LS1043A Soc package.
+#
+#  Copyright 2017 NXP
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsDynamicDefault.common]
+
+  #
+  # ARM General Interrupt Controller
+  gArmTokenSpaceGuid.PcdGicDistributorBase|0x01401000
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x01402000
+
+[PcdsFixedAtBuild.common]
+
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"LS1043a"
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
+
+  #
+  # LS1043a board Specific PCDs
+  # XX (DRAM - Region 1 2GB)
+  # (NOR - IFC Region 1 512MB)
+  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
+  gArmTokenSpaceGuid.PcdSystemMemorySize|0x80000000
+  gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000
+
+  #
+  # CCSR Address Space and other attached Memories
+  #
+  gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000
+  gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000
+  gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x01EE1000
+  gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x60000000
+  gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x20000000
+  gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0620000000
+  gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x00E0000000
+  gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x2EA
+  gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000
+  gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000
+  gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000
+  gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0080000000
+  gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x4000000000
+  gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x800000000
+  gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x4800000000
+  gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x800000000
+  gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x5000000000
+  gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x800000000
+  gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr|0x0080000000
+  gNxpQoriqLsTokenSpaceGuid.PcdDram1Size|0x0080000000
+  gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr|0x0880000000
+  gNxpQoriqLsTokenSpaceGuid.PcdDram2Size|0x0780000000
+  gNxpQoriqLsTokenSpaceGuid.PcdDram3BaseAddr|0x8800000000
+  gNxpQoriqLsTokenSpaceGuid.PcdDram3Size|0x7800000000
+  gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x1570000
+  gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x01EE0000
+  gNxpQoriqLsTokenSpaceGuid.PcdWdog1BaseAddr|0x02AD0000
+  gNxpQoriqLsTokenSpaceGuid.PcdWdog2BaseAddr|0x02AE0000
+  gNxpQoriqLsTokenSpaceGuid.PcdWdog3BaseAddr|0x02A70000
+  gNxpQoriqLsTokenSpaceGuid.PcdWdog4BaseAddr|0x02A80000
+  gNxpQoriqLsTokenSpaceGuid.PcdWdog5BaseAddr|0x02A90000
+  gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x01560000
+  gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02180000
+  gNxpQoriqLsTokenSpaceGuid.PcdI2c1BaseAddr|0x02190000
+  gNxpQoriqLsTokenSpaceGuid.PcdI2c2BaseAddr|0x021A0000
+  gNxpQoriqLsTokenSpaceGuid.PcdI2c3BaseAddr|0x021B0000
+  gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
+
+##
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [PATCH edk2-platforms] [PATCH v3 9/9] Build : Add build script and environment script
  2017-11-27 10:51 [PATCH edk2-platforms] [PATCH v3 0/9] Platform/NXP Meenakshi Aggarwal
                   ` (7 preceding siblings ...)
  2017-11-27 10:51 ` [PATCH edk2-platforms] [PATCH v3 8/9] Compilation : Add the fdf, dsc and dec files Meenakshi Aggarwal
@ 2017-11-27 10:51 ` Meenakshi Aggarwal
  2017-11-27 12:05 ` [PATCH edk2-platforms] [PATCH v3 0/9] Platform/NXP Leif Lindholm
  9 siblings, 0 replies; 25+ messages in thread
From: Meenakshi Aggarwal @ 2017-11-27 10:51 UTC (permalink / raw)
  To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel

Build script and Environment setup script.
Readme to explain how to run build script

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
 Platform/NXP/Env.cshrc |  77 ++++++++++++++++++++++++++++++++++++
 Platform/NXP/Readme.md |  15 +++++++
 Platform/NXP/build.sh  | 103 +++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 195 insertions(+)
 create mode 100755 Platform/NXP/Env.cshrc
 create mode 100644 Platform/NXP/Readme.md
 create mode 100755 Platform/NXP/build.sh

diff --git a/Platform/NXP/Env.cshrc b/Platform/NXP/Env.cshrc
new file mode 100755
index 0000000..31abb04
--- /dev/null
+++ b/Platform/NXP/Env.cshrc
@@ -0,0 +1,77 @@
+#  @file.
+#
+#  Copyright 2017 NXP
+#
+#  This program and the accompanying materials are licensed and made available under
+#  the terms and conditions of the BSD License which accompanies this distribution.
+#  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+unset GCC_UTILITY GCC_VERSION MajorVersion MinorVersion
+
+if [ X"$CROSS_COMPILE_64" != X"" ]; then
+  ARM64_PREFIX="$CROSS_COMPILE_64"
+elif [ X"$CROSS_COMPILE" != X"" ]; then
+  ARM64_PREFIX="$CROSS_COMPILE"
+else
+  ARM64_PREFIX="aarch64-linux-gnu-"
+fi
+
+GCC_UTILITY="${ARM64_PREFIX}gcc"
+CheckGcc=`which $GCC_UTILITY >/dev/null 2>&1`
+if [ "$?" -eq 0 ];then
+  GCC_VERSION=`$GCC_UTILITY -v 2>&1 | tail -n 1 | awk '{print $3}'`
+  MajorVersion=`echo $GCC_VERSION | cut -d . -f 1`
+  MinorVersion=`echo $GCC_VERSION | cut -d . -f 2`
+  GCC_ARCH_PREFIX=
+  NOTSUPPORTED=0
+
+  case $MajorVersion in
+    4)
+      case $MinorVersion in
+        9)
+          GCC_ARCH_PREFIX="GCC49_AARCH64_PREFIX"
+        ;;
+        *)
+          NOTSUPPORTED=1
+        ;;
+      esac
+    ;;
+    5)
+      case $MinorVersion in
+      4)
+        GCC_ARCH_PREFIX="GCC5_AARCH64_PREFIX"
+      ;;
+      *)
+        GCC_ARCH_PREFIX="GCC5_AARCH64_PREFIX"
+        echo "Warning: ${GCC_UTILITY} version ($MajorVersion.$MinorVersion) has not been tested, please use at own risk."
+      ;;
+      esac
+    ;;
+    *)
+      NOTSUPPORTED=1
+    ;;
+  esac
+
+  [ "$NOTSUPPORTED" -eq 1 ] && {
+      echo "Error: ${GCC_UTILITY} version ($MajorVersion.$MinorVersion) not supported ."
+      unset GCC_UTILITY GCC_VERSION MajorVersion MinorVersion
+  }
+
+  [ -n "$GCC_ARCH_PREFIX" ] && {
+    export GCC_ARCH_PREFIX="$GCC_ARCH_PREFIX"
+    export "$GCC_ARCH_PREFIX=$ARM64_PREFIX"
+  }
+
+  unset ARCH
+else
+    echo "Error: ${GCC_UTILITY} not found. Please check PATH variable."
+    unset GCC_UTILITY GCC_VERSION MajorVersion MinorVersion
+fi
+
+export PACKAGES_PATH=$PWD/../../../edk2-platforms
diff --git a/Platform/NXP/Readme.md b/Platform/NXP/Readme.md
new file mode 100644
index 0000000..a11b90c
--- /dev/null
+++ b/Platform/NXP/Readme.md
@@ -0,0 +1,15 @@
+Support for all NXP boards is available in this directory.
+
+# How to build
+
+build script source environment file Env.cshrc
+
+user need to run only build command.
+
+1. Build desired board
+   ./build.sh <board-name> <build-candidate> <clean> (optional)
+
+   board-name      : LS1043 / LS1046 / LS2088
+   build-candidate : DEBUG / RELEASE
+
+Currently, support for LS1043 is provided.
diff --git a/Platform/NXP/build.sh b/Platform/NXP/build.sh
new file mode 100755
index 0000000..e465ebf
--- /dev/null
+++ b/Platform/NXP/build.sh
@@ -0,0 +1,103 @@
+#!/bin/bash
+
+# UEFI build script for NXP LS SoCs
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution.  The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+# source environment file
+source Env.cshrc
+
+# Global Defaults
+ARCH=AARCH64
+TARGET_TOOLS=`echo $GCC_ARCH_PREFIX | cut -d _ -f 1`
+BASE_DIR=../../..
+
+[ -z "$TARGET_TOOLS" ] && {
+  echo "TARGET_TOOLS not found. Please run \"source Env.cshrc\" ."
+  exit 1
+}
+
+print_usage_banner()
+{
+    echo ""
+    echo "This shell script expects:"
+    echo "    Arg 1 (mandatory): Board Type (can be LS1043 / LS1046 / LS2088)."
+    echo "    Arg 2 (mandatory): Build candidate (can be RELEASE or DEBUG). By
+              default we build the RELEASE candidate."
+    echo "    Arg 3 (optional): clean - To do a 'make clean' operation."
+}
+
+# Check for total num of input arguments
+if [[ "$#" -gt 3 ]]; then
+  echo "Illegal number of parameters"
+  print_usage_banner
+  exit
+fi
+
+# Check for third parameter to be clean only
+if [[ "$3" && $3 != "clean" ]]; then
+  echo "Error ! Either clean or emplty"
+  print_usage_banner
+  exit
+fi
+
+# Check for input arguments
+if [[ $1 == "" || $2 == "" ]]; then
+  echo "Error !"
+  print_usage_banner
+  exit
+fi
+
+# Check for input arguments
+if [[ $1 != "LS1043" && $1 != "LS1046" && $1 != "LS2088" ]]; then
+  echo "Error ! Incorrect Board Type specified."
+  print_usage_banner
+  exit
+fi
+
+# Check for input arguments
+if [[ $2 != "RELEASE" ]]; then
+  if [[ $2 != "DEBUG" ]]; then
+    echo "Error ! Incorrect build target specified."
+    print_usage_banner
+    exit
+  fi
+fi
+
+PKG="aRdbPkg"
+
+echo ".........................................."
+echo "Welcome to $1$PKG UEFI Build environment"
+echo ".........................................."
+
+if [[ $3 == "clean" ]]; then
+  echo "Cleaning up the build directory '$BASE_DIR/Build/$1$PKG/'.."
+  rm -rf $BASE_DIR/Build/$1$PKG/*
+  exit
+fi
+
+# Clean-up
+set -e
+shopt -s nocasematch
+
+#
+# Setup workspace now
+#
+echo Initializing workspace
+cd $BASE_DIR
+
+# Use the BaseTools in edk2
+export EDK_TOOLS_PATH=`pwd`/BaseTools
+source edksetup.sh BaseTools
+
+
+build -p "$WORKSPACE/edk2-platforms/Platform/NXP/$1$PKG/$1$PKG.dsc" -a $ARCH -t $TARGET_TOOLS -b $2
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 25+ messages in thread

* Re: [PATCH edk2-platforms] [PATCH v3 0/9] Platform/NXP
  2017-11-27 10:51 [PATCH edk2-platforms] [PATCH v3 0/9] Platform/NXP Meenakshi Aggarwal
                   ` (8 preceding siblings ...)
  2017-11-27 10:51 ` [PATCH edk2-platforms] [PATCH v3 9/9] Build : Add build script and environment script Meenakshi Aggarwal
@ 2017-11-27 12:05 ` Leif Lindholm
  9 siblings, 0 replies; 25+ messages in thread
From: Leif Lindholm @ 2017-11-27 12:05 UTC (permalink / raw)
  To: Meenakshi Aggarwal
  Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi

On Mon, Nov 27, 2017 at 04:21:48PM +0530, Meenakshi Aggarwal wrote:
> v3:
> Added patch-prefix

I only meant you could apply this in future.
However, this new posting has ended up with ([PATCH ...][PATCH...]),
which is not ideal. There is no need to edit the patch subject for
each version - just specify (for a v3)
git format-patch --subject-prefix="PATCH edk2-platforms" -v3

If there is a need for a v4, or for future submissions, please also
look into
https://github.com/tianocore/tianocore.github.io/wiki/Laszlo's-unkempt-git-guide-for-edk2-contributors-and-maintainers#contributor-workflow
for how to configure your cloned git repository to generate summaries
and diffs that are easier to review.

> v2:
> 1. Incorporated styling comments
> 2. Removed/Rewrite function referred from linux
> 3. Created DS1307 Library under Silicon/Maxim and make it i2c driver based.
> 4. Created i2c driver
> 
> Meenakshi Aggarwal (9):
>   Platform/NXP: Add support for Big Endian Mmio APIs
>   Platform/NXP : Add support for Watchdog driver
>   SocLib : Add support for initialization of peripherals
>   Platform/NXP : Add support for DUART library
>   Platform/NXP: Add support for I2c driver
>   Silicon/Maxim : Add support for DS1307 RTC library
>   Platform/NXP: Add support for ArmPlatformLib
>   Compilation : Add the fdf, dsc and dec files.
>   Build : Add build script and environment script
> 
>  Platform/NXP/Drivers/I2cDxe/I2cDxe.c               | 728 +++++++++++++++++++++
>  Platform/NXP/Drivers/I2cDxe/I2cDxe.h               |  64 ++
>  Platform/NXP/Drivers/I2cDxe/I2cDxe.inf             |  57 ++
>  Platform/NXP/Drivers/WatchDog/WatchDog.c           | 421 ++++++++++++
>  Platform/NXP/Drivers/WatchDog/WatchDog.h           |  37 ++
>  Platform/NXP/Drivers/WatchDog/WatchDogDxe.inf      |  47 ++
>  Platform/NXP/Env.cshrc                             |  77 +++
>  Platform/NXP/Include/Bitops.h                      | 179 +++++
>  Platform/NXP/Include/Library/BeIoLib.h             | 332 ++++++++++
>  Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec       |  29 +
>  Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc       |  77 +++
>  Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf       | 281 ++++++++
>  .../Library/PlatformLib/ArmPlatformLib.c           | 105 +++
>  .../Library/PlatformLib/ArmPlatformLib.inf         |  70 ++
>  .../Library/PlatformLib/NxpQoriqLsHelper.S         |  38 ++
>  .../Library/PlatformLib/NxpQoriqLsMem.c            | 184 ++++++

In particular these ..., meaning reviewers need to start guessing
which files are affected.

Best Regards,

Leif

>  Platform/NXP/Library/BeIoLib/BeIoLib.c             | 400 +++++++++++
>  Platform/NXP/Library/BeIoLib/BeIoLib.inf           |  31 +
>  Platform/NXP/Library/DUartPortLib/DUart.h          | 128 ++++
>  Platform/NXP/Library/DUartPortLib/DUartPortLib.c   | 331 ++++++++++
>  Platform/NXP/Library/DUartPortLib/DUartPortLib.inf |  39 ++
>  Platform/NXP/NxpQoriqLs.dec                        | 248 +++++++
>  Platform/NXP/NxpQoriqLs.dsc                        | 453 +++++++++++++
>  Platform/NXP/Readme.md                             |  15 +
>  Platform/NXP/build.sh                              | 103 +++
>  Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h     |  59 ++
>  Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c  | 327 +++++++++
>  .../Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec    |  26 +
>  .../Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf    |  45 ++
>  Silicon/NXP/Chassis/Chassis.c                      | 413 ++++++++++++
>  Silicon/NXP/Chassis/Chassis.h                      | 144 ++++
>  Silicon/NXP/Chassis/Chassis2/Chassis2.dec          |  19 +
>  Silicon/NXP/Chassis/Chassis2/SerDes.h              |  69 ++
>  Silicon/NXP/Chassis/Chassis2/Soc.c                 | 145 ++++
>  Silicon/NXP/Chassis/Chassis2/Soc.h                 | 376 +++++++++++
>  Silicon/NXP/Chassis/LS1043aSocLib.inf              |  47 ++
>  Silicon/NXP/Chassis/SerDes.c                       | 254 +++++++
>  Silicon/NXP/LS1043A/Include/SocSerDes.h            |  55 ++
>  Silicon/NXP/LS1043A/LS1043A.dec                    |  22 +
>  Silicon/NXP/LS1043A/LS1043A.dsc                    |  82 +++
>  40 files changed, 6557 insertions(+)
>  create mode 100644 Platform/NXP/Drivers/I2cDxe/I2cDxe.c
>  create mode 100644 Platform/NXP/Drivers/I2cDxe/I2cDxe.h
>  create mode 100644 Platform/NXP/Drivers/I2cDxe/I2cDxe.inf
>  create mode 100644 Platform/NXP/Drivers/WatchDog/WatchDog.c
>  create mode 100644 Platform/NXP/Drivers/WatchDog/WatchDog.h
>  create mode 100644 Platform/NXP/Drivers/WatchDog/WatchDogDxe.inf
>  create mode 100755 Platform/NXP/Env.cshrc
>  create mode 100644 Platform/NXP/Include/Bitops.h
>  create mode 100644 Platform/NXP/Include/Library/BeIoLib.h
>  create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec
>  create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
>  create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
>  create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
>  create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
>  create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
>  create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
>  create mode 100644 Platform/NXP/Library/BeIoLib/BeIoLib.c
>  create mode 100644 Platform/NXP/Library/BeIoLib/BeIoLib.inf
>  create mode 100644 Platform/NXP/Library/DUartPortLib/DUart.h
>  create mode 100644 Platform/NXP/Library/DUartPortLib/DUartPortLib.c
>  create mode 100644 Platform/NXP/Library/DUartPortLib/DUartPortLib.inf
>  create mode 100644 Platform/NXP/NxpQoriqLs.dec
>  create mode 100644 Platform/NXP/NxpQoriqLs.dsc
>  create mode 100644 Platform/NXP/Readme.md
>  create mode 100755 Platform/NXP/build.sh
>  create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h
>  create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
>  create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
>  create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
>  create mode 100644 Silicon/NXP/Chassis/Chassis.c
>  create mode 100644 Silicon/NXP/Chassis/Chassis.h
>  create mode 100644 Silicon/NXP/Chassis/Chassis2/Chassis2.dec
>  create mode 100644 Silicon/NXP/Chassis/Chassis2/SerDes.h
>  create mode 100644 Silicon/NXP/Chassis/Chassis2/Soc.c
>  create mode 100644 Silicon/NXP/Chassis/Chassis2/Soc.h
>  create mode 100644 Silicon/NXP/Chassis/LS1043aSocLib.inf
>  create mode 100644 Silicon/NXP/Chassis/SerDes.c
>  create mode 100644 Silicon/NXP/LS1043A/Include/SocSerDes.h
>  create mode 100644 Silicon/NXP/LS1043A/LS1043A.dec
>  create mode 100644 Silicon/NXP/LS1043A/LS1043A.dsc
> 
> v1:
>  Following patches will add support of NXP SoCs in edk2-platforms.
>  
>  Our directory structure will be:
>  
>  edk2-platforms/
>  |-- Platform
>  |   |-- NXP
>  |   |   |-- build.sh
>  |   |   |-- Drivers
>  |   |   |-- Env.cshrc
>  |   |   |-- Include
>  |   |   |   `-- Library
>  |   |   |   `-- Drivers
>  |   |   |-- Library
>  |   |   |-- LS1043aRdbPkg
>  |   |   |   |-- Drivers
>  |   |   |   |-- Include
>  |   |   |   |   `-- Library
>  |   |   |   |   `-- Drivers
>  |   |   |   |-- Library
>  |   |   |   |-- LS1043aRdbPkg.dec
>  |   |   |   |-- LS1043aRdbPkg.dsc
>  |   |   |   `-- LS1043aRdbPkg.fdf
>  |   |   |-- NxpQoriqLs.dec
>  |   |   |-- NxpQoriqLs.dsc
>  |   |   `-- Readme.md
>  `-- Silicon
>      |-- NXP
>          |-- Chassis
>          |   |-- Chassis2
>          `-- LS1043A
>              |-- Include
>              |-- LS1043A.dec
>              `-- LS1043A.dsc
>              
>  In Silicon/NXP, we are keeping our SoC specific information and remaining code will be kept in Platform/NXP.
>  
>  Platform/NXP/LS1043aRdbPkg will host .dsc and .fdf files to support compilation for LS1043A RDB board.
>  
>  In next series of patches we will be adding support for LS2088 and LS1046 board.
>  
>  
>  Looking forward for your kind support in upstreaming our board in edk2-platforms.
>  
>  
>  Meenakshi Aggarwal (10):
>    Platform/NXP: Library to provide helper functions.
>    Platform/NXP: Add support for system reset library
>    Platform/NXP: Add support for Big Endian Mmio APIs
>    Platform/NXP : Add support for Watchdog driver
>    Platform/NXP : Add support for DUART library
>    Platform/NXP: Add support for I2c operations library
>    Platform/NXP : Add support for DS1307 RTC library
>    Platform/NXP: Add support for ArmPlatformLib
>    SocLib : Add support for initialization of peripherals
>    Compilation : Add the fdf, dsc and dec files.
>  
>   Platform/NXP/Drivers/WatchDog/WatchDog.c           | 386 +++++++++++++++
>   Platform/NXP/Drivers/WatchDog/WatchDog.h           |  37 ++
>   Platform/NXP/Drivers/WatchDog/WatchDogDxe.inf      |  47 ++
>   Platform/NXP/Env.cshrc                             |  75 +++
>   Platform/NXP/Include/Bitops.h                      | 179 +++++++
>   Platform/NXP/Include/Library/BeIoLib.h             | 332 +++++++++++++
>   Platform/NXP/Include/Library/I2c.h                 | 125 +++++
>   Platform/NXP/Include/Library/Utils.h               | 137 +++++
>   Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec       |  29 ++
>   Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc       |  74 +++
>   Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf       | 279 +++++++++++
>   .../Library/PlatformLib/ArmPlatformLib.c           | 105 ++++
>   .../Library/PlatformLib/ArmPlatformLib.inf         |  70 +++
>   .../Library/PlatformLib/NxpQoriqLsHelper.S         |  38 ++
>   .../Library/PlatformLib/NxpQoriqLsMem.c            | 184 +++++++
>   Platform/NXP/Library/BeIoLib/BeIoLib.c             | 400 +++++++++++++++
>   Platform/NXP/Library/BeIoLib/BeIoLib.inf           |  31 ++
>   Platform/NXP/Library/DUartPortLib/DUart.h          | 128 +++++
>   Platform/NXP/Library/DUartPortLib/DUartPortLib.c   | 334 +++++++++++++
>   Platform/NXP/Library/DUartPortLib/DUartPortLib.inf |  39 ++
>   Platform/NXP/Library/Ds1307RtcLib/Ds1307Rtc.h      |  40 ++
>   Platform/NXP/Library/Ds1307RtcLib/Ds1307RtcLib.c   | 226 +++++++++
>   Platform/NXP/Library/Ds1307RtcLib/Ds1307RtcLib.inf |  40 ++
>   Platform/NXP/Library/I2cLib/I2cLib.c               | 549 +++++++++++++++++++++
>   Platform/NXP/Library/I2cLib/I2cLib.h               | 109 ++++
>   Platform/NXP/Library/I2cLib/I2cLib.inf             |  43 ++
>   .../NXP/Library/ResetSystemLib/ResetSystemLib.c    |  96 ++++
>   .../NXP/Library/ResetSystemLib/ResetSystemLib.inf  |  33 ++
>   Platform/NXP/Library/UtilsLib/Utils.c              |  97 ++++
>   Platform/NXP/Library/UtilsLib/Utils.inf            |  30 ++
>   Platform/NXP/NxpQoriqLs.dec                        | 257 ++++++++++
>   Platform/NXP/NxpQoriqLs.dsc                        | 453 +++++++++++++++++
>   Platform/NXP/Readme.md                             |  14 +
>   Platform/NXP/build.sh                              | 100 ++++
>   Silicon/NXP/Chassis/Chassis.c                      | 393 +++++++++++++++
>   Silicon/NXP/Chassis/Chassis.h                      | 123 +++++
>   Silicon/NXP/Chassis/Chassis2/Chassis2.dec          |  19 +
>   Silicon/NXP/Chassis/Chassis2/SerDes.h              |  82 +++
>   Silicon/NXP/Chassis/Chassis2/Soc.c                 | 146 ++++++
>   Silicon/NXP/Chassis/Chassis2/Soc.h                 | 376 ++++++++++++++
>   Silicon/NXP/Chassis/LS1043aSocLib.inf              |  48 ++
>   Silicon/NXP/Chassis/SerDes.c                       | 253 ++++++++++
>   Silicon/NXP/LS1043A/Include/SocSerDes.h            |  55 +++
>   Silicon/NXP/LS1043A/LS1043A.dec                    |  22 +
>   Silicon/NXP/LS1043A/LS1043A.dsc                    |  82 +++
>   45 files changed, 6715 insertions(+)
>   create mode 100644 Platform/NXP/Drivers/WatchDog/WatchDog.c
>   create mode 100644 Platform/NXP/Drivers/WatchDog/WatchDog.h
>   create mode 100644 Platform/NXP/Drivers/WatchDog/WatchDogDxe.inf
>   create mode 100644 Platform/NXP/Env.cshrc  create mode 100644 
>  Platform/NXP/Include/Bitops.h  create mode 100644 
>  Platform/NXP/Include/Library/BeIoLib.h
>   create mode 100644 Platform/NXP/Include/Library/I2c.h
>   create mode 100644 Platform/NXP/Include/Library/Utils.h
>   create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec
>   create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
>   create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
>   create mode 100644 
>  Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
>   create mode 100644 
>  Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
>   create mode 100644 
>  Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
>   create mode 100644 
>  Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
>   create mode 100644 Platform/NXP/Library/BeIoLib/BeIoLib.c
>   create mode 100644 Platform/NXP/Library/BeIoLib/BeIoLib.inf
>   create mode 100644 Platform/NXP/Library/DUartPortLib/DUart.h
>   create mode 100644 Platform/NXP/Library/DUartPortLib/DUartPortLib.c
>   create mode 100644 Platform/NXP/Library/DUartPortLib/DUartPortLib.inf
>   create mode 100644 Platform/NXP/Library/Ds1307RtcLib/Ds1307Rtc.h
>   create mode 100644 Platform/NXP/Library/Ds1307RtcLib/Ds1307RtcLib.c
>   create mode 100644 Platform/NXP/Library/Ds1307RtcLib/Ds1307RtcLib.inf
>   create mode 100644 Platform/NXP/Library/I2cLib/I2cLib.c
>   create mode 100644 Platform/NXP/Library/I2cLib/I2cLib.h
>   create mode 100644 Platform/NXP/Library/I2cLib/I2cLib.inf
>   create mode 100644 
>  Platform/NXP/Library/ResetSystemLib/ResetSystemLib.c
>   create mode 100644 
>  Platform/NXP/Library/ResetSystemLib/ResetSystemLib.inf
>   create mode 100644 Platform/NXP/Library/UtilsLib/Utils.c
>   create mode 100644 Platform/NXP/Library/UtilsLib/Utils.inf
>   create mode 100644 Platform/NXP/NxpQoriqLs.dec  create mode 100644 
>  Platform/NXP/NxpQoriqLs.dsc  create mode 100644 Platform/NXP/Readme.md  
>  create mode 100755 Platform/NXP/build.sh  create mode 100644 
>  Silicon/NXP/Chassis/Chassis.c  create mode 100644 
>  Silicon/NXP/Chassis/Chassis.h  create mode 100644 
>  Silicon/NXP/Chassis/Chassis2/Chassis2.dec
>   create mode 100644 Silicon/NXP/Chassis/Chassis2/SerDes.h
>   create mode 100644 Silicon/NXP/Chassis/Chassis2/Soc.c
>   create mode 100644 Silicon/NXP/Chassis/Chassis2/Soc.h
>   create mode 100644 Silicon/NXP/Chassis/LS1043aSocLib.inf
>   create mode 100644 Silicon/NXP/Chassis/SerDes.c  create mode 100644 
>  Silicon/NXP/LS1043A/Include/SocSerDes.h
>   create mode 100644 Silicon/NXP/LS1043A/LS1043A.dec  create mode 
>  100644 Silicon/NXP/LS1043A/LS1043A.dsc
> 
> -- 
> 1.9.1
> 


^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add support for Watchdog driver
  2017-11-27 10:51 ` [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add support for Watchdog driver Meenakshi Aggarwal
@ 2017-12-04 14:35   ` Leif Lindholm
  2017-12-04 15:23     ` Gao, Liming
  0 siblings, 1 reply; 25+ messages in thread
From: Leif Lindholm @ 2017-12-04 14:35 UTC (permalink / raw)
  To: michael.d.kinney, liming.gao
  Cc: Meenakshi Aggarwal, ard.biesheuvel, edk2-devel, udit.kumar,
	v.sethi

Mike, Liming, as MdePkg mainteiners - one question below:

On Mon, Nov 27, 2017 at 04:21:50PM +0530, Meenakshi Aggarwal wrote:
> diff --git a/Platform/NXP/Drivers/WatchDog/WatchDog.c b/Platform/NXP/Drivers/WatchDog/WatchDog.c
> new file mode 100644
> index 0000000..a9c70ef
> --- /dev/null
> +++ b/Platform/NXP/Drivers/WatchDog/WatchDog.c
> @@ -0,0 +1,421 @@

...

> +/**
> +  This function registers the handler NotifyFunction so it is called every time
> +  the watchdog timer expires.  It also passes the amount of time since the last
> +  handler call to the NotifyFunction.
> +  If NotifyFunction is not NULL and a handler is not already registered,
> +  then the new handler is registered and EFI_SUCCESS is returned.
> +  If NotifyFunction is NULL, and a handler is already registered,
> +  then that handler is unregistered.
> +  If an attempt is made to register a handler when a handler is already registered,
> +  then EFI_ALREADY_STARTED is returned.
> +  If an attempt is made to unregister a handler when a handler is not registered,
> +  then EFI_INVALID_PARAMETER is returned.
> +
> +  @param  This             The EFI_TIMER_ARCH_PROTOCOL instance.
> +  @param  NotifyFunction   The function to call when a timer interrupt fires. This
> +                           function executes at TPL_HIGH_LEVEL. The DXE Core will
> +                           register a handler for the timer interrupt, so it can know
> +                           how much time has passed. This information is used to
> +                           signal timer based events. NULL will unregister the handler.
> +
> +  @retval EFI_SUCCESS           The watchdog timer handler was registered.
> +  @retval EFI_ALREADY_STARTED   NotifyFunction is not NULL, and a handler is already
> +                                registered.
> +  @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not
> +                                previously registered.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +WdogRegisterHandler (
> +  IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL   *This,
> +  IN EFI_WATCHDOG_TIMER_NOTIFY          NotifyFunction
> +  )
> +{
> +  // ERROR: This function is not supported.
> +  // The hardware watchdog will reset the board
> +  return EFI_INVALID_PARAMETER;

Michael, Liming - what's your take on this?

Is EFI_WATCHDOG_TIMER_ARCH_PROTOCOL suitable for use with a pure-hw
watchdog such as this?

If so, what would be a suitable return code here?
EFI_INVALID_PARAMETER does not look ideal.

/
    Leif


^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add support for Watchdog driver
  2017-12-04 14:35   ` Leif Lindholm
@ 2017-12-04 15:23     ` Gao, Liming
  2017-12-05  5:07       ` Udit Kumar
  0 siblings, 1 reply; 25+ messages in thread
From: Gao, Liming @ 2017-12-04 15:23 UTC (permalink / raw)
  To: Leif Lindholm, Kinney, Michael D
  Cc: Meenakshi Aggarwal, ard.biesheuvel@linaro.org,
	edk2-devel@lists.01.org, udit.kumar@nxp.com, v.sethi@nxp.com

Leif:
  I suggest return EFI_UNSUPPORTED for this case. The protocol implementation could return its status besides spec defined status.

Thanks
Liming
> -----Original Message-----
> From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> Sent: Monday, December 4, 2017 10:36 PM
> To: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming <liming.gao@intel.com>
> Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; ard.biesheuvel@linaro.org; edk2-devel@lists.01.org;
> udit.kumar@nxp.com; v.sethi@nxp.com
> Subject: Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add support for Watchdog driver
> 
> Mike, Liming, as MdePkg mainteiners - one question below:
> 
> On Mon, Nov 27, 2017 at 04:21:50PM +0530, Meenakshi Aggarwal wrote:
> > diff --git a/Platform/NXP/Drivers/WatchDog/WatchDog.c b/Platform/NXP/Drivers/WatchDog/WatchDog.c
> > new file mode 100644
> > index 0000000..a9c70ef
> > --- /dev/null
> > +++ b/Platform/NXP/Drivers/WatchDog/WatchDog.c
> > @@ -0,0 +1,421 @@
> 
> ...
> 
> > +/**
> > +  This function registers the handler NotifyFunction so it is called every time
> > +  the watchdog timer expires.  It also passes the amount of time since the last
> > +  handler call to the NotifyFunction.
> > +  If NotifyFunction is not NULL and a handler is not already registered,
> > +  then the new handler is registered and EFI_SUCCESS is returned.
> > +  If NotifyFunction is NULL, and a handler is already registered,
> > +  then that handler is unregistered.
> > +  If an attempt is made to register a handler when a handler is already registered,
> > +  then EFI_ALREADY_STARTED is returned.
> > +  If an attempt is made to unregister a handler when a handler is not registered,
> > +  then EFI_INVALID_PARAMETER is returned.
> > +
> > +  @param  This             The EFI_TIMER_ARCH_PROTOCOL instance.
> > +  @param  NotifyFunction   The function to call when a timer interrupt fires. This
> > +                           function executes at TPL_HIGH_LEVEL. The DXE Core will
> > +                           register a handler for the timer interrupt, so it can know
> > +                           how much time has passed. This information is used to
> > +                           signal timer based events. NULL will unregister the handler.
> > +
> > +  @retval EFI_SUCCESS           The watchdog timer handler was registered.
> > +  @retval EFI_ALREADY_STARTED   NotifyFunction is not NULL, and a handler is already
> > +                                registered.
> > +  @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not
> > +                                previously registered.
> > +
> > +**/
> > +STATIC
> > +EFI_STATUS
> > +EFIAPI
> > +WdogRegisterHandler (
> > +  IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL   *This,
> > +  IN EFI_WATCHDOG_TIMER_NOTIFY          NotifyFunction
> > +  )
> > +{
> > +  // ERROR: This function is not supported.
> > +  // The hardware watchdog will reset the board
> > +  return EFI_INVALID_PARAMETER;
> 
> Michael, Liming - what's your take on this?
> 
> Is EFI_WATCHDOG_TIMER_ARCH_PROTOCOL suitable for use with a pure-hw
> watchdog such as this?
> 
> If so, what would be a suitable return code here?
> EFI_INVALID_PARAMETER does not look ideal.
> 
> /
>     Leif


^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add support for Watchdog driver
  2017-12-04 15:23     ` Gao, Liming
@ 2017-12-05  5:07       ` Udit Kumar
  2017-12-05 11:06         ` Leif Lindholm
  0 siblings, 1 reply; 25+ messages in thread
From: Udit Kumar @ 2017-12-05  5:07 UTC (permalink / raw)
  To: Gao, Liming, Leif Lindholm, Kinney, Michael D
  Cc: Meenakshi Aggarwal, ard.biesheuvel@linaro.org,
	edk2-devel@lists.01.org, Varun Sethi

>   I suggest return EFI_UNSUPPORTED for this case. The protocol implementation
> could return its status besides spec defined status.

Thanks to help me , how core will treat this error  
1/  Wdt not available 
2/ ignoring this error 
3/ core is not registering handler  
I guess 3 is valid, 

On side track, looks wdt is not used by core services then do we really need this 
as part of arch protocol ?

regards
Udit 

> -----Original Message-----
> From: Gao, Liming [mailto:liming.gao@intel.com]
> Sent: Monday, December 04, 2017 8:53 PM
> To: Leif Lindholm <leif.lindholm@linaro.org>; Kinney, Michael D
> <michael.d.kinney@intel.com>
> Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>;
> ard.biesheuvel@linaro.org; edk2-devel@lists.01.org; Udit Kumar
> <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>
> Subject: RE: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add support
> for Watchdog driver
> 
> Leif:
>   I suggest return EFI_UNSUPPORTED for this case. The protocol implementation
> could return its status besides spec defined status.
> 
> Thanks
> Liming
> > -----Original Message-----
> > From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> > Sent: Monday, December 4, 2017 10:36 PM
> > To: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming
> > <liming.gao@intel.com>
> > Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>;
> > ard.biesheuvel@linaro.org; edk2-devel@lists.01.org;
> > udit.kumar@nxp.com; v.sethi@nxp.com
> > Subject: Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add
> > support for Watchdog driver
> >
> > Mike, Liming, as MdePkg mainteiners - one question below:
> >
> > On Mon, Nov 27, 2017 at 04:21:50PM +0530, Meenakshi Aggarwal wrote:
> > > diff --git a/Platform/NXP/Drivers/WatchDog/WatchDog.c
> > > b/Platform/NXP/Drivers/WatchDog/WatchDog.c
> > > new file mode 100644
> > > index 0000000..a9c70ef
> > > --- /dev/null
> > > +++ b/Platform/NXP/Drivers/WatchDog/WatchDog.c
> > > @@ -0,0 +1,421 @@
> >
> > ...
> >
> > > +/**
> > > +  This function registers the handler NotifyFunction so it is
> > > +called every time
> > > +  the watchdog timer expires.  It also passes the amount of time
> > > +since the last
> > > +  handler call to the NotifyFunction.
> > > +  If NotifyFunction is not NULL and a handler is not already
> > > +registered,
> > > +  then the new handler is registered and EFI_SUCCESS is returned.
> > > +  If NotifyFunction is NULL, and a handler is already registered,
> > > +  then that handler is unregistered.
> > > +  If an attempt is made to register a handler when a handler is
> > > +already registered,
> > > +  then EFI_ALREADY_STARTED is returned.
> > > +  If an attempt is made to unregister a handler when a handler is
> > > +not registered,
> > > +  then EFI_INVALID_PARAMETER is returned.
> > > +
> > > +  @param  This             The EFI_TIMER_ARCH_PROTOCOL instance.
> > > +  @param  NotifyFunction   The function to call when a timer interrupt fires.
> This
> > > +                           function executes at TPL_HIGH_LEVEL. The DXE Core will
> > > +                           register a handler for the timer interrupt, so it can know
> > > +                           how much time has passed. This information is used to
> > > +                           signal timer based events. NULL will unregister the handler.
> > > +
> > > +  @retval EFI_SUCCESS           The watchdog timer handler was registered.
> > > +  @retval EFI_ALREADY_STARTED   NotifyFunction is not NULL, and a
> handler is already
> > > +                                registered.
> > > +  @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler
> was not
> > > +                                previously registered.
> > > +
> > > +**/
> > > +STATIC
> > > +EFI_STATUS
> > > +EFIAPI
> > > +WdogRegisterHandler (
> > > +  IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL   *This,
> > > +  IN EFI_WATCHDOG_TIMER_NOTIFY          NotifyFunction
> > > +  )
> > > +{
> > > +  // ERROR: This function is not supported.
> > > +  // The hardware watchdog will reset the board
> > > +  return EFI_INVALID_PARAMETER;
> >
> > Michael, Liming - what's your take on this?
> >
> > Is EFI_WATCHDOG_TIMER_ARCH_PROTOCOL suitable for use with a pure-hw
> > watchdog such as this?
> >
> > If so, what would be a suitable return code here?
> > EFI_INVALID_PARAMETER does not look ideal.
> >
> > /
> >     Leif


^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add support for Watchdog driver
  2017-12-05  5:07       ` Udit Kumar
@ 2017-12-05 11:06         ` Leif Lindholm
  2017-12-07  3:35           ` Meenakshi Aggarwal
  2017-12-07  7:11           ` Gao, Liming
  0 siblings, 2 replies; 25+ messages in thread
From: Leif Lindholm @ 2017-12-05 11:06 UTC (permalink / raw)
  To: Udit Kumar
  Cc: Gao, Liming, Kinney, Michael D, Meenakshi Aggarwal,
	ard.biesheuvel@linaro.org, edk2-devel@lists.01.org, Varun Sethi

On Tue, Dec 05, 2017 at 05:07:00AM +0000, Udit Kumar wrote:
> >   I suggest return EFI_UNSUPPORTED for this case. The protocol implementation
> > could return its status besides spec defined status.
> 
> Thanks to help me , how core will treat this error  
> 1/  Wdt not available 
> 2/ ignoring this error 
> 3/ core is not registering handler  
> I guess 3 is valid, 

Looking at Core/Dxe/Misc/SetWatchdogTimer.c:
  //
  // Attempt to set the timeout
  //
  Status = gWatchdogTimer->SetTimerPeriod (gWatchdogTimer,
  MultU64x32 (Timeout, WATCHDOG_TIMER_CALIBRATE_PER_SECOND));

  //
  // Check for errors
  //
  if (EFI_ERROR (Status)) {
    return EFI_DEVICE_ERROR;
  }

The SetWatchdogTimer() call would always return EFI_DEVICE_ERROR.

> On side track, looks wdt is not used by core services then do we
> really need this as part of arch protocol ?

Yes, that was ultimately what I was implying with my question
regarding whether this protocol is relevant for a watchdog that can
only ever reset the system on timeout.

The protocol looks to me to be designed to use a dedicated generic
timer as backing for a software watchdog.

Liming, Mike?

If that is the case, then I agree this driver should probably not
implement this protocol, but rather set up a timer event (or a
dedicated timer) to stroke the watchdog.

Regards,

Leif

> regards
> Udit 
> 
> > -----Original Message-----
> > From: Gao, Liming [mailto:liming.gao@intel.com]
> > Sent: Monday, December 04, 2017 8:53 PM
> > To: Leif Lindholm <leif.lindholm@linaro.org>; Kinney, Michael D
> > <michael.d.kinney@intel.com>
> > Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>;
> > ard.biesheuvel@linaro.org; edk2-devel@lists.01.org; Udit Kumar
> > <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>
> > Subject: RE: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add support
> > for Watchdog driver
> > 
> > Leif:
> >   I suggest return EFI_UNSUPPORTED for this case. The protocol implementation
> > could return its status besides spec defined status.
> > 
> > Thanks
> > Liming
> > > -----Original Message-----
> > > From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> > > Sent: Monday, December 4, 2017 10:36 PM
> > > To: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming
> > > <liming.gao@intel.com>
> > > Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>;
> > > ard.biesheuvel@linaro.org; edk2-devel@lists.01.org;
> > > udit.kumar@nxp.com; v.sethi@nxp.com
> > > Subject: Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add
> > > support for Watchdog driver
> > >
> > > Mike, Liming, as MdePkg mainteiners - one question below:
> > >
> > > On Mon, Nov 27, 2017 at 04:21:50PM +0530, Meenakshi Aggarwal wrote:
> > > > diff --git a/Platform/NXP/Drivers/WatchDog/WatchDog.c
> > > > b/Platform/NXP/Drivers/WatchDog/WatchDog.c
> > > > new file mode 100644
> > > > index 0000000..a9c70ef
> > > > --- /dev/null
> > > > +++ b/Platform/NXP/Drivers/WatchDog/WatchDog.c
> > > > @@ -0,0 +1,421 @@
> > >
> > > ...
> > >
> > > > +/**
> > > > +  This function registers the handler NotifyFunction so it is
> > > > +called every time
> > > > +  the watchdog timer expires.  It also passes the amount of time
> > > > +since the last
> > > > +  handler call to the NotifyFunction.
> > > > +  If NotifyFunction is not NULL and a handler is not already
> > > > +registered,
> > > > +  then the new handler is registered and EFI_SUCCESS is returned.
> > > > +  If NotifyFunction is NULL, and a handler is already registered,
> > > > +  then that handler is unregistered.
> > > > +  If an attempt is made to register a handler when a handler is
> > > > +already registered,
> > > > +  then EFI_ALREADY_STARTED is returned.
> > > > +  If an attempt is made to unregister a handler when a handler is
> > > > +not registered,
> > > > +  then EFI_INVALID_PARAMETER is returned.
> > > > +
> > > > +  @param  This             The EFI_TIMER_ARCH_PROTOCOL instance.
> > > > +  @param  NotifyFunction   The function to call when a timer interrupt fires.
> > This
> > > > +                           function executes at TPL_HIGH_LEVEL. The DXE Core will
> > > > +                           register a handler for the timer interrupt, so it can know
> > > > +                           how much time has passed. This information is used to
> > > > +                           signal timer based events. NULL will unregister the handler.
> > > > +
> > > > +  @retval EFI_SUCCESS           The watchdog timer handler was registered.
> > > > +  @retval EFI_ALREADY_STARTED   NotifyFunction is not NULL, and a
> > handler is already
> > > > +                                registered.
> > > > +  @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler
> > was not
> > > > +                                previously registered.
> > > > +
> > > > +**/
> > > > +STATIC
> > > > +EFI_STATUS
> > > > +EFIAPI
> > > > +WdogRegisterHandler (
> > > > +  IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL   *This,
> > > > +  IN EFI_WATCHDOG_TIMER_NOTIFY          NotifyFunction
> > > > +  )
> > > > +{
> > > > +  // ERROR: This function is not supported.
> > > > +  // The hardware watchdog will reset the board
> > > > +  return EFI_INVALID_PARAMETER;
> > >
> > > Michael, Liming - what's your take on this?
> > >
> > > Is EFI_WATCHDOG_TIMER_ARCH_PROTOCOL suitable for use with a pure-hw
> > > watchdog such as this?
> > >
> > > If so, what would be a suitable return code here?
> > > EFI_INVALID_PARAMETER does not look ideal.
> > >
> > > /
> > >     Leif


^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add support for Watchdog driver
  2017-12-05 11:06         ` Leif Lindholm
@ 2017-12-07  3:35           ` Meenakshi Aggarwal
  2017-12-07  7:11           ` Gao, Liming
  1 sibling, 0 replies; 25+ messages in thread
From: Meenakshi Aggarwal @ 2017-12-07  3:35 UTC (permalink / raw)
  To: Leif Lindholm, Kinney, Michael D, Gao, Liming
  Cc: ard.biesheuvel@linaro.org, edk2-devel@lists.01.org, Varun Sethi,
	Udit Kumar

Hi Liming, Mike,


Please share your inputs on this.


Thanks,
Meenakshi

> -----Original Message-----
> From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> Sent: Tuesday, December 05, 2017 4:36 PM
> To: Udit Kumar <udit.kumar@nxp.com>
> Cc: Gao, Liming <liming.gao@intel.com>; Kinney, Michael D
> <michael.d.kinney@intel.com>; Meenakshi Aggarwal
> <meenakshi.aggarwal@nxp.com>; ard.biesheuvel@linaro.org; edk2-
> devel@lists.01.org; Varun Sethi <V.Sethi@nxp.com>
> Subject: Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add
> support for Watchdog driver
> 
> On Tue, Dec 05, 2017 at 05:07:00AM +0000, Udit Kumar wrote:
> > >   I suggest return EFI_UNSUPPORTED for this case. The protocol
> implementation
> > > could return its status besides spec defined status.
> >
> > Thanks to help me , how core will treat this error
> > 1/  Wdt not available
> > 2/ ignoring this error
> > 3/ core is not registering handler
> > I guess 3 is valid,
> 
> Looking at Core/Dxe/Misc/SetWatchdogTimer.c:
>   //
>   // Attempt to set the timeout
>   //
>   Status = gWatchdogTimer->SetTimerPeriod (gWatchdogTimer,
>   MultU64x32 (Timeout, WATCHDOG_TIMER_CALIBRATE_PER_SECOND));
> 
>   //
>   // Check for errors
>   //
>   if (EFI_ERROR (Status)) {
>     return EFI_DEVICE_ERROR;
>   }
> 
> The SetWatchdogTimer() call would always return EFI_DEVICE_ERROR.
> 
> > On side track, looks wdt is not used by core services then do we
> > really need this as part of arch protocol ?
> 
> Yes, that was ultimately what I was implying with my question
> regarding whether this protocol is relevant for a watchdog that can
> only ever reset the system on timeout.
> 
> The protocol looks to me to be designed to use a dedicated generic
> timer as backing for a software watchdog.
> 
> Liming, Mike?
> 
> If that is the case, then I agree this driver should probably not
> implement this protocol, but rather set up a timer event (or a
> dedicated timer) to stroke the watchdog.
> 
> Regards,
> 
> Leif
> 
> > regards
> > Udit
> >
> > > -----Original Message-----
> > > From: Gao, Liming [mailto:liming.gao@intel.com]
> > > Sent: Monday, December 04, 2017 8:53 PM
> > > To: Leif Lindholm <leif.lindholm@linaro.org>; Kinney, Michael D
> > > <michael.d.kinney@intel.com>
> > > Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>;
> > > ard.biesheuvel@linaro.org; edk2-devel@lists.01.org; Udit Kumar
> > > <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>
> > > Subject: RE: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add
> support
> > > for Watchdog driver
> > >
> > > Leif:
> > >   I suggest return EFI_UNSUPPORTED for this case. The protocol
> implementation
> > > could return its status besides spec defined status.
> > >
> > > Thanks
> > > Liming
> > > > -----Original Message-----
> > > > From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> > > > Sent: Monday, December 4, 2017 10:36 PM
> > > > To: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming
> > > > <liming.gao@intel.com>
> > > > Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>;
> > > > ard.biesheuvel@linaro.org; edk2-devel@lists.01.org;
> > > > udit.kumar@nxp.com; v.sethi@nxp.com
> > > > Subject: Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP :
> Add
> > > > support for Watchdog driver
> > > >
> > > > Mike, Liming, as MdePkg mainteiners - one question below:
> > > >
> > > > On Mon, Nov 27, 2017 at 04:21:50PM +0530, Meenakshi Aggarwal
> wrote:
> > > > > diff --git a/Platform/NXP/Drivers/WatchDog/WatchDog.c
> > > > > b/Platform/NXP/Drivers/WatchDog/WatchDog.c
> > > > > new file mode 100644
> > > > > index 0000000..a9c70ef
> > > > > --- /dev/null
> > > > > +++ b/Platform/NXP/Drivers/WatchDog/WatchDog.c
> > > > > @@ -0,0 +1,421 @@
> > > >
> > > > ...
> > > >
> > > > > +/**
> > > > > +  This function registers the handler NotifyFunction so it is
> > > > > +called every time
> > > > > +  the watchdog timer expires.  It also passes the amount of time
> > > > > +since the last
> > > > > +  handler call to the NotifyFunction.
> > > > > +  If NotifyFunction is not NULL and a handler is not already
> > > > > +registered,
> > > > > +  then the new handler is registered and EFI_SUCCESS is returned.
> > > > > +  If NotifyFunction is NULL, and a handler is already registered,
> > > > > +  then that handler is unregistered.
> > > > > +  If an attempt is made to register a handler when a handler is
> > > > > +already registered,
> > > > > +  then EFI_ALREADY_STARTED is returned.
> > > > > +  If an attempt is made to unregister a handler when a handler is
> > > > > +not registered,
> > > > > +  then EFI_INVALID_PARAMETER is returned.
> > > > > +
> > > > > +  @param  This             The EFI_TIMER_ARCH_PROTOCOL instance.
> > > > > +  @param  NotifyFunction   The function to call when a timer
> interrupt fires.
> > > This
> > > > > +                           function executes at TPL_HIGH_LEVEL. The DXE Core
> will
> > > > > +                           register a handler for the timer interrupt, so it can
> know
> > > > > +                           how much time has passed. This information is used to
> > > > > +                           signal timer based events. NULL will unregister the
> handler.
> > > > > +
> > > > > +  @retval EFI_SUCCESS           The watchdog timer handler was
> registered.
> > > > > +  @retval EFI_ALREADY_STARTED   NotifyFunction is not NULL, and a
> > > handler is already
> > > > > +                                registered.
> > > > > +  @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a
> handler
> > > was not
> > > > > +                                previously registered.
> > > > > +
> > > > > +**/
> > > > > +STATIC
> > > > > +EFI_STATUS
> > > > > +EFIAPI
> > > > > +WdogRegisterHandler (
> > > > > +  IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL   *This,
> > > > > +  IN EFI_WATCHDOG_TIMER_NOTIFY          NotifyFunction
> > > > > +  )
> > > > > +{
> > > > > +  // ERROR: This function is not supported.
> > > > > +  // The hardware watchdog will reset the board
> > > > > +  return EFI_INVALID_PARAMETER;
> > > >
> > > > Michael, Liming - what's your take on this?
> > > >
> > > > Is EFI_WATCHDOG_TIMER_ARCH_PROTOCOL suitable for use with a
> pure-hw
> > > > watchdog such as this?
> > > >
> > > > If so, what would be a suitable return code here?
> > > > EFI_INVALID_PARAMETER does not look ideal.
> > > >
> > > > /
> > > >     Leif


^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add support for Watchdog driver
  2017-12-05 11:06         ` Leif Lindholm
  2017-12-07  3:35           ` Meenakshi Aggarwal
@ 2017-12-07  7:11           ` Gao, Liming
  2017-12-07 11:03             ` Leif Lindholm
  2017-12-07 11:15             ` Udit Kumar
  1 sibling, 2 replies; 25+ messages in thread
From: Gao, Liming @ 2017-12-07  7:11 UTC (permalink / raw)
  To: Leif Lindholm, Udit Kumar
  Cc: Kinney, Michael D, Meenakshi Aggarwal, ard.biesheuvel@linaro.org,
	edk2-devel@lists.01.org, Varun Sethi

Leif:
  I don't see the core driver uses WatchdogTimer->RegisterHandler(). When it returns unsupported, it means the additional handler can't be registered. DxeCore uses WatchdogTimer->SetTimerPeriod(). This service is implemented in your driver. 

  Watchdog protocol is defined in PI spec. Spec describes that this protocol provides the services required to implement the Boot Service SetWatchdogTimer(). It provides a service to set the amount of time to wait before firing the watchdog timer, and it also provides a service to register a handler that is invoked when the watchdog timer fires. This protocol can implement the watchdog timer by using the event and timer Boot Services, or it can make use of custom hardware. If no handler has been registered, or the registered handler returns, then the system will be reset by calling the Runtime Service ResetSystem(). So, this protocol is required.

Thanks
Liming
>-----Original Message-----
>From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
>Sent: Tuesday, December 05, 2017 7:06 PM
>To: Udit Kumar <udit.kumar@nxp.com>
>Cc: Gao, Liming <liming.gao@intel.com>; Kinney, Michael D
><michael.d.kinney@intel.com>; Meenakshi Aggarwal
><meenakshi.aggarwal@nxp.com>; ard.biesheuvel@linaro.org; edk2-
>devel@lists.01.org; Varun Sethi <V.Sethi@nxp.com>
>Subject: Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add
>support for Watchdog driver
>
>On Tue, Dec 05, 2017 at 05:07:00AM +0000, Udit Kumar wrote:
>> >   I suggest return EFI_UNSUPPORTED for this case. The protocol
>implementation
>> > could return its status besides spec defined status.
>>
>> Thanks to help me , how core will treat this error
>> 1/  Wdt not available
>> 2/ ignoring this error
>> 3/ core is not registering handler
>> I guess 3 is valid,
>
>Looking at Core/Dxe/Misc/SetWatchdogTimer.c:
>  //
>  // Attempt to set the timeout
>  //
>  Status = gWatchdogTimer->SetTimerPeriod (gWatchdogTimer,
>  MultU64x32 (Timeout, WATCHDOG_TIMER_CALIBRATE_PER_SECOND));
>
>  //
>  // Check for errors
>  //
>  if (EFI_ERROR (Status)) {
>    return EFI_DEVICE_ERROR;
>  }
>
>The SetWatchdogTimer() call would always return EFI_DEVICE_ERROR.
>
>> On side track, looks wdt is not used by core services then do we
>> really need this as part of arch protocol ?
>
>Yes, that was ultimately what I was implying with my question
>regarding whether this protocol is relevant for a watchdog that can
>only ever reset the system on timeout.
>
>The protocol looks to me to be designed to use a dedicated generic
>timer as backing for a software watchdog.
>
>Liming, Mike?
>
>If that is the case, then I agree this driver should probably not
>implement this protocol, but rather set up a timer event (or a
>dedicated timer) to stroke the watchdog.
>
>Regards,
>
>Leif
>
>> regards
>> Udit
>>
>> > -----Original Message-----
>> > From: Gao, Liming [mailto:liming.gao@intel.com]
>> > Sent: Monday, December 04, 2017 8:53 PM
>> > To: Leif Lindholm <leif.lindholm@linaro.org>; Kinney, Michael D
>> > <michael.d.kinney@intel.com>
>> > Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>;
>> > ard.biesheuvel@linaro.org; edk2-devel@lists.01.org; Udit Kumar
>> > <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>
>> > Subject: RE: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add
>support
>> > for Watchdog driver
>> >
>> > Leif:
>> >   I suggest return EFI_UNSUPPORTED for this case. The protocol
>implementation
>> > could return its status besides spec defined status.
>> >
>> > Thanks
>> > Liming
>> > > -----Original Message-----
>> > > From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
>> > > Sent: Monday, December 4, 2017 10:36 PM
>> > > To: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming
>> > > <liming.gao@intel.com>
>> > > Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>;
>> > > ard.biesheuvel@linaro.org; edk2-devel@lists.01.org;
>> > > udit.kumar@nxp.com; v.sethi@nxp.com
>> > > Subject: Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add
>> > > support for Watchdog driver
>> > >
>> > > Mike, Liming, as MdePkg mainteiners - one question below:
>> > >
>> > > On Mon, Nov 27, 2017 at 04:21:50PM +0530, Meenakshi Aggarwal wrote:
>> > > > diff --git a/Platform/NXP/Drivers/WatchDog/WatchDog.c
>> > > > b/Platform/NXP/Drivers/WatchDog/WatchDog.c
>> > > > new file mode 100644
>> > > > index 0000000..a9c70ef
>> > > > --- /dev/null
>> > > > +++ b/Platform/NXP/Drivers/WatchDog/WatchDog.c
>> > > > @@ -0,0 +1,421 @@
>> > >
>> > > ...
>> > >
>> > > > +/**
>> > > > +  This function registers the handler NotifyFunction so it is
>> > > > +called every time
>> > > > +  the watchdog timer expires.  It also passes the amount of time
>> > > > +since the last
>> > > > +  handler call to the NotifyFunction.
>> > > > +  If NotifyFunction is not NULL and a handler is not already
>> > > > +registered,
>> > > > +  then the new handler is registered and EFI_SUCCESS is returned.
>> > > > +  If NotifyFunction is NULL, and a handler is already registered,
>> > > > +  then that handler is unregistered.
>> > > > +  If an attempt is made to register a handler when a handler is
>> > > > +already registered,
>> > > > +  then EFI_ALREADY_STARTED is returned.
>> > > > +  If an attempt is made to unregister a handler when a handler is
>> > > > +not registered,
>> > > > +  then EFI_INVALID_PARAMETER is returned.
>> > > > +
>> > > > +  @param  This             The EFI_TIMER_ARCH_PROTOCOL instance.
>> > > > +  @param  NotifyFunction   The function to call when a timer interrupt
>fires.
>> > This
>> > > > +                           function executes at TPL_HIGH_LEVEL. The DXE Core
>will
>> > > > +                           register a handler for the timer interrupt, so it can know
>> > > > +                           how much time has passed. This information is used to
>> > > > +                           signal timer based events. NULL will unregister the
>handler.
>> > > > +
>> > > > +  @retval EFI_SUCCESS           The watchdog timer handler was
>registered.
>> > > > +  @retval EFI_ALREADY_STARTED   NotifyFunction is not NULL, and a
>> > handler is already
>> > > > +                                registered.
>> > > > +  @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a
>handler
>> > was not
>> > > > +                                previously registered.
>> > > > +
>> > > > +**/
>> > > > +STATIC
>> > > > +EFI_STATUS
>> > > > +EFIAPI
>> > > > +WdogRegisterHandler (
>> > > > +  IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL   *This,
>> > > > +  IN EFI_WATCHDOG_TIMER_NOTIFY          NotifyFunction
>> > > > +  )
>> > > > +{
>> > > > +  // ERROR: This function is not supported.
>> > > > +  // The hardware watchdog will reset the board
>> > > > +  return EFI_INVALID_PARAMETER;
>> > >
>> > > Michael, Liming - what's your take on this?
>> > >
>> > > Is EFI_WATCHDOG_TIMER_ARCH_PROTOCOL suitable for use with a
>pure-hw
>> > > watchdog such as this?
>> > >
>> > > If so, what would be a suitable return code here?
>> > > EFI_INVALID_PARAMETER does not look ideal.
>> > >
>> > > /
>> > >     Leif


^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add support for Watchdog driver
  2017-12-07  7:11           ` Gao, Liming
@ 2017-12-07 11:03             ` Leif Lindholm
  2017-12-07 14:54               ` Gao, Liming
  2017-12-07 11:15             ` Udit Kumar
  1 sibling, 1 reply; 25+ messages in thread
From: Leif Lindholm @ 2017-12-07 11:03 UTC (permalink / raw)
  To: Gao, Liming
  Cc: Udit Kumar, Kinney, Michael D, Meenakshi Aggarwal,
	ard.biesheuvel@linaro.org, edk2-devel@lists.01.org, Varun Sethi

Hi Liming,

On Thu, Dec 07, 2017 at 07:11:38AM +0000, Gao, Liming wrote:
> Leif:
>   I don't see the core driver uses
>   WatchdogTimer->RegisterHandler(). When it returns unsupported, it
>   means the additional handler can't be registered. DxeCore uses
>   WatchdogTimer->SetTimerPeriod(). This service is implemented in
>   your driver.
> 
>   Watchdog protocol is defined in PI spec. Spec describes that this
>   protocol provides the services required to implement the Boot
>   Service SetWatchdogTimer(). It provides a service to set the
>   amount of time to wait before firing the watchdog timer, and it
>   also provides a service to register a handler that is invoked when
>   the watchdog timer fires. This protocol can implement the watchdog
>   timer by using the event and timer Boot Services, or it can make
>   use of custom hardware. If no handler has been registered, or the
>   registered handler returns, then the system will be reset by
>   calling the Runtime Service ResetSystem(). So, this protocol is
>   required.

I am not disputing that the protocol is not required. I am suggesting
that this hardware watchdog _cannot_ be used to register a handler.

If this hardware watchdog does not get updated in time, that causes an
immediate hardware reset of the processor.

Because of this, I believe EFI_WATCHDOG_TIMER_ARCH_PROTOCOL is not the
appropriate way to make use of it.

Please let me know whether you agree.

Regards,

Leif

> Thanks
> Liming
> >-----Original Message-----
> >From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> >Sent: Tuesday, December 05, 2017 7:06 PM
> >To: Udit Kumar <udit.kumar@nxp.com>
> >Cc: Gao, Liming <liming.gao@intel.com>; Kinney, Michael D
> ><michael.d.kinney@intel.com>; Meenakshi Aggarwal
> ><meenakshi.aggarwal@nxp.com>; ard.biesheuvel@linaro.org; edk2-
> >devel@lists.01.org; Varun Sethi <V.Sethi@nxp.com>
> >Subject: Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add
> >support for Watchdog driver
> >
> >On Tue, Dec 05, 2017 at 05:07:00AM +0000, Udit Kumar wrote:
> >> >   I suggest return EFI_UNSUPPORTED for this case. The protocol
> >implementation
> >> > could return its status besides spec defined status.
> >>
> >> Thanks to help me , how core will treat this error
> >> 1/  Wdt not available
> >> 2/ ignoring this error
> >> 3/ core is not registering handler
> >> I guess 3 is valid,
> >
> >Looking at Core/Dxe/Misc/SetWatchdogTimer.c:
> >  //
> >  // Attempt to set the timeout
> >  //
> >  Status = gWatchdogTimer->SetTimerPeriod (gWatchdogTimer,
> >  MultU64x32 (Timeout, WATCHDOG_TIMER_CALIBRATE_PER_SECOND));
> >
> >  //
> >  // Check for errors
> >  //
> >  if (EFI_ERROR (Status)) {
> >    return EFI_DEVICE_ERROR;
> >  }
> >
> >The SetWatchdogTimer() call would always return EFI_DEVICE_ERROR.
> >
> >> On side track, looks wdt is not used by core services then do we
> >> really need this as part of arch protocol ?
> >
> >Yes, that was ultimately what I was implying with my question
> >regarding whether this protocol is relevant for a watchdog that can
> >only ever reset the system on timeout.
> >
> >The protocol looks to me to be designed to use a dedicated generic
> >timer as backing for a software watchdog.
> >
> >Liming, Mike?
> >
> >If that is the case, then I agree this driver should probably not
> >implement this protocol, but rather set up a timer event (or a
> >dedicated timer) to stroke the watchdog.
> >
> >Regards,
> >
> >Leif
> >
> >> regards
> >> Udit
> >>
> >> > -----Original Message-----
> >> > From: Gao, Liming [mailto:liming.gao@intel.com]
> >> > Sent: Monday, December 04, 2017 8:53 PM
> >> > To: Leif Lindholm <leif.lindholm@linaro.org>; Kinney, Michael D
> >> > <michael.d.kinney@intel.com>
> >> > Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>;
> >> > ard.biesheuvel@linaro.org; edk2-devel@lists.01.org; Udit Kumar
> >> > <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>
> >> > Subject: RE: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add
> >support
> >> > for Watchdog driver
> >> >
> >> > Leif:
> >> >   I suggest return EFI_UNSUPPORTED for this case. The protocol
> >implementation
> >> > could return its status besides spec defined status.
> >> >
> >> > Thanks
> >> > Liming
> >> > > -----Original Message-----
> >> > > From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> >> > > Sent: Monday, December 4, 2017 10:36 PM
> >> > > To: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming
> >> > > <liming.gao@intel.com>
> >> > > Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>;
> >> > > ard.biesheuvel@linaro.org; edk2-devel@lists.01.org;
> >> > > udit.kumar@nxp.com; v.sethi@nxp.com
> >> > > Subject: Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add
> >> > > support for Watchdog driver
> >> > >
> >> > > Mike, Liming, as MdePkg mainteiners - one question below:
> >> > >
> >> > > On Mon, Nov 27, 2017 at 04:21:50PM +0530, Meenakshi Aggarwal wrote:
> >> > > > diff --git a/Platform/NXP/Drivers/WatchDog/WatchDog.c
> >> > > > b/Platform/NXP/Drivers/WatchDog/WatchDog.c
> >> > > > new file mode 100644
> >> > > > index 0000000..a9c70ef
> >> > > > --- /dev/null
> >> > > > +++ b/Platform/NXP/Drivers/WatchDog/WatchDog.c
> >> > > > @@ -0,0 +1,421 @@
> >> > >
> >> > > ...
> >> > >
> >> > > > +/**
> >> > > > +  This function registers the handler NotifyFunction so it is
> >> > > > +called every time
> >> > > > +  the watchdog timer expires.  It also passes the amount of time
> >> > > > +since the last
> >> > > > +  handler call to the NotifyFunction.
> >> > > > +  If NotifyFunction is not NULL and a handler is not already
> >> > > > +registered,
> >> > > > +  then the new handler is registered and EFI_SUCCESS is returned.
> >> > > > +  If NotifyFunction is NULL, and a handler is already registered,
> >> > > > +  then that handler is unregistered.
> >> > > > +  If an attempt is made to register a handler when a handler is
> >> > > > +already registered,
> >> > > > +  then EFI_ALREADY_STARTED is returned.
> >> > > > +  If an attempt is made to unregister a handler when a handler is
> >> > > > +not registered,
> >> > > > +  then EFI_INVALID_PARAMETER is returned.
> >> > > > +
> >> > > > +  @param  This             The EFI_TIMER_ARCH_PROTOCOL instance.
> >> > > > +  @param  NotifyFunction   The function to call when a timer interrupt
> >fires.
> >> > This
> >> > > > +                           function executes at TPL_HIGH_LEVEL. The DXE Core
> >will
> >> > > > +                           register a handler for the timer interrupt, so it can know
> >> > > > +                           how much time has passed. This information is used to
> >> > > > +                           signal timer based events. NULL will unregister the
> >handler.
> >> > > > +
> >> > > > +  @retval EFI_SUCCESS           The watchdog timer handler was
> >registered.
> >> > > > +  @retval EFI_ALREADY_STARTED   NotifyFunction is not NULL, and a
> >> > handler is already
> >> > > > +                                registered.
> >> > > > +  @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a
> >handler
> >> > was not
> >> > > > +                                previously registered.
> >> > > > +
> >> > > > +**/
> >> > > > +STATIC
> >> > > > +EFI_STATUS
> >> > > > +EFIAPI
> >> > > > +WdogRegisterHandler (
> >> > > > +  IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL   *This,
> >> > > > +  IN EFI_WATCHDOG_TIMER_NOTIFY          NotifyFunction
> >> > > > +  )
> >> > > > +{
> >> > > > +  // ERROR: This function is not supported.
> >> > > > +  // The hardware watchdog will reset the board
> >> > > > +  return EFI_INVALID_PARAMETER;
> >> > >
> >> > > Michael, Liming - what's your take on this?
> >> > >
> >> > > Is EFI_WATCHDOG_TIMER_ARCH_PROTOCOL suitable for use with a
> >pure-hw
> >> > > watchdog such as this?
> >> > >
> >> > > If so, what would be a suitable return code here?
> >> > > EFI_INVALID_PARAMETER does not look ideal.
> >> > >
> >> > > /
> >> > >     Leif


^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add support for Watchdog driver
  2017-12-07  7:11           ` Gao, Liming
  2017-12-07 11:03             ` Leif Lindholm
@ 2017-12-07 11:15             ` Udit Kumar
  2017-12-07 14:51               ` Gao, Liming
  1 sibling, 1 reply; 25+ messages in thread
From: Udit Kumar @ 2017-12-07 11:15 UTC (permalink / raw)
  To: Gao, Liming, Leif Lindholm
  Cc: Kinney, Michael D, Meenakshi Aggarwal, ard.biesheuvel@linaro.org,
	edk2-devel@lists.01.org, Varun Sethi

Hi Liming, 

> DxeCore uses WatchdogTimer->SetTimerPeriod(). This service is implemented in
> your driver.

Callers of SetTimerPeriod are ignoring error reported. 
Is they assume this call will be perfect or they are ok in case some error on watchdog service. 

 
Regards
Udit 

> -----Original Message-----
> From: Gao, Liming [mailto:liming.gao@intel.com]
> Sent: Thursday, December 07, 2017 12:42 PM
> To: Leif Lindholm <leif.lindholm@linaro.org>; Udit Kumar
> <udit.kumar@nxp.com>
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Meenakshi Aggarwal
> <meenakshi.aggarwal@nxp.com>; ard.biesheuvel@linaro.org; edk2-
> devel@lists.01.org; Varun Sethi <V.Sethi@nxp.com>
> Subject: RE: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add support
> for Watchdog driver
> 
> Leif:
>   I don't see the core driver uses WatchdogTimer->RegisterHandler(). When it
> returns unsupported, it means the additional handler can't be registered.
> DxeCore uses WatchdogTimer->SetTimerPeriod(). This service is implemented in
> your driver.
> 
>   Watchdog protocol is defined in PI spec. Spec describes that this protocol
> provides the services required to implement the Boot Service
> SetWatchdogTimer(). It provides a service to set the amount of time to wait
> before firing the watchdog timer, and it also provides a service to register a
> handler that is invoked when the watchdog timer fires. This protocol can
> implement the watchdog timer by using the event and timer Boot Services, or it
> can make use of custom hardware. If no handler has been registered, or the
> registered handler returns, then the system will be reset by calling the Runtime
> Service ResetSystem(). So, this protocol is required.
> 
> Thanks
> Liming
> >-----Original Message-----
> >From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> >Sent: Tuesday, December 05, 2017 7:06 PM
> >To: Udit Kumar <udit.kumar@nxp.com>
> >Cc: Gao, Liming <liming.gao@intel.com>; Kinney, Michael D
> ><michael.d.kinney@intel.com>; Meenakshi Aggarwal
> ><meenakshi.aggarwal@nxp.com>; ard.biesheuvel@linaro.org; edk2-
> >devel@lists.01.org; Varun Sethi <V.Sethi@nxp.com>
> >Subject: Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add
> >support for Watchdog driver
> >
> >On Tue, Dec 05, 2017 at 05:07:00AM +0000, Udit Kumar wrote:
> >> >   I suggest return EFI_UNSUPPORTED for this case. The protocol
> >implementation
> >> > could return its status besides spec defined status.
> >>
> >> Thanks to help me , how core will treat this error 1/  Wdt not
> >> available 2/ ignoring this error 3/ core is not registering handler I
> >> guess 3 is valid,
> >
> >Looking at Core/Dxe/Misc/SetWatchdogTimer.c:
> >  //
> >  // Attempt to set the timeout
> >  //
> >  Status = gWatchdogTimer->SetTimerPeriod (gWatchdogTimer,
> >  MultU64x32 (Timeout, WATCHDOG_TIMER_CALIBRATE_PER_SECOND));
> >
> >  //
> >  // Check for errors
> >  //
> >  if (EFI_ERROR (Status)) {
> >    return EFI_DEVICE_ERROR;
> >  }
> >
> >The SetWatchdogTimer() call would always return EFI_DEVICE_ERROR.
> >
> >> On side track, looks wdt is not used by core services then do we
> >> really need this as part of arch protocol ?
> >
> >Yes, that was ultimately what I was implying with my question regarding
> >whether this protocol is relevant for a watchdog that can only ever
> >reset the system on timeout.
> >
> >The protocol looks to me to be designed to use a dedicated generic
> >timer as backing for a software watchdog.
> >
> >Liming, Mike?
> >
> >If that is the case, then I agree this driver should probably not
> >implement this protocol, but rather set up a timer event (or a
> >dedicated timer) to stroke the watchdog.
> >
> >Regards,
> >
> >Leif
> >
> >> regards
> >> Udit
> >>
> >> > -----Original Message-----
> >> > From: Gao, Liming [mailto:liming.gao@intel.com]
> >> > Sent: Monday, December 04, 2017 8:53 PM
> >> > To: Leif Lindholm <leif.lindholm@linaro.org>; Kinney, Michael D
> >> > <michael.d.kinney@intel.com>
> >> > Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>;
> >> > ard.biesheuvel@linaro.org; edk2-devel@lists.01.org; Udit Kumar
> >> > <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>
> >> > Subject: RE: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP :
> >> > Add
> >support
> >> > for Watchdog driver
> >> >
> >> > Leif:
> >> >   I suggest return EFI_UNSUPPORTED for this case. The protocol
> >implementation
> >> > could return its status besides spec defined status.
> >> >
> >> > Thanks
> >> > Liming
> >> > > -----Original Message-----
> >> > > From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> >> > > Sent: Monday, December 4, 2017 10:36 PM
> >> > > To: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming
> >> > > <liming.gao@intel.com>
> >> > > Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>;
> >> > > ard.biesheuvel@linaro.org; edk2-devel@lists.01.org;
> >> > > udit.kumar@nxp.com; v.sethi@nxp.com
> >> > > Subject: Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP :
> >> > > Add support for Watchdog driver
> >> > >
> >> > > Mike, Liming, as MdePkg mainteiners - one question below:
> >> > >
> >> > > On Mon, Nov 27, 2017 at 04:21:50PM +0530, Meenakshi Aggarwal wrote:
> >> > > > diff --git a/Platform/NXP/Drivers/WatchDog/WatchDog.c
> >> > > > b/Platform/NXP/Drivers/WatchDog/WatchDog.c
> >> > > > new file mode 100644
> >> > > > index 0000000..a9c70ef
> >> > > > --- /dev/null
> >> > > > +++ b/Platform/NXP/Drivers/WatchDog/WatchDog.c
> >> > > > @@ -0,0 +1,421 @@
> >> > >
> >> > > ...
> >> > >
> >> > > > +/**
> >> > > > +  This function registers the handler NotifyFunction so it is
> >> > > > +called every time
> >> > > > +  the watchdog timer expires.  It also passes the amount of
> >> > > > +time since the last
> >> > > > +  handler call to the NotifyFunction.
> >> > > > +  If NotifyFunction is not NULL and a handler is not already
> >> > > > +registered,
> >> > > > +  then the new handler is registered and EFI_SUCCESS is returned.
> >> > > > +  If NotifyFunction is NULL, and a handler is already
> >> > > > +registered,
> >> > > > +  then that handler is unregistered.
> >> > > > +  If an attempt is made to register a handler when a handler
> >> > > > +is already registered,
> >> > > > +  then EFI_ALREADY_STARTED is returned.
> >> > > > +  If an attempt is made to unregister a handler when a handler
> >> > > > +is not registered,
> >> > > > +  then EFI_INVALID_PARAMETER is returned.
> >> > > > +
> >> > > > +  @param  This             The EFI_TIMER_ARCH_PROTOCOL instance.
> >> > > > +  @param  NotifyFunction   The function to call when a timer interrupt
> >fires.
> >> > This
> >> > > > +                           function executes at
> >> > > > + TPL_HIGH_LEVEL. The DXE Core
> >will
> >> > > > +                           register a handler for the timer interrupt, so it can know
> >> > > > +                           how much time has passed. This information is used to
> >> > > > +                           signal timer based events. NULL
> >> > > > + will unregister the
> >handler.
> >> > > > +
> >> > > > +  @retval EFI_SUCCESS           The watchdog timer handler was
> >registered.
> >> > > > +  @retval EFI_ALREADY_STARTED   NotifyFunction is not NULL, and a
> >> > handler is already
> >> > > > +                                registered.
> >> > > > +  @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a
> >handler
> >> > was not
> >> > > > +                                previously registered.
> >> > > > +
> >> > > > +**/
> >> > > > +STATIC
> >> > > > +EFI_STATUS
> >> > > > +EFIAPI
> >> > > > +WdogRegisterHandler (
> >> > > > +  IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL   *This,
> >> > > > +  IN EFI_WATCHDOG_TIMER_NOTIFY          NotifyFunction
> >> > > > +  )
> >> > > > +{
> >> > > > +  // ERROR: This function is not supported.
> >> > > > +  // The hardware watchdog will reset the board
> >> > > > +  return EFI_INVALID_PARAMETER;
> >> > >
> >> > > Michael, Liming - what's your take on this?
> >> > >
> >> > > Is EFI_WATCHDOG_TIMER_ARCH_PROTOCOL suitable for use with a
> >pure-hw
> >> > > watchdog such as this?
> >> > >
> >> > > If so, what would be a suitable return code here?
> >> > > EFI_INVALID_PARAMETER does not look ideal.
> >> > >
> >> > > /
> >> > >     Leif


^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add support for Watchdog driver
  2017-12-07 11:15             ` Udit Kumar
@ 2017-12-07 14:51               ` Gao, Liming
  0 siblings, 0 replies; 25+ messages in thread
From: Gao, Liming @ 2017-12-07 14:51 UTC (permalink / raw)
  To: Udit Kumar, Leif Lindholm
  Cc: Kinney, Michael D, Meenakshi Aggarwal, ard.biesheuvel@linaro.org,
	edk2-devel@lists.01.org, Varun Sethi

CoreSetWatchdogTimer() allows the error status for watchdog service.

> -----Original Message-----
> From: Udit Kumar [mailto:udit.kumar@nxp.com]
> Sent: Thursday, December 7, 2017 7:15 PM
> To: Gao, Liming <liming.gao@intel.com>; Leif Lindholm <leif.lindholm@linaro.org>
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>;
> ard.biesheuvel@linaro.org; edk2-devel@lists.01.org; Varun Sethi <V.Sethi@nxp.com>
> Subject: RE: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add support for Watchdog driver
> 
> Hi Liming,
> 
> > DxeCore uses WatchdogTimer->SetTimerPeriod(). This service is implemented in
> > your driver.
> 
> Callers of SetTimerPeriod are ignoring error reported.
> Is they assume this call will be perfect or they are ok in case some error on watchdog service.
> 
> 
> Regards
> Udit
> 
> > -----Original Message-----
> > From: Gao, Liming [mailto:liming.gao@intel.com]
> > Sent: Thursday, December 07, 2017 12:42 PM
> > To: Leif Lindholm <leif.lindholm@linaro.org>; Udit Kumar
> > <udit.kumar@nxp.com>
> > Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Meenakshi Aggarwal
> > <meenakshi.aggarwal@nxp.com>; ard.biesheuvel@linaro.org; edk2-
> > devel@lists.01.org; Varun Sethi <V.Sethi@nxp.com>
> > Subject: RE: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add support
> > for Watchdog driver
> >
> > Leif:
> >   I don't see the core driver uses WatchdogTimer->RegisterHandler(). When it
> > returns unsupported, it means the additional handler can't be registered.
> > DxeCore uses WatchdogTimer->SetTimerPeriod(). This service is implemented in
> > your driver.
> >
> >   Watchdog protocol is defined in PI spec. Spec describes that this protocol
> > provides the services required to implement the Boot Service
> > SetWatchdogTimer(). It provides a service to set the amount of time to wait
> > before firing the watchdog timer, and it also provides a service to register a
> > handler that is invoked when the watchdog timer fires. This protocol can
> > implement the watchdog timer by using the event and timer Boot Services, or it
> > can make use of custom hardware. If no handler has been registered, or the
> > registered handler returns, then the system will be reset by calling the Runtime
> > Service ResetSystem(). So, this protocol is required.
> >
> > Thanks
> > Liming
> > >-----Original Message-----
> > >From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> > >Sent: Tuesday, December 05, 2017 7:06 PM
> > >To: Udit Kumar <udit.kumar@nxp.com>
> > >Cc: Gao, Liming <liming.gao@intel.com>; Kinney, Michael D
> > ><michael.d.kinney@intel.com>; Meenakshi Aggarwal
> > ><meenakshi.aggarwal@nxp.com>; ard.biesheuvel@linaro.org; edk2-
> > >devel@lists.01.org; Varun Sethi <V.Sethi@nxp.com>
> > >Subject: Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add
> > >support for Watchdog driver
> > >
> > >On Tue, Dec 05, 2017 at 05:07:00AM +0000, Udit Kumar wrote:
> > >> >   I suggest return EFI_UNSUPPORTED for this case. The protocol
> > >implementation
> > >> > could return its status besides spec defined status.
> > >>
> > >> Thanks to help me , how core will treat this error 1/  Wdt not
> > >> available 2/ ignoring this error 3/ core is not registering handler I
> > >> guess 3 is valid,
> > >
> > >Looking at Core/Dxe/Misc/SetWatchdogTimer.c:
> > >  //
> > >  // Attempt to set the timeout
> > >  //
> > >  Status = gWatchdogTimer->SetTimerPeriod (gWatchdogTimer,
> > >  MultU64x32 (Timeout, WATCHDOG_TIMER_CALIBRATE_PER_SECOND));
> > >
> > >  //
> > >  // Check for errors
> > >  //
> > >  if (EFI_ERROR (Status)) {
> > >    return EFI_DEVICE_ERROR;
> > >  }
> > >
> > >The SetWatchdogTimer() call would always return EFI_DEVICE_ERROR.
> > >
> > >> On side track, looks wdt is not used by core services then do we
> > >> really need this as part of arch protocol ?
> > >
> > >Yes, that was ultimately what I was implying with my question regarding
> > >whether this protocol is relevant for a watchdog that can only ever
> > >reset the system on timeout.
> > >
> > >The protocol looks to me to be designed to use a dedicated generic
> > >timer as backing for a software watchdog.
> > >
> > >Liming, Mike?
> > >
> > >If that is the case, then I agree this driver should probably not
> > >implement this protocol, but rather set up a timer event (or a
> > >dedicated timer) to stroke the watchdog.
> > >
> > >Regards,
> > >
> > >Leif
> > >
> > >> regards
> > >> Udit
> > >>
> > >> > -----Original Message-----
> > >> > From: Gao, Liming [mailto:liming.gao@intel.com]
> > >> > Sent: Monday, December 04, 2017 8:53 PM
> > >> > To: Leif Lindholm <leif.lindholm@linaro.org>; Kinney, Michael D
> > >> > <michael.d.kinney@intel.com>
> > >> > Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>;
> > >> > ard.biesheuvel@linaro.org; edk2-devel@lists.01.org; Udit Kumar
> > >> > <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>
> > >> > Subject: RE: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP :
> > >> > Add
> > >support
> > >> > for Watchdog driver
> > >> >
> > >> > Leif:
> > >> >   I suggest return EFI_UNSUPPORTED for this case. The protocol
> > >implementation
> > >> > could return its status besides spec defined status.
> > >> >
> > >> > Thanks
> > >> > Liming
> > >> > > -----Original Message-----
> > >> > > From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> > >> > > Sent: Monday, December 4, 2017 10:36 PM
> > >> > > To: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming
> > >> > > <liming.gao@intel.com>
> > >> > > Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>;
> > >> > > ard.biesheuvel@linaro.org; edk2-devel@lists.01.org;
> > >> > > udit.kumar@nxp.com; v.sethi@nxp.com
> > >> > > Subject: Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP :
> > >> > > Add support for Watchdog driver
> > >> > >
> > >> > > Mike, Liming, as MdePkg mainteiners - one question below:
> > >> > >
> > >> > > On Mon, Nov 27, 2017 at 04:21:50PM +0530, Meenakshi Aggarwal wrote:
> > >> > > > diff --git a/Platform/NXP/Drivers/WatchDog/WatchDog.c
> > >> > > > b/Platform/NXP/Drivers/WatchDog/WatchDog.c
> > >> > > > new file mode 100644
> > >> > > > index 0000000..a9c70ef
> > >> > > > --- /dev/null
> > >> > > > +++ b/Platform/NXP/Drivers/WatchDog/WatchDog.c
> > >> > > > @@ -0,0 +1,421 @@
> > >> > >
> > >> > > ...
> > >> > >
> > >> > > > +/**
> > >> > > > +  This function registers the handler NotifyFunction so it is
> > >> > > > +called every time
> > >> > > > +  the watchdog timer expires.  It also passes the amount of
> > >> > > > +time since the last
> > >> > > > +  handler call to the NotifyFunction.
> > >> > > > +  If NotifyFunction is not NULL and a handler is not already
> > >> > > > +registered,
> > >> > > > +  then the new handler is registered and EFI_SUCCESS is returned.
> > >> > > > +  If NotifyFunction is NULL, and a handler is already
> > >> > > > +registered,
> > >> > > > +  then that handler is unregistered.
> > >> > > > +  If an attempt is made to register a handler when a handler
> > >> > > > +is already registered,
> > >> > > > +  then EFI_ALREADY_STARTED is returned.
> > >> > > > +  If an attempt is made to unregister a handler when a handler
> > >> > > > +is not registered,
> > >> > > > +  then EFI_INVALID_PARAMETER is returned.
> > >> > > > +
> > >> > > > +  @param  This             The EFI_TIMER_ARCH_PROTOCOL instance.
> > >> > > > +  @param  NotifyFunction   The function to call when a timer interrupt
> > >fires.
> > >> > This
> > >> > > > +                           function executes at
> > >> > > > + TPL_HIGH_LEVEL. The DXE Core
> > >will
> > >> > > > +                           register a handler for the timer interrupt, so it can know
> > >> > > > +                           how much time has passed. This information is used to
> > >> > > > +                           signal timer based events. NULL
> > >> > > > + will unregister the
> > >handler.
> > >> > > > +
> > >> > > > +  @retval EFI_SUCCESS           The watchdog timer handler was
> > >registered.
> > >> > > > +  @retval EFI_ALREADY_STARTED   NotifyFunction is not NULL, and a
> > >> > handler is already
> > >> > > > +                                registered.
> > >> > > > +  @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a
> > >handler
> > >> > was not
> > >> > > > +                                previously registered.
> > >> > > > +
> > >> > > > +**/
> > >> > > > +STATIC
> > >> > > > +EFI_STATUS
> > >> > > > +EFIAPI
> > >> > > > +WdogRegisterHandler (
> > >> > > > +  IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL   *This,
> > >> > > > +  IN EFI_WATCHDOG_TIMER_NOTIFY          NotifyFunction
> > >> > > > +  )
> > >> > > > +{
> > >> > > > +  // ERROR: This function is not supported.
> > >> > > > +  // The hardware watchdog will reset the board
> > >> > > > +  return EFI_INVALID_PARAMETER;
> > >> > >
> > >> > > Michael, Liming - what's your take on this?
> > >> > >
> > >> > > Is EFI_WATCHDOG_TIMER_ARCH_PROTOCOL suitable for use with a
> > >pure-hw
> > >> > > watchdog such as this?
> > >> > >
> > >> > > If so, what would be a suitable return code here?
> > >> > > EFI_INVALID_PARAMETER does not look ideal.
> > >> > >
> > >> > > /
> > >> > >     Leif


^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add support for Watchdog driver
  2017-12-07 11:03             ` Leif Lindholm
@ 2017-12-07 14:54               ` Gao, Liming
  2017-12-07 15:34                 ` Leif Lindholm
  0 siblings, 1 reply; 25+ messages in thread
From: Gao, Liming @ 2017-12-07 14:54 UTC (permalink / raw)
  To: Leif Lindholm
  Cc: Udit Kumar, Kinney, Michael D, Meenakshi Aggarwal,
	ard.biesheuvel@linaro.org, edk2-devel@lists.01.org, Varun Sethi

Leif:
  I don't review the whole patch serial. Could you point your usage case on watch dog timer protocol?

Thanks
Liming
> -----Original Message-----
> From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> Sent: Thursday, December 7, 2017 7:04 PM
> To: Gao, Liming <liming.gao@intel.com>
> Cc: Udit Kumar <udit.kumar@nxp.com>; Kinney, Michael D <michael.d.kinney@intel.com>; Meenakshi Aggarwal
> <meenakshi.aggarwal@nxp.com>; ard.biesheuvel@linaro.org; edk2-devel@lists.01.org; Varun Sethi <V.Sethi@nxp.com>
> Subject: Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add support for Watchdog driver
> 
> Hi Liming,
> 
> On Thu, Dec 07, 2017 at 07:11:38AM +0000, Gao, Liming wrote:
> > Leif:
> >   I don't see the core driver uses
> >   WatchdogTimer->RegisterHandler(). When it returns unsupported, it
> >   means the additional handler can't be registered. DxeCore uses
> >   WatchdogTimer->SetTimerPeriod(). This service is implemented in
> >   your driver.
> >
> >   Watchdog protocol is defined in PI spec. Spec describes that this
> >   protocol provides the services required to implement the Boot
> >   Service SetWatchdogTimer(). It provides a service to set the
> >   amount of time to wait before firing the watchdog timer, and it
> >   also provides a service to register a handler that is invoked when
> >   the watchdog timer fires. This protocol can implement the watchdog
> >   timer by using the event and timer Boot Services, or it can make
> >   use of custom hardware. If no handler has been registered, or the
> >   registered handler returns, then the system will be reset by
> >   calling the Runtime Service ResetSystem(). So, this protocol is
> >   required.
> 
> I am not disputing that the protocol is not required. I am suggesting
> that this hardware watchdog _cannot_ be used to register a handler.
> 
> If this hardware watchdog does not get updated in time, that causes an
> immediate hardware reset of the processor.
> 
> Because of this, I believe EFI_WATCHDOG_TIMER_ARCH_PROTOCOL is not the
> appropriate way to make use of it.
> 
> Please let me know whether you agree.
> 
> Regards,
> 
> Leif
> 
> > Thanks
> > Liming
> > >-----Original Message-----
> > >From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> > >Sent: Tuesday, December 05, 2017 7:06 PM
> > >To: Udit Kumar <udit.kumar@nxp.com>
> > >Cc: Gao, Liming <liming.gao@intel.com>; Kinney, Michael D
> > ><michael.d.kinney@intel.com>; Meenakshi Aggarwal
> > ><meenakshi.aggarwal@nxp.com>; ard.biesheuvel@linaro.org; edk2-
> > >devel@lists.01.org; Varun Sethi <V.Sethi@nxp.com>
> > >Subject: Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add
> > >support for Watchdog driver
> > >
> > >On Tue, Dec 05, 2017 at 05:07:00AM +0000, Udit Kumar wrote:
> > >> >   I suggest return EFI_UNSUPPORTED for this case. The protocol
> > >implementation
> > >> > could return its status besides spec defined status.
> > >>
> > >> Thanks to help me , how core will treat this error
> > >> 1/  Wdt not available
> > >> 2/ ignoring this error
> > >> 3/ core is not registering handler
> > >> I guess 3 is valid,
> > >
> > >Looking at Core/Dxe/Misc/SetWatchdogTimer.c:
> > >  //
> > >  // Attempt to set the timeout
> > >  //
> > >  Status = gWatchdogTimer->SetTimerPeriod (gWatchdogTimer,
> > >  MultU64x32 (Timeout, WATCHDOG_TIMER_CALIBRATE_PER_SECOND));
> > >
> > >  //
> > >  // Check for errors
> > >  //
> > >  if (EFI_ERROR (Status)) {
> > >    return EFI_DEVICE_ERROR;
> > >  }
> > >
> > >The SetWatchdogTimer() call would always return EFI_DEVICE_ERROR.
> > >
> > >> On side track, looks wdt is not used by core services then do we
> > >> really need this as part of arch protocol ?
> > >
> > >Yes, that was ultimately what I was implying with my question
> > >regarding whether this protocol is relevant for a watchdog that can
> > >only ever reset the system on timeout.
> > >
> > >The protocol looks to me to be designed to use a dedicated generic
> > >timer as backing for a software watchdog.
> > >
> > >Liming, Mike?
> > >
> > >If that is the case, then I agree this driver should probably not
> > >implement this protocol, but rather set up a timer event (or a
> > >dedicated timer) to stroke the watchdog.
> > >
> > >Regards,
> > >
> > >Leif
> > >
> > >> regards
> > >> Udit
> > >>
> > >> > -----Original Message-----
> > >> > From: Gao, Liming [mailto:liming.gao@intel.com]
> > >> > Sent: Monday, December 04, 2017 8:53 PM
> > >> > To: Leif Lindholm <leif.lindholm@linaro.org>; Kinney, Michael D
> > >> > <michael.d.kinney@intel.com>
> > >> > Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>;
> > >> > ard.biesheuvel@linaro.org; edk2-devel@lists.01.org; Udit Kumar
> > >> > <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>
> > >> > Subject: RE: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add
> > >support
> > >> > for Watchdog driver
> > >> >
> > >> > Leif:
> > >> >   I suggest return EFI_UNSUPPORTED for this case. The protocol
> > >implementation
> > >> > could return its status besides spec defined status.
> > >> >
> > >> > Thanks
> > >> > Liming
> > >> > > -----Original Message-----
> > >> > > From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> > >> > > Sent: Monday, December 4, 2017 10:36 PM
> > >> > > To: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming
> > >> > > <liming.gao@intel.com>
> > >> > > Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>;
> > >> > > ard.biesheuvel@linaro.org; edk2-devel@lists.01.org;
> > >> > > udit.kumar@nxp.com; v.sethi@nxp.com
> > >> > > Subject: Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add
> > >> > > support for Watchdog driver
> > >> > >
> > >> > > Mike, Liming, as MdePkg mainteiners - one question below:
> > >> > >
> > >> > > On Mon, Nov 27, 2017 at 04:21:50PM +0530, Meenakshi Aggarwal wrote:
> > >> > > > diff --git a/Platform/NXP/Drivers/WatchDog/WatchDog.c
> > >> > > > b/Platform/NXP/Drivers/WatchDog/WatchDog.c
> > >> > > > new file mode 100644
> > >> > > > index 0000000..a9c70ef
> > >> > > > --- /dev/null
> > >> > > > +++ b/Platform/NXP/Drivers/WatchDog/WatchDog.c
> > >> > > > @@ -0,0 +1,421 @@
> > >> > >
> > >> > > ...
> > >> > >
> > >> > > > +/**
> > >> > > > +  This function registers the handler NotifyFunction so it is
> > >> > > > +called every time
> > >> > > > +  the watchdog timer expires.  It also passes the amount of time
> > >> > > > +since the last
> > >> > > > +  handler call to the NotifyFunction.
> > >> > > > +  If NotifyFunction is not NULL and a handler is not already
> > >> > > > +registered,
> > >> > > > +  then the new handler is registered and EFI_SUCCESS is returned.
> > >> > > > +  If NotifyFunction is NULL, and a handler is already registered,
> > >> > > > +  then that handler is unregistered.
> > >> > > > +  If an attempt is made to register a handler when a handler is
> > >> > > > +already registered,
> > >> > > > +  then EFI_ALREADY_STARTED is returned.
> > >> > > > +  If an attempt is made to unregister a handler when a handler is
> > >> > > > +not registered,
> > >> > > > +  then EFI_INVALID_PARAMETER is returned.
> > >> > > > +
> > >> > > > +  @param  This             The EFI_TIMER_ARCH_PROTOCOL instance.
> > >> > > > +  @param  NotifyFunction   The function to call when a timer interrupt
> > >fires.
> > >> > This
> > >> > > > +                           function executes at TPL_HIGH_LEVEL. The DXE Core
> > >will
> > >> > > > +                           register a handler for the timer interrupt, so it can know
> > >> > > > +                           how much time has passed. This information is used to
> > >> > > > +                           signal timer based events. NULL will unregister the
> > >handler.
> > >> > > > +
> > >> > > > +  @retval EFI_SUCCESS           The watchdog timer handler was
> > >registered.
> > >> > > > +  @retval EFI_ALREADY_STARTED   NotifyFunction is not NULL, and a
> > >> > handler is already
> > >> > > > +                                registered.
> > >> > > > +  @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a
> > >handler
> > >> > was not
> > >> > > > +                                previously registered.
> > >> > > > +
> > >> > > > +**/
> > >> > > > +STATIC
> > >> > > > +EFI_STATUS
> > >> > > > +EFIAPI
> > >> > > > +WdogRegisterHandler (
> > >> > > > +  IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL   *This,
> > >> > > > +  IN EFI_WATCHDOG_TIMER_NOTIFY          NotifyFunction
> > >> > > > +  )
> > >> > > > +{
> > >> > > > +  // ERROR: This function is not supported.
> > >> > > > +  // The hardware watchdog will reset the board
> > >> > > > +  return EFI_INVALID_PARAMETER;
> > >> > >
> > >> > > Michael, Liming - what's your take on this?
> > >> > >
> > >> > > Is EFI_WATCHDOG_TIMER_ARCH_PROTOCOL suitable for use with a
> > >pure-hw
> > >> > > watchdog such as this?
> > >> > >
> > >> > > If so, what would be a suitable return code here?
> > >> > > EFI_INVALID_PARAMETER does not look ideal.
> > >> > >
> > >> > > /
> > >> > >     Leif


^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add support for Watchdog driver
  2017-12-07 14:54               ` Gao, Liming
@ 2017-12-07 15:34                 ` Leif Lindholm
  2017-12-08  4:41                   ` Udit Kumar
  2017-12-10 13:30                   ` Gao, Liming
  0 siblings, 2 replies; 25+ messages in thread
From: Leif Lindholm @ 2017-12-07 15:34 UTC (permalink / raw)
  To: Gao, Liming
  Cc: Udit Kumar, Kinney, Michael D, Meenakshi Aggarwal,
	ard.biesheuvel@linaro.org, edk2-devel@lists.01.org, Varun Sethi

Liming,

https://www.mail-archive.com/edk2-devel@lists.01.org/msg32761.html
Search for WdogRegisterHandler.

This topic is entirely unrelated to any _usage_ of watchdog timer
protocol.

The topic is only whether it is reasonable to _implement_
EFI_WATCHDOG_TIMER_ARCH_PROTOCOL for a hardware watchdog that *cannot*
cause a callback to a handler function.
Because when the hardware watchdog times out, it triggers a hard
system reset, without any software interaction.

/
    Leif

On Thu, Dec 07, 2017 at 02:54:08PM +0000, Gao, Liming wrote:
> Leif:
>   I don't review the whole patch serial. Could you point your usage
>   case on watch dog timer protocol?
> 
> Thanks
> Liming
> > -----Original Message-----
> > From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> > Sent: Thursday, December 7, 2017 7:04 PM
> > To: Gao, Liming <liming.gao@intel.com>
> > Cc: Udit Kumar <udit.kumar@nxp.com>; Kinney, Michael D <michael.d.kinney@intel.com>; Meenakshi Aggarwal
> > <meenakshi.aggarwal@nxp.com>; ard.biesheuvel@linaro.org; edk2-devel@lists.01.org; Varun Sethi <V.Sethi@nxp.com>
> > Subject: Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add support for Watchdog driver
> > 
> > Hi Liming,
> > 
> > On Thu, Dec 07, 2017 at 07:11:38AM +0000, Gao, Liming wrote:
> > > Leif:
> > >   I don't see the core driver uses
> > >   WatchdogTimer->RegisterHandler(). When it returns unsupported, it
> > >   means the additional handler can't be registered. DxeCore uses
> > >   WatchdogTimer->SetTimerPeriod(). This service is implemented in
> > >   your driver.
> > >
> > >   Watchdog protocol is defined in PI spec. Spec describes that this
> > >   protocol provides the services required to implement the Boot
> > >   Service SetWatchdogTimer(). It provides a service to set the
> > >   amount of time to wait before firing the watchdog timer, and it
> > >   also provides a service to register a handler that is invoked when
> > >   the watchdog timer fires. This protocol can implement the watchdog
> > >   timer by using the event and timer Boot Services, or it can make
> > >   use of custom hardware. If no handler has been registered, or the
> > >   registered handler returns, then the system will be reset by
> > >   calling the Runtime Service ResetSystem(). So, this protocol is
> > >   required.
> > 
> > I am not disputing that the protocol is not required. I am suggesting
> > that this hardware watchdog _cannot_ be used to register a handler.
> > 
> > If this hardware watchdog does not get updated in time, that causes an
> > immediate hardware reset of the processor.
> > 
> > Because of this, I believe EFI_WATCHDOG_TIMER_ARCH_PROTOCOL is not the
> > appropriate way to make use of it.
> > 
> > Please let me know whether you agree.
> > 
> > Regards,
> > 
> > Leif
> > 
> > > Thanks
> > > Liming
> > > >-----Original Message-----
> > > >From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> > > >Sent: Tuesday, December 05, 2017 7:06 PM
> > > >To: Udit Kumar <udit.kumar@nxp.com>
> > > >Cc: Gao, Liming <liming.gao@intel.com>; Kinney, Michael D
> > > ><michael.d.kinney@intel.com>; Meenakshi Aggarwal
> > > ><meenakshi.aggarwal@nxp.com>; ard.biesheuvel@linaro.org; edk2-
> > > >devel@lists.01.org; Varun Sethi <V.Sethi@nxp.com>
> > > >Subject: Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add
> > > >support for Watchdog driver
> > > >
> > > >On Tue, Dec 05, 2017 at 05:07:00AM +0000, Udit Kumar wrote:
> > > >> >   I suggest return EFI_UNSUPPORTED for this case. The protocol
> > > >implementation
> > > >> > could return its status besides spec defined status.
> > > >>
> > > >> Thanks to help me , how core will treat this error
> > > >> 1/  Wdt not available
> > > >> 2/ ignoring this error
> > > >> 3/ core is not registering handler
> > > >> I guess 3 is valid,
> > > >
> > > >Looking at Core/Dxe/Misc/SetWatchdogTimer.c:
> > > >  //
> > > >  // Attempt to set the timeout
> > > >  //
> > > >  Status = gWatchdogTimer->SetTimerPeriod (gWatchdogTimer,
> > > >  MultU64x32 (Timeout, WATCHDOG_TIMER_CALIBRATE_PER_SECOND));
> > > >
> > > >  //
> > > >  // Check for errors
> > > >  //
> > > >  if (EFI_ERROR (Status)) {
> > > >    return EFI_DEVICE_ERROR;
> > > >  }
> > > >
> > > >The SetWatchdogTimer() call would always return EFI_DEVICE_ERROR.
> > > >
> > > >> On side track, looks wdt is not used by core services then do we
> > > >> really need this as part of arch protocol ?
> > > >
> > > >Yes, that was ultimately what I was implying with my question
> > > >regarding whether this protocol is relevant for a watchdog that can
> > > >only ever reset the system on timeout.
> > > >
> > > >The protocol looks to me to be designed to use a dedicated generic
> > > >timer as backing for a software watchdog.
> > > >
> > > >Liming, Mike?
> > > >
> > > >If that is the case, then I agree this driver should probably not
> > > >implement this protocol, but rather set up a timer event (or a
> > > >dedicated timer) to stroke the watchdog.
> > > >
> > > >Regards,
> > > >
> > > >Leif
> > > >
> > > >> regards
> > > >> Udit
> > > >>
> > > >> > -----Original Message-----
> > > >> > From: Gao, Liming [mailto:liming.gao@intel.com]
> > > >> > Sent: Monday, December 04, 2017 8:53 PM
> > > >> > To: Leif Lindholm <leif.lindholm@linaro.org>; Kinney, Michael D
> > > >> > <michael.d.kinney@intel.com>
> > > >> > Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>;
> > > >> > ard.biesheuvel@linaro.org; edk2-devel@lists.01.org; Udit Kumar
> > > >> > <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>
> > > >> > Subject: RE: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add
> > > >support
> > > >> > for Watchdog driver
> > > >> >
> > > >> > Leif:
> > > >> >   I suggest return EFI_UNSUPPORTED for this case. The protocol
> > > >implementation
> > > >> > could return its status besides spec defined status.
> > > >> >
> > > >> > Thanks
> > > >> > Liming
> > > >> > > -----Original Message-----
> > > >> > > From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> > > >> > > Sent: Monday, December 4, 2017 10:36 PM
> > > >> > > To: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming
> > > >> > > <liming.gao@intel.com>
> > > >> > > Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>;
> > > >> > > ard.biesheuvel@linaro.org; edk2-devel@lists.01.org;
> > > >> > > udit.kumar@nxp.com; v.sethi@nxp.com
> > > >> > > Subject: Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add
> > > >> > > support for Watchdog driver
> > > >> > >
> > > >> > > Mike, Liming, as MdePkg mainteiners - one question below:
> > > >> > >
> > > >> > > On Mon, Nov 27, 2017 at 04:21:50PM +0530, Meenakshi Aggarwal wrote:
> > > >> > > > diff --git a/Platform/NXP/Drivers/WatchDog/WatchDog.c
> > > >> > > > b/Platform/NXP/Drivers/WatchDog/WatchDog.c
> > > >> > > > new file mode 100644
> > > >> > > > index 0000000..a9c70ef
> > > >> > > > --- /dev/null
> > > >> > > > +++ b/Platform/NXP/Drivers/WatchDog/WatchDog.c
> > > >> > > > @@ -0,0 +1,421 @@
> > > >> > >
> > > >> > > ...
> > > >> > >
> > > >> > > > +/**
> > > >> > > > +  This function registers the handler NotifyFunction so it is
> > > >> > > > +called every time
> > > >> > > > +  the watchdog timer expires.  It also passes the amount of time
> > > >> > > > +since the last
> > > >> > > > +  handler call to the NotifyFunction.
> > > >> > > > +  If NotifyFunction is not NULL and a handler is not already
> > > >> > > > +registered,
> > > >> > > > +  then the new handler is registered and EFI_SUCCESS is returned.
> > > >> > > > +  If NotifyFunction is NULL, and a handler is already registered,
> > > >> > > > +  then that handler is unregistered.
> > > >> > > > +  If an attempt is made to register a handler when a handler is
> > > >> > > > +already registered,
> > > >> > > > +  then EFI_ALREADY_STARTED is returned.
> > > >> > > > +  If an attempt is made to unregister a handler when a handler is
> > > >> > > > +not registered,
> > > >> > > > +  then EFI_INVALID_PARAMETER is returned.
> > > >> > > > +
> > > >> > > > +  @param  This             The EFI_TIMER_ARCH_PROTOCOL instance.
> > > >> > > > +  @param  NotifyFunction   The function to call when a timer interrupt
> > > >fires.
> > > >> > This
> > > >> > > > +                           function executes at TPL_HIGH_LEVEL. The DXE Core
> > > >will
> > > >> > > > +                           register a handler for the timer interrupt, so it can know
> > > >> > > > +                           how much time has passed. This information is used to
> > > >> > > > +                           signal timer based events. NULL will unregister the
> > > >handler.
> > > >> > > > +
> > > >> > > > +  @retval EFI_SUCCESS           The watchdog timer handler was
> > > >registered.
> > > >> > > > +  @retval EFI_ALREADY_STARTED   NotifyFunction is not NULL, and a
> > > >> > handler is already
> > > >> > > > +                                registered.
> > > >> > > > +  @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a
> > > >handler
> > > >> > was not
> > > >> > > > +                                previously registered.
> > > >> > > > +
> > > >> > > > +**/
> > > >> > > > +STATIC
> > > >> > > > +EFI_STATUS
> > > >> > > > +EFIAPI
> > > >> > > > +WdogRegisterHandler (
> > > >> > > > +  IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL   *This,
> > > >> > > > +  IN EFI_WATCHDOG_TIMER_NOTIFY          NotifyFunction
> > > >> > > > +  )
> > > >> > > > +{
> > > >> > > > +  // ERROR: This function is not supported.
> > > >> > > > +  // The hardware watchdog will reset the board
> > > >> > > > +  return EFI_INVALID_PARAMETER;
> > > >> > >
> > > >> > > Michael, Liming - what's your take on this?
> > > >> > >
> > > >> > > Is EFI_WATCHDOG_TIMER_ARCH_PROTOCOL suitable for use with a
> > > >pure-hw
> > > >> > > watchdog such as this?
> > > >> > >
> > > >> > > If so, what would be a suitable return code here?
> > > >> > > EFI_INVALID_PARAMETER does not look ideal.
> > > >> > >
> > > >> > > /
> > > >> > >     Leif


^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add support for Watchdog driver
  2017-12-07 15:34                 ` Leif Lindholm
@ 2017-12-08  4:41                   ` Udit Kumar
  2017-12-10 13:30                   ` Gao, Liming
  1 sibling, 0 replies; 25+ messages in thread
From: Udit Kumar @ 2017-12-08  4:41 UTC (permalink / raw)
  To: Leif Lindholm, Gao, Liming
  Cc: Kinney, Michael D, Meenakshi Aggarwal, ard.biesheuvel@linaro.org,
	edk2-devel@lists.01.org, Varun Sethi

> Because when the hardware watchdog times out, it triggers a hard system reset,
> without any software interaction.

Little more complexity around this piece of h/w
e.g once watchdog is started it cannot be stopped. 
Most caller seems to set timeout of 5 mins and later stopping watchdog. 
But actually watchdog is not stopped and OS needs to be loaded within this time or some
specific application needs to ping it.

Thx
Udit


> -----Original Message-----
> From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> Sent: Thursday, December 07, 2017 9:04 PM
> To: Gao, Liming <liming.gao@intel.com>
> Cc: Udit Kumar <udit.kumar@nxp.com>; Kinney, Michael D
> <michael.d.kinney@intel.com>; Meenakshi Aggarwal
> <meenakshi.aggarwal@nxp.com>; ard.biesheuvel@linaro.org; edk2-
> devel@lists.01.org; Varun Sethi <V.Sethi@nxp.com>
> Subject: Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add support
> for Watchdog driver
> 
> Liming,
> 
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.
> mail-archive.com%2Fedk2-
> devel%40lists.01.org%2Fmsg32761.html&data=02%7C01%7Cudit.kumar%40nxp
> .com%7Cb5a84bfc5cdc435a605e08d53d87ff95%7C686ea1d3bc2b4c6fa92cd99c
> 5c301635%7C0%7C0%7C636482576674878205&sdata=w3k%2B7Aw6D78uaTty
> GOh%2F8JUSiHVIdpCPkBudMth6m%2Fw%3D&reserved=0
> Search for WdogRegisterHandler.
> 
> This topic is entirely unrelated to any _usage_ of watchdog timer protocol.
> 
> The topic is only whether it is reasonable to _implement_
> EFI_WATCHDOG_TIMER_ARCH_PROTOCOL for a hardware watchdog that
> *cannot* cause a callback to a handler function.
> Because when the hardware watchdog times out, it triggers a hard system reset,
> without any software interaction.
> 
> /
>     Leif
> 
> On Thu, Dec 07, 2017 at 02:54:08PM +0000, Gao, Liming wrote:
> > Leif:
> >   I don't review the whole patch serial. Could you point your usage
> >   case on watch dog timer protocol?
> >
> > Thanks
> > Liming
> > > -----Original Message-----
> > > From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> > > Sent: Thursday, December 7, 2017 7:04 PM
> > > To: Gao, Liming <liming.gao@intel.com>
> > > Cc: Udit Kumar <udit.kumar@nxp.com>; Kinney, Michael D
> > > <michael.d.kinney@intel.com>; Meenakshi Aggarwal
> > > <meenakshi.aggarwal@nxp.com>; ard.biesheuvel@linaro.org;
> > > edk2-devel@lists.01.org; Varun Sethi <V.Sethi@nxp.com>
> > > Subject: Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP :
> > > Add support for Watchdog driver
> > >
> > > Hi Liming,
> > >
> > > On Thu, Dec 07, 2017 at 07:11:38AM +0000, Gao, Liming wrote:
> > > > Leif:
> > > >   I don't see the core driver uses
> > > >   WatchdogTimer->RegisterHandler(). When it returns unsupported, it
> > > >   means the additional handler can't be registered. DxeCore uses
> > > >   WatchdogTimer->SetTimerPeriod(). This service is implemented in
> > > >   your driver.
> > > >
> > > >   Watchdog protocol is defined in PI spec. Spec describes that this
> > > >   protocol provides the services required to implement the Boot
> > > >   Service SetWatchdogTimer(). It provides a service to set the
> > > >   amount of time to wait before firing the watchdog timer, and it
> > > >   also provides a service to register a handler that is invoked when
> > > >   the watchdog timer fires. This protocol can implement the watchdog
> > > >   timer by using the event and timer Boot Services, or it can make
> > > >   use of custom hardware. If no handler has been registered, or the
> > > >   registered handler returns, then the system will be reset by
> > > >   calling the Runtime Service ResetSystem(). So, this protocol is
> > > >   required.
> > >
> > > I am not disputing that the protocol is not required. I am
> > > suggesting that this hardware watchdog _cannot_ be used to register a
> handler.
> > >
> > > If this hardware watchdog does not get updated in time, that causes
> > > an immediate hardware reset of the processor.
> > >
> > > Because of this, I believe EFI_WATCHDOG_TIMER_ARCH_PROTOCOL is not
> > > the appropriate way to make use of it.
> > >
> > > Please let me know whether you agree.
> > >
> > > Regards,
> > >
> > > Leif
> > >
> > > > Thanks
> > > > Liming
> > > > >-----Original Message-----
> > > > >From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> > > > >Sent: Tuesday, December 05, 2017 7:06 PM
> > > > >To: Udit Kumar <udit.kumar@nxp.com>
> > > > >Cc: Gao, Liming <liming.gao@intel.com>; Kinney, Michael D
> > > > ><michael.d.kinney@intel.com>; Meenakshi Aggarwal
> > > > ><meenakshi.aggarwal@nxp.com>; ard.biesheuvel@linaro.org; edk2-
> > > > >devel@lists.01.org; Varun Sethi <V.Sethi@nxp.com>
> > > > >Subject: Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP :
> > > > >Add support for Watchdog driver
> > > > >
> > > > >On Tue, Dec 05, 2017 at 05:07:00AM +0000, Udit Kumar wrote:
> > > > >> >   I suggest return EFI_UNSUPPORTED for this case. The
> > > > >> > protocol
> > > > >implementation
> > > > >> > could return its status besides spec defined status.
> > > > >>
> > > > >> Thanks to help me , how core will treat this error 1/  Wdt not
> > > > >> available 2/ ignoring this error 3/ core is not registering
> > > > >> handler I guess 3 is valid,
> > > > >
> > > > >Looking at Core/Dxe/Misc/SetWatchdogTimer.c:
> > > > >  //
> > > > >  // Attempt to set the timeout
> > > > >  //
> > > > >  Status = gWatchdogTimer->SetTimerPeriod (gWatchdogTimer,
> > > > >  MultU64x32 (Timeout, WATCHDOG_TIMER_CALIBRATE_PER_SECOND));
> > > > >
> > > > >  //
> > > > >  // Check for errors
> > > > >  //
> > > > >  if (EFI_ERROR (Status)) {
> > > > >    return EFI_DEVICE_ERROR;
> > > > >  }
> > > > >
> > > > >The SetWatchdogTimer() call would always return EFI_DEVICE_ERROR.
> > > > >
> > > > >> On side track, looks wdt is not used by core services then do
> > > > >> we really need this as part of arch protocol ?
> > > > >
> > > > >Yes, that was ultimately what I was implying with my question
> > > > >regarding whether this protocol is relevant for a watchdog that
> > > > >can only ever reset the system on timeout.
> > > > >
> > > > >The protocol looks to me to be designed to use a dedicated
> > > > >generic timer as backing for a software watchdog.
> > > > >
> > > > >Liming, Mike?
> > > > >
> > > > >If that is the case, then I agree this driver should probably not
> > > > >implement this protocol, but rather set up a timer event (or a
> > > > >dedicated timer) to stroke the watchdog.
> > > > >
> > > > >Regards,
> > > > >
> > > > >Leif
> > > > >
> > > > >> regards
> > > > >> Udit
> > > > >>
> > > > >> > -----Original Message-----
> > > > >> > From: Gao, Liming [mailto:liming.gao@intel.com]
> > > > >> > Sent: Monday, December 04, 2017 8:53 PM
> > > > >> > To: Leif Lindholm <leif.lindholm@linaro.org>; Kinney, Michael
> > > > >> > D <michael.d.kinney@intel.com>
> > > > >> > Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>;
> > > > >> > ard.biesheuvel@linaro.org; edk2-devel@lists.01.org; Udit
> > > > >> > Kumar <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>
> > > > >> > Subject: RE: [PATCH edk2-platforms] [PATCH v3 2/9]
> > > > >> > Platform/NXP : Add
> > > > >support
> > > > >> > for Watchdog driver
> > > > >> >
> > > > >> > Leif:
> > > > >> >   I suggest return EFI_UNSUPPORTED for this case. The
> > > > >> > protocol
> > > > >implementation
> > > > >> > could return its status besides spec defined status.
> > > > >> >
> > > > >> > Thanks
> > > > >> > Liming
> > > > >> > > -----Original Message-----
> > > > >> > > From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> > > > >> > > Sent: Monday, December 4, 2017 10:36 PM
> > > > >> > > To: Kinney, Michael D <michael.d.kinney@intel.com>; Gao,
> > > > >> > > Liming <liming.gao@intel.com>
> > > > >> > > Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>;
> > > > >> > > ard.biesheuvel@linaro.org; edk2-devel@lists.01.org;
> > > > >> > > udit.kumar@nxp.com; v.sethi@nxp.com
> > > > >> > > Subject: Re: [PATCH edk2-platforms] [PATCH v3 2/9]
> > > > >> > > Platform/NXP : Add support for Watchdog driver
> > > > >> > >
> > > > >> > > Mike, Liming, as MdePkg mainteiners - one question below:
> > > > >> > >
> > > > >> > > On Mon, Nov 27, 2017 at 04:21:50PM +0530, Meenakshi Aggarwal
> wrote:
> > > > >> > > > diff --git a/Platform/NXP/Drivers/WatchDog/WatchDog.c
> > > > >> > > > b/Platform/NXP/Drivers/WatchDog/WatchDog.c
> > > > >> > > > new file mode 100644
> > > > >> > > > index 0000000..a9c70ef
> > > > >> > > > --- /dev/null
> > > > >> > > > +++ b/Platform/NXP/Drivers/WatchDog/WatchDog.c
> > > > >> > > > @@ -0,0 +1,421 @@
> > > > >> > >
> > > > >> > > ...
> > > > >> > >
> > > > >> > > > +/**
> > > > >> > > > +  This function registers the handler NotifyFunction so
> > > > >> > > > +it is called every time
> > > > >> > > > +  the watchdog timer expires.  It also passes the amount
> > > > >> > > > +of time since the last
> > > > >> > > > +  handler call to the NotifyFunction.
> > > > >> > > > +  If NotifyFunction is not NULL and a handler is not
> > > > >> > > > +already registered,
> > > > >> > > > +  then the new handler is registered and EFI_SUCCESS is returned.
> > > > >> > > > +  If NotifyFunction is NULL, and a handler is already
> > > > >> > > > +registered,
> > > > >> > > > +  then that handler is unregistered.
> > > > >> > > > +  If an attempt is made to register a handler when a
> > > > >> > > > +handler is already registered,
> > > > >> > > > +  then EFI_ALREADY_STARTED is returned.
> > > > >> > > > +  If an attempt is made to unregister a handler when a
> > > > >> > > > +handler is not registered,
> > > > >> > > > +  then EFI_INVALID_PARAMETER is returned.
> > > > >> > > > +
> > > > >> > > > +  @param  This             The EFI_TIMER_ARCH_PROTOCOL
> instance.
> > > > >> > > > +  @param  NotifyFunction   The function to call when a timer
> interrupt
> > > > >fires.
> > > > >> > This
> > > > >> > > > +                           function executes at
> > > > >> > > > + TPL_HIGH_LEVEL. The DXE Core
> > > > >will
> > > > >> > > > +                           register a handler for the timer interrupt, so it can
> know
> > > > >> > > > +                           how much time has passed. This information is
> used to
> > > > >> > > > +                           signal timer based events.
> > > > >> > > > + NULL will unregister the
> > > > >handler.
> > > > >> > > > +
> > > > >> > > > +  @retval EFI_SUCCESS           The watchdog timer handler was
> > > > >registered.
> > > > >> > > > +  @retval EFI_ALREADY_STARTED   NotifyFunction is not NULL,
> and a
> > > > >> > handler is already
> > > > >> > > > +                                registered.
> > > > >> > > > +  @retval EFI_INVALID_PARAMETER NotifyFunction is NULL,
> > > > >> > > > + and a
> > > > >handler
> > > > >> > was not
> > > > >> > > > +                                previously registered.
> > > > >> > > > +
> > > > >> > > > +**/
> > > > >> > > > +STATIC
> > > > >> > > > +EFI_STATUS
> > > > >> > > > +EFIAPI
> > > > >> > > > +WdogRegisterHandler (
> > > > >> > > > +  IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL   *This,
> > > > >> > > > +  IN EFI_WATCHDOG_TIMER_NOTIFY          NotifyFunction
> > > > >> > > > +  )
> > > > >> > > > +{
> > > > >> > > > +  // ERROR: This function is not supported.
> > > > >> > > > +  // The hardware watchdog will reset the board
> > > > >> > > > +  return EFI_INVALID_PARAMETER;
> > > > >> > >
> > > > >> > > Michael, Liming - what's your take on this?
> > > > >> > >
> > > > >> > > Is EFI_WATCHDOG_TIMER_ARCH_PROTOCOL suitable for use with a
> > > > >pure-hw
> > > > >> > > watchdog such as this?
> > > > >> > >
> > > > >> > > If so, what would be a suitable return code here?
> > > > >> > > EFI_INVALID_PARAMETER does not look ideal.
> > > > >> > >
> > > > >> > > /
> > > > >> > >     Leif


^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add support for Watchdog driver
  2017-12-07 15:34                 ` Leif Lindholm
  2017-12-08  4:41                   ` Udit Kumar
@ 2017-12-10 13:30                   ` Gao, Liming
  2017-12-14  3:37                     ` Meenakshi Aggarwal
  1 sibling, 1 reply; 25+ messages in thread
From: Gao, Liming @ 2017-12-10 13:30 UTC (permalink / raw)
  To: Leif Lindholm
  Cc: ard.biesheuvel@linaro.org, edk2-devel@lists.01.org,
	Kinney, Michael D

Leif:
  I have no strong opinion. PI spec doesn't require WdogRegisterHandler must be supported. So, this implementation doesn't break spec. For this platform, if there is no register handler or no critical register handler, this Watchdog driver can be used. 

Thanks
Liming
> -----Original Message-----
> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Leif Lindholm
> Sent: Thursday, December 7, 2017 11:34 PM
> To: Gao, Liming <liming.gao@intel.com>
> Cc: ard.biesheuvel@linaro.org; edk2-devel@lists.01.org; Kinney, Michael D <michael.d.kinney@intel.com>
> Subject: Re: [edk2] [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add support for Watchdog driver
> 
> Liming,
> 
> https://www.mail-archive.com/edk2-devel@lists.01.org/msg32761.html
> Search for WdogRegisterHandler.
> 
> This topic is entirely unrelated to any _usage_ of watchdog timer
> protocol.
> 
> The topic is only whether it is reasonable to _implement_
> EFI_WATCHDOG_TIMER_ARCH_PROTOCOL for a hardware watchdog that *cannot*
> cause a callback to a handler function.
> Because when the hardware watchdog times out, it triggers a hard
> system reset, without any software interaction.
> 
> /
>     Leif
> 
> On Thu, Dec 07, 2017 at 02:54:08PM +0000, Gao, Liming wrote:
> > Leif:
> >   I don't review the whole patch serial. Could you point your usage
> >   case on watch dog timer protocol?
> >
> > Thanks
> > Liming
> > > -----Original Message-----
> > > From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> > > Sent: Thursday, December 7, 2017 7:04 PM
> > > To: Gao, Liming <liming.gao@intel.com>
> > > Cc: Udit Kumar <udit.kumar@nxp.com>; Kinney, Michael D <michael.d.kinney@intel.com>; Meenakshi Aggarwal
> > > <meenakshi.aggarwal@nxp.com>; ard.biesheuvel@linaro.org; edk2-devel@lists.01.org; Varun Sethi <V.Sethi@nxp.com>
> > > Subject: Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add support for Watchdog driver
> > >
> > > Hi Liming,
> > >
> > > On Thu, Dec 07, 2017 at 07:11:38AM +0000, Gao, Liming wrote:
> > > > Leif:
> > > >   I don't see the core driver uses
> > > >   WatchdogTimer->RegisterHandler(). When it returns unsupported, it
> > > >   means the additional handler can't be registered. DxeCore uses
> > > >   WatchdogTimer->SetTimerPeriod(). This service is implemented in
> > > >   your driver.
> > > >
> > > >   Watchdog protocol is defined in PI spec. Spec describes that this
> > > >   protocol provides the services required to implement the Boot
> > > >   Service SetWatchdogTimer(). It provides a service to set the
> > > >   amount of time to wait before firing the watchdog timer, and it
> > > >   also provides a service to register a handler that is invoked when
> > > >   the watchdog timer fires. This protocol can implement the watchdog
> > > >   timer by using the event and timer Boot Services, or it can make
> > > >   use of custom hardware. If no handler has been registered, or the
> > > >   registered handler returns, then the system will be reset by
> > > >   calling the Runtime Service ResetSystem(). So, this protocol is
> > > >   required.
> > >
> > > I am not disputing that the protocol is not required. I am suggesting
> > > that this hardware watchdog _cannot_ be used to register a handler.
> > >
> > > If this hardware watchdog does not get updated in time, that causes an
> > > immediate hardware reset of the processor.
> > >
> > > Because of this, I believe EFI_WATCHDOG_TIMER_ARCH_PROTOCOL is not the
> > > appropriate way to make use of it.
> > >
> > > Please let me know whether you agree.
> > >
> > > Regards,
> > >
> > > Leif
> > >
> > > > Thanks
> > > > Liming
> > > > >-----Original Message-----
> > > > >From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> > > > >Sent: Tuesday, December 05, 2017 7:06 PM
> > > > >To: Udit Kumar <udit.kumar@nxp.com>
> > > > >Cc: Gao, Liming <liming.gao@intel.com>; Kinney, Michael D
> > > > ><michael.d.kinney@intel.com>; Meenakshi Aggarwal
> > > > ><meenakshi.aggarwal@nxp.com>; ard.biesheuvel@linaro.org; edk2-
> > > > >devel@lists.01.org; Varun Sethi <V.Sethi@nxp.com>
> > > > >Subject: Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add
> > > > >support for Watchdog driver
> > > > >
> > > > >On Tue, Dec 05, 2017 at 05:07:00AM +0000, Udit Kumar wrote:
> > > > >> >   I suggest return EFI_UNSUPPORTED for this case. The protocol
> > > > >implementation
> > > > >> > could return its status besides spec defined status.
> > > > >>
> > > > >> Thanks to help me , how core will treat this error
> > > > >> 1/  Wdt not available
> > > > >> 2/ ignoring this error
> > > > >> 3/ core is not registering handler
> > > > >> I guess 3 is valid,
> > > > >
> > > > >Looking at Core/Dxe/Misc/SetWatchdogTimer.c:
> > > > >  //
> > > > >  // Attempt to set the timeout
> > > > >  //
> > > > >  Status = gWatchdogTimer->SetTimerPeriod (gWatchdogTimer,
> > > > >  MultU64x32 (Timeout, WATCHDOG_TIMER_CALIBRATE_PER_SECOND));
> > > > >
> > > > >  //
> > > > >  // Check for errors
> > > > >  //
> > > > >  if (EFI_ERROR (Status)) {
> > > > >    return EFI_DEVICE_ERROR;
> > > > >  }
> > > > >
> > > > >The SetWatchdogTimer() call would always return EFI_DEVICE_ERROR.
> > > > >
> > > > >> On side track, looks wdt is not used by core services then do we
> > > > >> really need this as part of arch protocol ?
> > > > >
> > > > >Yes, that was ultimately what I was implying with my question
> > > > >regarding whether this protocol is relevant for a watchdog that can
> > > > >only ever reset the system on timeout.
> > > > >
> > > > >The protocol looks to me to be designed to use a dedicated generic
> > > > >timer as backing for a software watchdog.
> > > > >
> > > > >Liming, Mike?
> > > > >
> > > > >If that is the case, then I agree this driver should probably not
> > > > >implement this protocol, but rather set up a timer event (or a
> > > > >dedicated timer) to stroke the watchdog.
> > > > >
> > > > >Regards,
> > > > >
> > > > >Leif
> > > > >
> > > > >> regards
> > > > >> Udit
> > > > >>
> > > > >> > -----Original Message-----
> > > > >> > From: Gao, Liming [mailto:liming.gao@intel.com]
> > > > >> > Sent: Monday, December 04, 2017 8:53 PM
> > > > >> > To: Leif Lindholm <leif.lindholm@linaro.org>; Kinney, Michael D
> > > > >> > <michael.d.kinney@intel.com>
> > > > >> > Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>;
> > > > >> > ard.biesheuvel@linaro.org; edk2-devel@lists.01.org; Udit Kumar
> > > > >> > <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>
> > > > >> > Subject: RE: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add
> > > > >support
> > > > >> > for Watchdog driver
> > > > >> >
> > > > >> > Leif:
> > > > >> >   I suggest return EFI_UNSUPPORTED for this case. The protocol
> > > > >implementation
> > > > >> > could return its status besides spec defined status.
> > > > >> >
> > > > >> > Thanks
> > > > >> > Liming
> > > > >> > > -----Original Message-----
> > > > >> > > From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> > > > >> > > Sent: Monday, December 4, 2017 10:36 PM
> > > > >> > > To: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming
> > > > >> > > <liming.gao@intel.com>
> > > > >> > > Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>;
> > > > >> > > ard.biesheuvel@linaro.org; edk2-devel@lists.01.org;
> > > > >> > > udit.kumar@nxp.com; v.sethi@nxp.com
> > > > >> > > Subject: Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add
> > > > >> > > support for Watchdog driver
> > > > >> > >
> > > > >> > > Mike, Liming, as MdePkg mainteiners - one question below:
> > > > >> > >
> > > > >> > > On Mon, Nov 27, 2017 at 04:21:50PM +0530, Meenakshi Aggarwal wrote:
> > > > >> > > > diff --git a/Platform/NXP/Drivers/WatchDog/WatchDog.c
> > > > >> > > > b/Platform/NXP/Drivers/WatchDog/WatchDog.c
> > > > >> > > > new file mode 100644
> > > > >> > > > index 0000000..a9c70ef
> > > > >> > > > --- /dev/null
> > > > >> > > > +++ b/Platform/NXP/Drivers/WatchDog/WatchDog.c
> > > > >> > > > @@ -0,0 +1,421 @@
> > > > >> > >
> > > > >> > > ...
> > > > >> > >
> > > > >> > > > +/**
> > > > >> > > > +  This function registers the handler NotifyFunction so it is
> > > > >> > > > +called every time
> > > > >> > > > +  the watchdog timer expires.  It also passes the amount of time
> > > > >> > > > +since the last
> > > > >> > > > +  handler call to the NotifyFunction.
> > > > >> > > > +  If NotifyFunction is not NULL and a handler is not already
> > > > >> > > > +registered,
> > > > >> > > > +  then the new handler is registered and EFI_SUCCESS is returned.
> > > > >> > > > +  If NotifyFunction is NULL, and a handler is already registered,
> > > > >> > > > +  then that handler is unregistered.
> > > > >> > > > +  If an attempt is made to register a handler when a handler is
> > > > >> > > > +already registered,
> > > > >> > > > +  then EFI_ALREADY_STARTED is returned.
> > > > >> > > > +  If an attempt is made to unregister a handler when a handler is
> > > > >> > > > +not registered,
> > > > >> > > > +  then EFI_INVALID_PARAMETER is returned.
> > > > >> > > > +
> > > > >> > > > +  @param  This             The EFI_TIMER_ARCH_PROTOCOL instance.
> > > > >> > > > +  @param  NotifyFunction   The function to call when a timer interrupt
> > > > >fires.
> > > > >> > This
> > > > >> > > > +                           function executes at TPL_HIGH_LEVEL. The DXE Core
> > > > >will
> > > > >> > > > +                           register a handler for the timer interrupt, so it can know
> > > > >> > > > +                           how much time has passed. This information is used to
> > > > >> > > > +                           signal timer based events. NULL will unregister the
> > > > >handler.
> > > > >> > > > +
> > > > >> > > > +  @retval EFI_SUCCESS           The watchdog timer handler was
> > > > >registered.
> > > > >> > > > +  @retval EFI_ALREADY_STARTED   NotifyFunction is not NULL, and a
> > > > >> > handler is already
> > > > >> > > > +                                registered.
> > > > >> > > > +  @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a
> > > > >handler
> > > > >> > was not
> > > > >> > > > +                                previously registered.
> > > > >> > > > +
> > > > >> > > > +**/
> > > > >> > > > +STATIC
> > > > >> > > > +EFI_STATUS
> > > > >> > > > +EFIAPI
> > > > >> > > > +WdogRegisterHandler (
> > > > >> > > > +  IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL   *This,
> > > > >> > > > +  IN EFI_WATCHDOG_TIMER_NOTIFY          NotifyFunction
> > > > >> > > > +  )
> > > > >> > > > +{
> > > > >> > > > +  // ERROR: This function is not supported.
> > > > >> > > > +  // The hardware watchdog will reset the board
> > > > >> > > > +  return EFI_INVALID_PARAMETER;
> > > > >> > >
> > > > >> > > Michael, Liming - what's your take on this?
> > > > >> > >
> > > > >> > > Is EFI_WATCHDOG_TIMER_ARCH_PROTOCOL suitable for use with a
> > > > >pure-hw
> > > > >> > > watchdog such as this?
> > > > >> > >
> > > > >> > > If so, what would be a suitable return code here?
> > > > >> > > EFI_INVALID_PARAMETER does not look ideal.
> > > > >> > >
> > > > >> > > /
> > > > >> > >     Leif
> _______________________________________________
> edk2-devel mailing list
> edk2-devel@lists.01.org
> https://lists.01.org/mailman/listinfo/edk2-devel


^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add support for Watchdog driver
  2017-12-10 13:30                   ` Gao, Liming
@ 2017-12-14  3:37                     ` Meenakshi Aggarwal
  0 siblings, 0 replies; 25+ messages in thread
From: Meenakshi Aggarwal @ 2017-12-14  3:37 UTC (permalink / raw)
  To: Gao, Liming, Leif Lindholm
  Cc: Kinney, Michael D, edk2-devel@lists.01.org,
	ard.biesheuvel@linaro.org, Udit Kumar, Varun Sethi

Hi,

There is no clean way to register a handler with this watchdog controller.
Even if we do then there are chances that false notification will be sent to the module which has registered a handler.

We can go ahead with this implementation, i assume and i will share new revision of patch replacing EFI_INVALID_PARAMETER with EFI_UNSUPPORTED.

Please share your feedback.

Thanks,
Meenakshi

> -----Original Message-----
> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of
> Gao, Liming
> Sent: Sunday, December 10, 2017 7:01 PM
> To: Leif Lindholm <leif.lindholm@linaro.org>
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; edk2-
> devel@lists.01.org; ard.biesheuvel@linaro.org
> Subject: Re: [edk2] [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP :
> Add support for Watchdog driver
> 
> Leif:
>   I have no strong opinion. PI spec doesn't require WdogRegisterHandler
> must be supported. So, this implementation doesn't break spec. For this
> platform, if there is no register handler or no critical register handler, this
> Watchdog driver can be used.
> 
> Thanks
> Liming
> > -----Original Message-----
> > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of
> Leif Lindholm
> > Sent: Thursday, December 7, 2017 11:34 PM
> > To: Gao, Liming <liming.gao@intel.com>
> > Cc: ard.biesheuvel@linaro.org; edk2-devel@lists.01.org; Kinney, Michael D
> <michael.d.kinney@intel.com>
> > Subject: Re: [edk2] [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP :
> Add support for Watchdog driver
> >
> > Liming,
> >
> >
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fw
> ww.mail-archive.com%2Fedk2-
> devel%40lists.01.org%2Fmsg32761.html&data=02%7C01%7Cmeenakshi.aggar
> wal%40nxp.com%7C3b6ad3d8cfdd4a766c4a08d53fd23a09%7C686ea1d3bc2b4
> c6fa92cd99c5c301635%7C0%7C0%7C636485094541353596&sdata=kEb4x9jl1ng
> %2FlumodoxsB5i4RD3NmTUgX9GN9KcKtkI%3D&reserved=0
> > Search for WdogRegisterHandler.
> >
> > This topic is entirely unrelated to any _usage_ of watchdog timer
> > protocol.
> >
> > The topic is only whether it is reasonable to _implement_
> > EFI_WATCHDOG_TIMER_ARCH_PROTOCOL for a hardware watchdog that
> *cannot*
> > cause a callback to a handler function.
> > Because when the hardware watchdog times out, it triggers a hard
> > system reset, without any software interaction.
> >
> > /
> >     Leif
> >
> > On Thu, Dec 07, 2017 at 02:54:08PM +0000, Gao, Liming wrote:
> > > Leif:
> > >   I don't review the whole patch serial. Could you point your usage
> > >   case on watch dog timer protocol?
> > >
> > > Thanks
> > > Liming
> > > > -----Original Message-----
> > > > From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> > > > Sent: Thursday, December 7, 2017 7:04 PM
> > > > To: Gao, Liming <liming.gao@intel.com>
> > > > Cc: Udit Kumar <udit.kumar@nxp.com>; Kinney, Michael D
> <michael.d.kinney@intel.com>; Meenakshi Aggarwal
> > > > <meenakshi.aggarwal@nxp.com>; ard.biesheuvel@linaro.org; edk2-
> devel@lists.01.org; Varun Sethi <V.Sethi@nxp.com>
> > > > Subject: Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP :
> Add support for Watchdog driver
> > > >
> > > > Hi Liming,
> > > >
> > > > On Thu, Dec 07, 2017 at 07:11:38AM +0000, Gao, Liming wrote:
> > > > > Leif:
> > > > >   I don't see the core driver uses
> > > > >   WatchdogTimer->RegisterHandler(). When it returns unsupported, it
> > > > >   means the additional handler can't be registered. DxeCore uses
> > > > >   WatchdogTimer->SetTimerPeriod(). This service is implemented in
> > > > >   your driver.
> > > > >
> > > > >   Watchdog protocol is defined in PI spec. Spec describes that this
> > > > >   protocol provides the services required to implement the Boot
> > > > >   Service SetWatchdogTimer(). It provides a service to set the
> > > > >   amount of time to wait before firing the watchdog timer, and it
> > > > >   also provides a service to register a handler that is invoked when
> > > > >   the watchdog timer fires. This protocol can implement the watchdog
> > > > >   timer by using the event and timer Boot Services, or it can make
> > > > >   use of custom hardware. If no handler has been registered, or the
> > > > >   registered handler returns, then the system will be reset by
> > > > >   calling the Runtime Service ResetSystem(). So, this protocol is
> > > > >   required.
> > > >
> > > > I am not disputing that the protocol is not required. I am suggesting
> > > > that this hardware watchdog _cannot_ be used to register a handler.
> > > >
> > > > If this hardware watchdog does not get updated in time, that causes an
> > > > immediate hardware reset of the processor.
> > > >
> > > > Because of this, I believe EFI_WATCHDOG_TIMER_ARCH_PROTOCOL is
> not the
> > > > appropriate way to make use of it.
> > > >
> > > > Please let me know whether you agree.
> > > >
> > > > Regards,
> > > >
> > > > Leif
> > > >
> > > > > Thanks
> > > > > Liming
> > > > > >-----Original Message-----
> > > > > >From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> > > > > >Sent: Tuesday, December 05, 2017 7:06 PM
> > > > > >To: Udit Kumar <udit.kumar@nxp.com>
> > > > > >Cc: Gao, Liming <liming.gao@intel.com>; Kinney, Michael D
> > > > > ><michael.d.kinney@intel.com>; Meenakshi Aggarwal
> > > > > ><meenakshi.aggarwal@nxp.com>; ard.biesheuvel@linaro.org; edk2-
> > > > > >devel@lists.01.org; Varun Sethi <V.Sethi@nxp.com>
> > > > > >Subject: Re: [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP :
> Add
> > > > > >support for Watchdog driver
> > > > > >
> > > > > >On Tue, Dec 05, 2017 at 05:07:00AM +0000, Udit Kumar wrote:
> > > > > >> >   I suggest return EFI_UNSUPPORTED for this case. The protocol
> > > > > >implementation
> > > > > >> > could return its status besides spec defined status.
> > > > > >>
> > > > > >> Thanks to help me , how core will treat this error
> > > > > >> 1/  Wdt not available
> > > > > >> 2/ ignoring this error
> > > > > >> 3/ core is not registering handler
> > > > > >> I guess 3 is valid,
> > > > > >
> > > > > >Looking at Core/Dxe/Misc/SetWatchdogTimer.c:
> > > > > >  //
> > > > > >  // Attempt to set the timeout
> > > > > >  //
> > > > > >  Status = gWatchdogTimer->SetTimerPeriod (gWatchdogTimer,
> > > > > >  MultU64x32 (Timeout,
> WATCHDOG_TIMER_CALIBRATE_PER_SECOND));
> > > > > >
> > > > > >  //
> > > > > >  // Check for errors
> > > > > >  //
> > > > > >  if (EFI_ERROR (Status)) {
> > > > > >    return EFI_DEVICE_ERROR;
> > > > > >  }
> > > > > >
> > > > > >The SetWatchdogTimer() call would always return
> EFI_DEVICE_ERROR.
> > > > > >
> > > > > >> On side track, looks wdt is not used by core services then do we
> > > > > >> really need this as part of arch protocol ?
> > > > > >
> > > > > >Yes, that was ultimately what I was implying with my question
> > > > > >regarding whether this protocol is relevant for a watchdog that can
> > > > > >only ever reset the system on timeout.
> > > > > >
> > > > > >The protocol looks to me to be designed to use a dedicated generic
> > > > > >timer as backing for a software watchdog.
> > > > > >
> > > > > >Liming, Mike?
> > > > > >
> > > > > >If that is the case, then I agree this driver should probably not
> > > > > >implement this protocol, but rather set up a timer event (or a
> > > > > >dedicated timer) to stroke the watchdog.
> > > > > >
> > > > > >Regards,
> > > > > >
> > > > > >Leif
> > > > > >
> > > > > >> regards
> > > > > >> Udit
> > > > > >>
> > > > > >> > -----Original Message-----
> > > > > >> > From: Gao, Liming [mailto:liming.gao@intel.com]
> > > > > >> > Sent: Monday, December 04, 2017 8:53 PM
> > > > > >> > To: Leif Lindholm <leif.lindholm@linaro.org>; Kinney, Michael D
> > > > > >> > <michael.d.kinney@intel.com>
> > > > > >> > Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>;
> > > > > >> > ard.biesheuvel@linaro.org; edk2-devel@lists.01.org; Udit Kumar
> > > > > >> > <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>
> > > > > >> > Subject: RE: [PATCH edk2-platforms] [PATCH v3 2/9]
> Platform/NXP : Add
> > > > > >support
> > > > > >> > for Watchdog driver
> > > > > >> >
> > > > > >> > Leif:
> > > > > >> >   I suggest return EFI_UNSUPPORTED for this case. The protocol
> > > > > >implementation
> > > > > >> > could return its status besides spec defined status.
> > > > > >> >
> > > > > >> > Thanks
> > > > > >> > Liming
> > > > > >> > > -----Original Message-----
> > > > > >> > > From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> > > > > >> > > Sent: Monday, December 4, 2017 10:36 PM
> > > > > >> > > To: Kinney, Michael D <michael.d.kinney@intel.com>; Gao,
> Liming
> > > > > >> > > <liming.gao@intel.com>
> > > > > >> > > Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>;
> > > > > >> > > ard.biesheuvel@linaro.org; edk2-devel@lists.01.org;
> > > > > >> > > udit.kumar@nxp.com; v.sethi@nxp.com
> > > > > >> > > Subject: Re: [PATCH edk2-platforms] [PATCH v3 2/9]
> Platform/NXP : Add
> > > > > >> > > support for Watchdog driver
> > > > > >> > >
> > > > > >> > > Mike, Liming, as MdePkg mainteiners - one question below:
> > > > > >> > >
> > > > > >> > > On Mon, Nov 27, 2017 at 04:21:50PM +0530, Meenakshi
> Aggarwal wrote:
> > > > > >> > > > diff --git a/Platform/NXP/Drivers/WatchDog/WatchDog.c
> > > > > >> > > > b/Platform/NXP/Drivers/WatchDog/WatchDog.c
> > > > > >> > > > new file mode 100644
> > > > > >> > > > index 0000000..a9c70ef
> > > > > >> > > > --- /dev/null
> > > > > >> > > > +++ b/Platform/NXP/Drivers/WatchDog/WatchDog.c
> > > > > >> > > > @@ -0,0 +1,421 @@
> > > > > >> > >
> > > > > >> > > ...
> > > > > >> > >
> > > > > >> > > > +/**
> > > > > >> > > > +  This function registers the handler NotifyFunction so it is
> > > > > >> > > > +called every time
> > > > > >> > > > +  the watchdog timer expires.  It also passes the amount of
> time
> > > > > >> > > > +since the last
> > > > > >> > > > +  handler call to the NotifyFunction.
> > > > > >> > > > +  If NotifyFunction is not NULL and a handler is not already
> > > > > >> > > > +registered,
> > > > > >> > > > +  then the new handler is registered and EFI_SUCCESS is
> returned.
> > > > > >> > > > +  If NotifyFunction is NULL, and a handler is already
> registered,
> > > > > >> > > > +  then that handler is unregistered.
> > > > > >> > > > +  If an attempt is made to register a handler when a handler
> is
> > > > > >> > > > +already registered,
> > > > > >> > > > +  then EFI_ALREADY_STARTED is returned.
> > > > > >> > > > +  If an attempt is made to unregister a handler when a
> handler is
> > > > > >> > > > +not registered,
> > > > > >> > > > +  then EFI_INVALID_PARAMETER is returned.
> > > > > >> > > > +
> > > > > >> > > > +  @param  This             The EFI_TIMER_ARCH_PROTOCOL
> instance.
> > > > > >> > > > +  @param  NotifyFunction   The function to call when a timer
> interrupt
> > > > > >fires.
> > > > > >> > This
> > > > > >> > > > +                           function executes at TPL_HIGH_LEVEL. The
> DXE Core
> > > > > >will
> > > > > >> > > > +                           register a handler for the timer interrupt, so it
> can know
> > > > > >> > > > +                           how much time has passed. This information is
> used to
> > > > > >> > > > +                           signal timer based events. NULL will unregister
> the
> > > > > >handler.
> > > > > >> > > > +
> > > > > >> > > > +  @retval EFI_SUCCESS           The watchdog timer handler
> was
> > > > > >registered.
> > > > > >> > > > +  @retval EFI_ALREADY_STARTED   NotifyFunction is not
> NULL, and a
> > > > > >> > handler is already
> > > > > >> > > > +                                registered.
> > > > > >> > > > +  @retval EFI_INVALID_PARAMETER NotifyFunction is NULL,
> and a
> > > > > >handler
> > > > > >> > was not
> > > > > >> > > > +                                previously registered.
> > > > > >> > > > +
> > > > > >> > > > +**/
> > > > > >> > > > +STATIC
> > > > > >> > > > +EFI_STATUS
> > > > > >> > > > +EFIAPI
> > > > > >> > > > +WdogRegisterHandler (
> > > > > >> > > > +  IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL   *This,
> > > > > >> > > > +  IN EFI_WATCHDOG_TIMER_NOTIFY          NotifyFunction
> > > > > >> > > > +  )
> > > > > >> > > > +{
> > > > > >> > > > +  // ERROR: This function is not supported.
> > > > > >> > > > +  // The hardware watchdog will reset the board
> > > > > >> > > > +  return EFI_INVALID_PARAMETER;
> > > > > >> > >
> > > > > >> > > Michael, Liming - what's your take on this?
> > > > > >> > >
> > > > > >> > > Is EFI_WATCHDOG_TIMER_ARCH_PROTOCOL suitable for use
> with a
> > > > > >pure-hw
> > > > > >> > > watchdog such as this?
> > > > > >> > >
> > > > > >> > > If so, what would be a suitable return code here?
> > > > > >> > > EFI_INVALID_PARAMETER does not look ideal.
> > > > > >> > >
> > > > > >> > > /
> > > > > >> > >     Leif
> > _______________________________________________
> > edk2-devel mailing list
> > edk2-devel@lists.01.org
> >
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^ permalink raw reply	[flat|nested] 25+ messages in thread

end of thread, other threads:[~2017-12-14  3:33 UTC | newest]

Thread overview: 25+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-11-27 10:51 [PATCH edk2-platforms] [PATCH v3 0/9] Platform/NXP Meenakshi Aggarwal
2017-11-27 10:51 ` [PATCH edk2-platforms] [PATCH v3 1/9] Platform/NXP: Add support for Big Endian Mmio APIs Meenakshi Aggarwal
2017-11-27 10:51 ` [PATCH edk2-platforms] [PATCH v3 2/9] Platform/NXP : Add support for Watchdog driver Meenakshi Aggarwal
2017-12-04 14:35   ` Leif Lindholm
2017-12-04 15:23     ` Gao, Liming
2017-12-05  5:07       ` Udit Kumar
2017-12-05 11:06         ` Leif Lindholm
2017-12-07  3:35           ` Meenakshi Aggarwal
2017-12-07  7:11           ` Gao, Liming
2017-12-07 11:03             ` Leif Lindholm
2017-12-07 14:54               ` Gao, Liming
2017-12-07 15:34                 ` Leif Lindholm
2017-12-08  4:41                   ` Udit Kumar
2017-12-10 13:30                   ` Gao, Liming
2017-12-14  3:37                     ` Meenakshi Aggarwal
2017-12-07 11:15             ` Udit Kumar
2017-12-07 14:51               ` Gao, Liming
2017-11-27 10:51 ` [PATCH edk2-platforms] [PATCH v3 3/9] SocLib : Add support for initialization of peripherals Meenakshi Aggarwal
2017-11-27 10:51 ` [PATCH edk2-platforms] [PATCH v3 4/9] Platform/NXP : Add support for DUART library Meenakshi Aggarwal
2017-11-27 10:51 ` [PATCH edk2-platforms] [PATCH v3 5/9] Platform/NXP: Add support for I2c driver Meenakshi Aggarwal
2017-11-27 10:51 ` [PATCH edk2-platforms] [PATCH v3 6/9] Silicon/Maxim : Add support for DS1307 RTC library Meenakshi Aggarwal
2017-11-27 10:51 ` [PATCH edk2-platforms] [PATCH v3 7/9] Platform/NXP: Add support for ArmPlatformLib Meenakshi Aggarwal
2017-11-27 10:51 ` [PATCH edk2-platforms] [PATCH v3 8/9] Compilation : Add the fdf, dsc and dec files Meenakshi Aggarwal
2017-11-27 10:51 ` [PATCH edk2-platforms] [PATCH v3 9/9] Build : Add build script and environment script Meenakshi Aggarwal
2017-11-27 12:05 ` [PATCH edk2-platforms] [PATCH v3 0/9] Platform/NXP Leif Lindholm

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