[platforms: PATCH 4/5] Marvell/Drivers: Rename SPI master driver

[Marcin Wojtas <mw@semihalf.com>]

Hitherto driver name was very generic. In order to be ready
for adding new SPI master drivers, use the controller's
traditional name (it's called SPI Orion in linux and
U-Boot) for files and the entry point.

Additionally, move the files to new 'Controllers' directory,
which is paralel to existing 'Devices' and 'Variables', so
that to make the separation more clear.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
 Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf            |   2 +-
 Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc             |   2 +-
 Silicon/Marvell/Drivers/Spi/Controllers/MvSpiOrionDxe.c   | 432 ++++++++++++++++++++
 Silicon/Marvell/Drivers/Spi/Controllers/MvSpiOrionDxe.h   | 148 +++++++
 Silicon/Marvell/Drivers/Spi/Controllers/MvSpiOrionDxe.inf |  73 ++++
 Silicon/Marvell/Drivers/Spi/MvSpiDxe.c                    | 432 --------------------
 Silicon/Marvell/Drivers/Spi/MvSpiDxe.h                    | 148 -------
 Silicon/Marvell/Drivers/Spi/MvSpiDxe.inf                  |  73 ----
 8 files changed, 655 insertions(+), 655 deletions(-)

diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf b/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf
index 3b0646e..6d57b9a 100644
--- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf
+++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf
@@ -110,7 +110,7 @@ FvNameGuid         = 5eda4200-2c5f-43cb-9da3-0baf74b1b30c
   INF Silicon/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf
   INF MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf
   INF Silicon/Marvell/Drivers/I2c/Devices/MvEeprom/MvEeprom.inf
-  INF Silicon/Marvell/Drivers/Spi/MvSpiDxe.inf
+  INF Silicon/Marvell/Drivers/Spi/Controllers/MvSpiOrionDxe.inf
   INF Silicon/Marvell/Drivers/Spi/Devices/MvSpiFlash.inf
   INF Silicon/Marvell/Armada7k8k/Drivers/Armada7k8kRngDxe/Armada7k8kRngDxe.inf
 
diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
index 7d87766..0eb3ef3 100644
--- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
+++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
@@ -411,7 +411,7 @@
   Silicon/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf
   MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf
   Silicon/Marvell/Drivers/I2c/Devices/MvEeprom/MvEeprom.inf
-  Silicon/Marvell/Drivers/Spi/MvSpiDxe.inf
+  Silicon/Marvell/Drivers/Spi/Controllers/MvSpiOrionDxe.inf
   Silicon/Marvell/Drivers/Spi/Devices/MvSpiFlash.inf
   Silicon/Marvell/Armada7k8k/Drivers/Armada7k8kRngDxe/Armada7k8kRngDxe.inf
 
diff --git a/Silicon/Marvell/Drivers/Spi/Controllers/MvSpiOrionDxe.c b/Silicon/Marvell/Drivers/Spi/Controllers/MvSpiOrionDxe.c
new file mode 100755
index 0000000..c657daf
--- /dev/null
+++ b/Silicon/Marvell/Drivers/Spi/Controllers/MvSpiOrionDxe.c
@@ -0,0 +1,432 @@
+/*******************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice,
+  this list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in the
+  documentation and/or other materials provided with the distribution.
+
+* Neither the name of Marvell nor the names of its contributors may be
+  used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+#include "MvSpiOrionDxe.h"
+
+SPI_MASTER *mSpiMasterInstance;
+
+STATIC
+EFI_STATUS
+SpiSetBaudRate (
+  IN SPI_DEVICE *Slave,
+  IN UINT32 CpuClock,
+  IN UINT32 MaxFreq
+  )
+{
+  UINT32 Spr, BestSpr, Sppr, BestSppr, ClockDivider, Match, Reg, MinBaudDiff;
+  UINTN SpiRegBase = Slave->HostRegisterBaseAddress;
+
+  MinBaudDiff = 0xFFFFFFFF;
+  BestSppr = 0;
+
+  //Spr is in range 1-15 and Sppr in range 0-8
+  for (Spr = 1; Spr <= 15; Spr++) {
+    for (Sppr = 0; Sppr <= 7; Sppr++) {
+      ClockDivider = Spr * (1 << Sppr);
+
+      if ((CpuClock / ClockDivider) > MaxFreq) {
+        continue;
+      }
+
+      if ((CpuClock / ClockDivider) == MaxFreq) {
+        BestSpr = Spr;
+        BestSppr = Sppr;
+        Match = 1;
+        break;
+        }
+
+      if ((MaxFreq - (CpuClock / ClockDivider)) < MinBaudDiff) {
+        MinBaudDiff = (MaxFreq - (CpuClock / ClockDivider));
+        BestSpr = Spr;
+        BestSppr = Sppr;
+      }
+    }
+
+    if (Match == 1) {
+      break;
+    }
+  }
+
+  if (BestSpr == 0) {
+    return (EFI_INVALID_PARAMETER);
+  }
+
+  Reg = MmioRead32 (SpiRegBase + SPI_CONF_REG);
+  Reg &= ~(SPI_SPR_MASK | SPI_SPPR_0_MASK | SPI_SPPR_HI_MASK);
+  Reg |= (BestSpr << SPI_SPR_OFFSET) |
+         ((BestSppr & 0x1) << SPI_SPPR_0_OFFSET) |
+         ((BestSppr >> 1) << SPI_SPPR_HI_OFFSET);
+  MmioWrite32 (SpiRegBase + SPI_CONF_REG, Reg);
+
+  return EFI_SUCCESS;
+}
+
+STATIC
+VOID
+SpiSetCs (
+  IN SPI_DEVICE *Slave
+  )
+{
+  UINT32 Reg;
+  UINTN  SpiRegBase = Slave->HostRegisterBaseAddress;
+
+  Reg = MmioRead32 (SpiRegBase + SPI_CTRL_REG);
+  Reg &= ~SPI_CS_NUM_MASK;
+  Reg |= (Slave->Cs << SPI_CS_NUM_OFFSET);
+  MmioWrite32 (SpiRegBase + SPI_CTRL_REG, Reg);
+}
+
+STATIC
+VOID
+SpiActivateCs (
+  IN SPI_DEVICE *Slave
+  )
+{
+  UINT32 Reg;
+  UINTN  SpiRegBase = Slave->HostRegisterBaseAddress;
+
+  SpiSetCs(Slave);
+  Reg = MmioRead32 (SpiRegBase + SPI_CTRL_REG);
+  Reg |= SPI_CS_EN_MASK;
+  MmioWrite32(SpiRegBase + SPI_CTRL_REG, Reg);
+}
+
+STATIC
+VOID
+SpiDeactivateCs (
+  IN SPI_DEVICE *Slave
+  )
+{
+  UINT32 Reg;
+  UINTN  SpiRegBase = Slave->HostRegisterBaseAddress;
+
+  Reg = MmioRead32 (SpiRegBase + SPI_CTRL_REG);
+  Reg &= ~SPI_CS_EN_MASK;
+  MmioWrite32(SpiRegBase + SPI_CTRL_REG, Reg);
+}
+
+STATIC
+VOID
+SpiSetupTransfer (
+  IN MARVELL_SPI_MASTER_PROTOCOL *This,
+  IN SPI_DEVICE *Slave
+  )
+{
+  SPI_MASTER *SpiMaster;
+  UINT32 Reg, CoreClock, SpiMaxFreq;
+  UINTN SpiRegBase;
+
+  SpiMaster = SPI_MASTER_FROM_SPI_MASTER_PROTOCOL (This);
+
+  // Initialize values from PCDs
+  SpiRegBase  = Slave->HostRegisterBaseAddress;
+  CoreClock   = Slave->CoreClock;
+  SpiMaxFreq  = Slave->MaxFreq;
+
+  EfiAcquireLock (&SpiMaster->Lock);
+
+  Reg = MmioRead32 (SpiRegBase + SPI_CONF_REG);
+  Reg |= SPI_BYTE_LENGTH;
+  MmioWrite32 (SpiRegBase + SPI_CONF_REG, Reg);
+
+  SpiSetCs(Slave);
+
+  SpiSetBaudRate (Slave, CoreClock, SpiMaxFreq);
+
+  Reg = MmioRead32 (SpiRegBase + SPI_CONF_REG);
+  Reg &= ~(SPI_CPOL_MASK | SPI_CPHA_MASK | SPI_TXLSBF_MASK | SPI_RXLSBF_MASK);
+
+  switch (Slave->Mode) {
+  case SPI_MODE0:
+    break;
+  case SPI_MODE1:
+    Reg |= SPI_CPHA_MASK;
+    break;
+  case SPI_MODE2:
+    Reg |= SPI_CPOL_MASK;
+    break;
+  case SPI_MODE3:
+    Reg |= SPI_CPOL_MASK;
+    Reg |= SPI_CPHA_MASK;
+    break;
+  }
+
+  MmioWrite32 (SpiRegBase + SPI_CONF_REG, Reg);
+
+  EfiReleaseLock (&SpiMaster->Lock);
+}
+
+EFI_STATUS
+EFIAPI
+MvSpiTransfer (
+  IN MARVELL_SPI_MASTER_PROTOCOL *This,
+  IN SPI_DEVICE *Slave,
+  IN UINTN DataByteCount,
+  IN VOID *DataOut,
+  IN VOID *DataIn,
+  IN UINTN Flag
+  )
+{
+  SPI_MASTER *SpiMaster;
+  UINT64  Length;
+  UINT32  Iterator, Reg;
+  UINT8   *DataOutPtr = (UINT8 *)DataOut;
+  UINT8   *DataInPtr  = (UINT8 *)DataIn;
+  UINT8   DataToSend  = 0;
+  UINTN   SpiRegBase;
+
+  SpiMaster = SPI_MASTER_FROM_SPI_MASTER_PROTOCOL (This);
+
+  SpiRegBase = Slave->HostRegisterBaseAddress;
+
+  Length = 8 * DataByteCount;
+
+  if (!EfiAtRuntime ()) {
+    EfiAcquireLock (&SpiMaster->Lock);
+  }
+
+  if (Flag & SPI_TRANSFER_BEGIN) {
+    SpiActivateCs (Slave);
+  }
+
+  // Set 8-bit mode
+  Reg = MmioRead32 (SpiRegBase + SPI_CONF_REG);
+  Reg &= ~SPI_BYTE_LENGTH;
+  MmioWrite32 (SpiRegBase + SPI_CONF_REG, Reg);
+
+  while (Length > 0) {
+    if (DataOut != NULL) {
+      DataToSend = *DataOutPtr & 0xFF;
+    }
+    // Transmit Data
+    MmioWrite32 (SpiRegBase + SPI_INT_CAUSE_REG, 0x0);
+    MmioWrite32 (SpiRegBase + SPI_DATA_OUT_REG, DataToSend);
+    // Wait for memory ready
+    for (Iterator = 0; Iterator < SPI_TIMEOUT; Iterator++) {
+      if (MmioRead32 (SpiRegBase + SPI_INT_CAUSE_REG)) {
+        if (DataInPtr != NULL) {
+          *DataInPtr = MmioRead32 (SpiRegBase + SPI_DATA_IN_REG);
+          DataInPtr++;
+        }
+        if (DataOutPtr != NULL) {
+          DataOutPtr++;
+        }
+        Length -= 8;
+        break;
+      }
+    }
+
+    if (Iterator >= SPI_TIMEOUT) {
+      DEBUG ((DEBUG_ERROR, "%a: Timeout\n", __FUNCTION__));
+      return EFI_TIMEOUT;
+    }
+  }
+
+  if (Flag & SPI_TRANSFER_END) {
+    SpiDeactivateCs (Slave);
+  }
+
+  if (!EfiAtRuntime ()) {
+    EfiReleaseLock (&SpiMaster->Lock);
+  }
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+MvSpiReadWrite (
+  IN  MARVELL_SPI_MASTER_PROTOCOL *This,
+  IN  SPI_DEVICE *Slave,
+  IN  UINT8 *Cmd,
+  IN  UINTN CmdSize,
+  IN  UINT8 *DataOut,
+  OUT UINT8 *DataIn,
+  IN  UINTN DataSize
+  )
+{
+  EFI_STATUS Status;
+
+  Status = MvSpiTransfer (This, Slave, CmdSize, Cmd, NULL, SPI_TRANSFER_BEGIN);
+  if (EFI_ERROR (Status)) {
+    Print (L"Spi Transfer Error\n");
+    return EFI_DEVICE_ERROR;
+  }
+
+  Status = MvSpiTransfer (This, Slave, DataSize, DataOut, DataIn, SPI_TRANSFER_END);
+  if (EFI_ERROR (Status)) {
+    Print (L"Spi Transfer Error\n");
+    return EFI_DEVICE_ERROR;
+  }
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+MvSpiInit (
+  IN MARVELL_SPI_MASTER_PROTOCOL * This
+  )
+{
+
+  return EFI_SUCCESS;
+}
+
+SPI_DEVICE *
+EFIAPI
+MvSpiSetupSlave (
+  IN MARVELL_SPI_MASTER_PROTOCOL *This,
+  IN SPI_DEVICE *Slave,
+  IN UINTN Cs,
+  IN SPI_MODE Mode
+  )
+{
+  if (!Slave) {
+    Slave = AllocateZeroPool (sizeof(SPI_DEVICE));
+    if (Slave == NULL) {
+      DEBUG((DEBUG_ERROR, "Cannot allocate memory\n"));
+      return NULL;
+    }
+
+    Slave->Cs   = Cs;
+    Slave->Mode = Mode;
+  }
+
+  Slave->HostRegisterBaseAddress = PcdGet32 (PcdSpiRegBase);
+  Slave->CoreClock = PcdGet32 (PcdSpiClockFrequency);
+  Slave->MaxFreq = PcdGet32 (PcdSpiMaxFrequency);
+
+  SpiSetupTransfer (This, Slave);
+
+  return Slave;
+}
+
+EFI_STATUS
+EFIAPI
+MvSpiFreeSlave (
+  IN SPI_DEVICE *Slave
+  )
+{
+  FreePool (Slave);
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+MvSpiConfigRuntime (
+  IN SPI_DEVICE *Slave
+  )
+{
+  EFI_STATUS Status;
+  UINTN AlignedAddress;
+
+  //
+  // Host register base may be not aligned to the page size,
+  // which is not accepted when setting memory space attributes.
+  // Add one aligned page of memory space which covers the host
+  // controller registers.
+  //
+  AlignedAddress = Slave->HostRegisterBaseAddress & ~(SIZE_4KB - 1);
+
+  Status = gDS->AddMemorySpace (EfiGcdMemoryTypeMemoryMappedIo,
+                  AlignedAddress,
+                  SIZE_4KB,
+                  EFI_MEMORY_UC | EFI_MEMORY_RUNTIME);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "%a: Failed to add memory space\n", __FUNCTION__));
+    return Status;
+  }
+
+  Status = gDS->SetMemorySpaceAttributes (AlignedAddress,
+                  SIZE_4KB,
+                  EFI_MEMORY_UC | EFI_MEMORY_RUNTIME);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "%a: Failed to set memory attributes\n", __FUNCTION__));
+    gDS->RemoveMemorySpace (AlignedAddress, SIZE_4KB);
+    return Status;
+  }
+
+  return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+SpiMasterInitProtocol (
+  IN MARVELL_SPI_MASTER_PROTOCOL *SpiMasterProtocol
+  )
+{
+
+  SpiMasterProtocol->Init        = MvSpiInit;
+  SpiMasterProtocol->SetupDevice = MvSpiSetupSlave;
+  SpiMasterProtocol->FreeDevice  = MvSpiFreeSlave;
+  SpiMasterProtocol->Transfer    = MvSpiTransfer;
+  SpiMasterProtocol->ReadWrite   = MvSpiReadWrite;
+  SpiMasterProtocol->ConfigRuntime = MvSpiConfigRuntime;
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+SpiOrionEntryPoint (
+  IN EFI_HANDLE       ImageHandle,
+  IN EFI_SYSTEM_TABLE *SystemTable
+  )
+{
+  EFI_STATUS  Status;
+
+  mSpiMasterInstance = AllocateRuntimeZeroPool (sizeof (SPI_MASTER));
+  if (mSpiMasterInstance == NULL) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  EfiInitializeLock (&mSpiMasterInstance->Lock, TPL_NOTIFY);
+
+  SpiMasterInitProtocol (&mSpiMasterInstance->SpiMasterProtocol);
+
+  mSpiMasterInstance->Signature = SPI_MASTER_SIGNATURE;
+
+  Status = gBS->InstallMultipleProtocolInterfaces (
+                  &(mSpiMasterInstance->Handle),
+                  &gMarvellSpiMasterProtocolGuid,
+                  &(mSpiMasterInstance->SpiMasterProtocol),
+                  NULL
+                  );
+  if (EFI_ERROR (Status)) {
+    FreePool (mSpiMasterInstance);
+    return EFI_DEVICE_ERROR;
+  }
+
+  return EFI_SUCCESS;
+}
diff --git a/Silicon/Marvell/Drivers/Spi/Controllers/MvSpiOrionDxe.h b/Silicon/Marvell/Drivers/Spi/Controllers/MvSpiOrionDxe.h
new file mode 100644
index 0000000..50cdc02
--- /dev/null
+++ b/Silicon/Marvell/Drivers/Spi/Controllers/MvSpiOrionDxe.h
@@ -0,0 +1,148 @@
+/*******************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice,
+  this list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in the
+  documentation and/or other materials provided with the distribution.
+
+* Neither the name of Marvell nor the names of its contributors may be
+  used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+#ifndef __SPI_MASTER_H__
+#define __SPI_MASTER_H__
+
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeLib.h>
+
+#include <Protocol/Spi.h>
+
+#define SPI_MASTER_SIGNATURE                      SIGNATURE_32 ('M', 'S', 'P', 'I')
+#define SPI_MASTER_FROM_SPI_MASTER_PROTOCOL(a)  CR (a, SPI_MASTER, SpiMasterProtocol, SPI_MASTER_SIGNATURE)
+
+// Marvell Flash Device Controller Registers
+#define SPI_CTRL_REG                    (0x00)
+#define SPI_CONF_REG                    (0x04)
+#define SPI_DATA_OUT_REG                (0x08)
+#define SPI_DATA_IN_REG                 (0x0c)
+#define SPI_INT_CAUSE_REG               (0x10)
+
+// Serial Memory Interface Control Register Masks
+#define SPI_CS_NUM_OFFSET               2
+#define SPI_CS_NUM_MASK                 (0x7 << SPI_CS_NUM_OFFSET)
+#define SPI_MEM_READY_MASK              (0x1 << 1)
+#define SPI_CS_EN_MASK                  (0x1 << 0)
+
+// Serial Memory Interface Configuration Register Masks
+#define SPI_BYTE_LENGTH_OFFSET          5
+#define SPI_BYTE_LENGTH                 (0x1  << SPI_BYTE_LENGTH_OFFSET)
+#define SPI_CPOL_OFFSET                 11
+#define SPI_CPOL_MASK                   (0x1 << SPI_CPOL_OFFSET)
+#define SPI_CPHA_OFFSET                 12
+#define SPI_CPHA_MASK                  (0x1 << SPI_CPHA_OFFSET)
+#define SPI_TXLSBF_OFFSET               13
+#define SPI_TXLSBF_MASK                 (0x1 << SPI_TXLSBF_OFFSET)
+#define SPI_RXLSBF_OFFSET               14
+#define SPI_RXLSBF_MASK                 (0x1 << SPI_RXLSBF_OFFSET)
+
+#define SPI_SPR_OFFSET                  0
+#define SPI_SPR_MASK                    (0xf << SPI_SPR_OFFSET)
+#define SPI_SPPR_0_OFFSET               4
+#define SPI_SPPR_0_MASK                 (0x1 << SPI_SPPR_0_OFFSET)
+#define SPI_SPPR_HI_OFFSET              6
+#define SPI_SPPR_HI_MASK                (0x3 << SPI_SPPR_HI_OFFSET)
+
+#define SPI_TRANSFER_BEGIN              0x01  // Assert CS before transfer
+#define SPI_TRANSFER_END                0x02  // Deassert CS after transfers
+
+#define SPI_TIMEOUT                     100000
+
+typedef struct {
+  MARVELL_SPI_MASTER_PROTOCOL SpiMasterProtocol;
+  UINTN                   Signature;
+  EFI_HANDLE              Handle;
+  EFI_LOCK                Lock;
+} SPI_MASTER;
+
+EFI_STATUS
+EFIAPI
+MvSpiTransfer (
+  IN MARVELL_SPI_MASTER_PROTOCOL *This,
+  IN SPI_DEVICE *Slave,
+  IN UINTN DataByteCount,
+  IN VOID *DataOut,
+  IN VOID *DataIn,
+  IN UINTN Flag
+  );
+
+EFI_STATUS
+EFIAPI
+MvSpiReadWrite (
+  IN  MARVELL_SPI_MASTER_PROTOCOL *This,
+  IN  SPI_DEVICE *Slave,
+  IN  UINT8 *Cmd,
+  IN  UINTN CmdSize,
+  IN  UINT8 *DataOut,
+  OUT UINT8 *DataIn,
+  IN  UINTN DataSize
+  );
+
+EFI_STATUS
+EFIAPI
+MvSpiInit (
+  IN MARVELL_SPI_MASTER_PROTOCOL     * This
+  );
+
+SPI_DEVICE *
+EFIAPI
+MvSpiSetupSlave (
+  IN MARVELL_SPI_MASTER_PROTOCOL     * This,
+  IN SPI_DEVICE *Slave,
+  IN UINTN Cs,
+  IN SPI_MODE Mode
+  );
+
+EFI_STATUS
+EFIAPI
+MvSpiFreeSlave (
+  IN SPI_DEVICE *Slave
+  );
+
+EFI_STATUS
+EFIAPI
+SpiMasterEntryPoint (
+  IN EFI_HANDLE       ImageHandle,
+  IN EFI_SYSTEM_TABLE *SystemTable
+  );
+
+#endif // __SPI_MASTER_H__
diff --git a/Silicon/Marvell/Drivers/Spi/Controllers/MvSpiOrionDxe.inf b/Silicon/Marvell/Drivers/Spi/Controllers/MvSpiOrionDxe.inf
new file mode 100644
index 0000000..3f85b40
--- /dev/null
+++ b/Silicon/Marvell/Drivers/Spi/Controllers/MvSpiOrionDxe.inf
@@ -0,0 +1,73 @@
+#
+# Marvell BSD License Option
+#
+# If you received this File from Marvell, you may opt to use, redistribute
+# and/or modify this File under the following licensing terms.
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Marvell nor the names of its contributors may be
+# used to endorse or promote products derived from this software without
+# specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = SpiOrionDxe
+  FILE_GUID                      = c19dbc8a-f4f9-43b0-aee5-802e3ed03d15
+  MODULE_TYPE                    = DXE_RUNTIME_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = SpiOrionEntryPoint
+
+[Sources]
+  MvSpiOrionDxe.c
+  MvSpiOrionDxe.h
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/Marvell/Marvell.dec
+
+[LibraryClasses]
+  NorFlashInfoLib
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  TimerLib
+  UefiLib
+  DebugLib
+  DxeServicesTableLib
+  MemoryAllocationLib
+  IoLib
+  UefiRuntimeLib
+
+[FixedPcd]
+  gMarvellTokenSpaceGuid.PcdSpiRegBase
+  gMarvellTokenSpaceGuid.PcdSpiClockFrequency
+  gMarvellTokenSpaceGuid.PcdSpiMaxFrequency
+
+[Protocols]
+  gMarvellSpiMasterProtocolGuid
+
+[Depex]
+  #
+  # MvSpiDxe must be loaded prior to MvSpiFlash driver
+  #
+  BEFORE gMarvellSpiFlashDxeGuid
diff --git a/Silicon/Marvell/Drivers/Spi/MvSpiDxe.c b/Silicon/Marvell/Drivers/Spi/MvSpiDxe.c
deleted file mode 100755
index bab6cf4..0000000
--- a/Silicon/Marvell/Drivers/Spi/MvSpiDxe.c
+++ /dev/null
@@ -1,432 +0,0 @@
-/*******************************************************************************
-Copyright (C) 2016 Marvell International Ltd.
-
-Marvell BSD License Option
-
-If you received this File from Marvell, you may opt to use, redistribute and/or
-modify this File under the following licensing terms.
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice,
-  this list of conditions and the following disclaimer.
-
-* Redistributions in binary form must reproduce the above copyright
-  notice, this list of conditions and the following disclaimer in the
-  documentation and/or other materials provided with the distribution.
-
-* Neither the name of Marvell nor the names of its contributors may be
-  used to endorse or promote products derived from this software without
-  specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-#include "MvSpiDxe.h"
-
-SPI_MASTER *mSpiMasterInstance;
-
-STATIC
-EFI_STATUS
-SpiSetBaudRate (
-  IN SPI_DEVICE *Slave,
-  IN UINT32 CpuClock,
-  IN UINT32 MaxFreq
-  )
-{
-  UINT32 Spr, BestSpr, Sppr, BestSppr, ClockDivider, Match, Reg, MinBaudDiff;
-  UINTN SpiRegBase = Slave->HostRegisterBaseAddress;
-
-  MinBaudDiff = 0xFFFFFFFF;
-  BestSppr = 0;
-
-  //Spr is in range 1-15 and Sppr in range 0-8
-  for (Spr = 1; Spr <= 15; Spr++) {
-    for (Sppr = 0; Sppr <= 7; Sppr++) {
-      ClockDivider = Spr * (1 << Sppr);
-
-      if ((CpuClock / ClockDivider) > MaxFreq) {
-        continue;
-      }
-
-      if ((CpuClock / ClockDivider) == MaxFreq) {
-        BestSpr = Spr;
-        BestSppr = Sppr;
-        Match = 1;
-        break;
-        }
-
-      if ((MaxFreq - (CpuClock / ClockDivider)) < MinBaudDiff) {
-        MinBaudDiff = (MaxFreq - (CpuClock / ClockDivider));
-        BestSpr = Spr;
-        BestSppr = Sppr;
-      }
-    }
-
-    if (Match == 1) {
-      break;
-    }
-  }
-
-  if (BestSpr == 0) {
-    return (EFI_INVALID_PARAMETER);
-  }
-
-  Reg = MmioRead32 (SpiRegBase + SPI_CONF_REG);
-  Reg &= ~(SPI_SPR_MASK | SPI_SPPR_0_MASK | SPI_SPPR_HI_MASK);
-  Reg |= (BestSpr << SPI_SPR_OFFSET) |
-         ((BestSppr & 0x1) << SPI_SPPR_0_OFFSET) |
-         ((BestSppr >> 1) << SPI_SPPR_HI_OFFSET);
-  MmioWrite32 (SpiRegBase + SPI_CONF_REG, Reg);
-
-  return EFI_SUCCESS;
-}
-
-STATIC
-VOID
-SpiSetCs (
-  IN SPI_DEVICE *Slave
-  )
-{
-  UINT32 Reg;
-  UINTN  SpiRegBase = Slave->HostRegisterBaseAddress;
-
-  Reg = MmioRead32 (SpiRegBase + SPI_CTRL_REG);
-  Reg &= ~SPI_CS_NUM_MASK;
-  Reg |= (Slave->Cs << SPI_CS_NUM_OFFSET);
-  MmioWrite32 (SpiRegBase + SPI_CTRL_REG, Reg);
-}
-
-STATIC
-VOID
-SpiActivateCs (
-  IN SPI_DEVICE *Slave
-  )
-{
-  UINT32 Reg;
-  UINTN  SpiRegBase = Slave->HostRegisterBaseAddress;
-
-  SpiSetCs(Slave);
-  Reg = MmioRead32 (SpiRegBase + SPI_CTRL_REG);
-  Reg |= SPI_CS_EN_MASK;
-  MmioWrite32(SpiRegBase + SPI_CTRL_REG, Reg);
-}
-
-STATIC
-VOID
-SpiDeactivateCs (
-  IN SPI_DEVICE *Slave
-  )
-{
-  UINT32 Reg;
-  UINTN  SpiRegBase = Slave->HostRegisterBaseAddress;
-
-  Reg = MmioRead32 (SpiRegBase + SPI_CTRL_REG);
-  Reg &= ~SPI_CS_EN_MASK;
-  MmioWrite32(SpiRegBase + SPI_CTRL_REG, Reg);
-}
-
-STATIC
-VOID
-SpiSetupTransfer (
-  IN MARVELL_SPI_MASTER_PROTOCOL *This,
-  IN SPI_DEVICE *Slave
-  )
-{
-  SPI_MASTER *SpiMaster;
-  UINT32 Reg, CoreClock, SpiMaxFreq;
-  UINTN SpiRegBase;
-
-  SpiMaster = SPI_MASTER_FROM_SPI_MASTER_PROTOCOL (This);
-
-  // Initialize values from PCDs
-  SpiRegBase  = Slave->HostRegisterBaseAddress;
-  CoreClock   = Slave->CoreClock;
-  SpiMaxFreq  = Slave->MaxFreq;
-
-  EfiAcquireLock (&SpiMaster->Lock);
-
-  Reg = MmioRead32 (SpiRegBase + SPI_CONF_REG);
-  Reg |= SPI_BYTE_LENGTH;
-  MmioWrite32 (SpiRegBase + SPI_CONF_REG, Reg);
-
-  SpiSetCs(Slave);
-
-  SpiSetBaudRate (Slave, CoreClock, SpiMaxFreq);
-
-  Reg = MmioRead32 (SpiRegBase + SPI_CONF_REG);
-  Reg &= ~(SPI_CPOL_MASK | SPI_CPHA_MASK | SPI_TXLSBF_MASK | SPI_RXLSBF_MASK);
-
-  switch (Slave->Mode) {
-  case SPI_MODE0:
-    break;
-  case SPI_MODE1:
-    Reg |= SPI_CPHA_MASK;
-    break;
-  case SPI_MODE2:
-    Reg |= SPI_CPOL_MASK;
-    break;
-  case SPI_MODE3:
-    Reg |= SPI_CPOL_MASK;
-    Reg |= SPI_CPHA_MASK;
-    break;
-  }
-
-  MmioWrite32 (SpiRegBase + SPI_CONF_REG, Reg);
-
-  EfiReleaseLock (&SpiMaster->Lock);
-}
-
-EFI_STATUS
-EFIAPI
-MvSpiTransfer (
-  IN MARVELL_SPI_MASTER_PROTOCOL *This,
-  IN SPI_DEVICE *Slave,
-  IN UINTN DataByteCount,
-  IN VOID *DataOut,
-  IN VOID *DataIn,
-  IN UINTN Flag
-  )
-{
-  SPI_MASTER *SpiMaster;
-  UINT64  Length;
-  UINT32  Iterator, Reg;
-  UINT8   *DataOutPtr = (UINT8 *)DataOut;
-  UINT8   *DataInPtr  = (UINT8 *)DataIn;
-  UINT8   DataToSend  = 0;
-  UINTN   SpiRegBase;
-
-  SpiMaster = SPI_MASTER_FROM_SPI_MASTER_PROTOCOL (This);
-
-  SpiRegBase = Slave->HostRegisterBaseAddress;
-
-  Length = 8 * DataByteCount;
-
-  if (!EfiAtRuntime ()) {
-    EfiAcquireLock (&SpiMaster->Lock);
-  }
-
-  if (Flag & SPI_TRANSFER_BEGIN) {
-    SpiActivateCs (Slave);
-  }
-
-  // Set 8-bit mode
-  Reg = MmioRead32 (SpiRegBase + SPI_CONF_REG);
-  Reg &= ~SPI_BYTE_LENGTH;
-  MmioWrite32 (SpiRegBase + SPI_CONF_REG, Reg);
-
-  while (Length > 0) {
-    if (DataOut != NULL) {
-      DataToSend = *DataOutPtr & 0xFF;
-    }
-    // Transmit Data
-    MmioWrite32 (SpiRegBase + SPI_INT_CAUSE_REG, 0x0);
-    MmioWrite32 (SpiRegBase + SPI_DATA_OUT_REG, DataToSend);
-    // Wait for memory ready
-    for (Iterator = 0; Iterator < SPI_TIMEOUT; Iterator++) {
-      if (MmioRead32 (SpiRegBase + SPI_INT_CAUSE_REG)) {
-        if (DataInPtr != NULL) {
-          *DataInPtr = MmioRead32 (SpiRegBase + SPI_DATA_IN_REG);
-          DataInPtr++;
-        }
-        if (DataOutPtr != NULL) {
-          DataOutPtr++;
-        }
-        Length -= 8;
-        break;
-      }
-    }
-
-    if (Iterator >= SPI_TIMEOUT) {
-      DEBUG ((DEBUG_ERROR, "%a: Timeout\n", __FUNCTION__));
-      return EFI_TIMEOUT;
-    }
-  }
-
-  if (Flag & SPI_TRANSFER_END) {
-    SpiDeactivateCs (Slave);
-  }
-
-  if (!EfiAtRuntime ()) {
-    EfiReleaseLock (&SpiMaster->Lock);
-  }
-
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-EFIAPI
-MvSpiReadWrite (
-  IN  MARVELL_SPI_MASTER_PROTOCOL *This,
-  IN  SPI_DEVICE *Slave,
-  IN  UINT8 *Cmd,
-  IN  UINTN CmdSize,
-  IN  UINT8 *DataOut,
-  OUT UINT8 *DataIn,
-  IN  UINTN DataSize
-  )
-{
-  EFI_STATUS Status;
-
-  Status = MvSpiTransfer (This, Slave, CmdSize, Cmd, NULL, SPI_TRANSFER_BEGIN);
-  if (EFI_ERROR (Status)) {
-    Print (L"Spi Transfer Error\n");
-    return EFI_DEVICE_ERROR;
-  }
-
-  Status = MvSpiTransfer (This, Slave, DataSize, DataOut, DataIn, SPI_TRANSFER_END);
-  if (EFI_ERROR (Status)) {
-    Print (L"Spi Transfer Error\n");
-    return EFI_DEVICE_ERROR;
-  }
-
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-EFIAPI
-MvSpiInit (
-  IN MARVELL_SPI_MASTER_PROTOCOL * This
-  )
-{
-
-  return EFI_SUCCESS;
-}
-
-SPI_DEVICE *
-EFIAPI
-MvSpiSetupSlave (
-  IN MARVELL_SPI_MASTER_PROTOCOL *This,
-  IN SPI_DEVICE *Slave,
-  IN UINTN Cs,
-  IN SPI_MODE Mode
-  )
-{
-  if (!Slave) {
-    Slave = AllocateZeroPool (sizeof(SPI_DEVICE));
-    if (Slave == NULL) {
-      DEBUG((DEBUG_ERROR, "Cannot allocate memory\n"));
-      return NULL;
-    }
-
-    Slave->Cs   = Cs;
-    Slave->Mode = Mode;
-  }
-
-  Slave->HostRegisterBaseAddress = PcdGet32 (PcdSpiRegBase);
-  Slave->CoreClock = PcdGet32 (PcdSpiClockFrequency);
-  Slave->MaxFreq = PcdGet32 (PcdSpiMaxFrequency);
-
-  SpiSetupTransfer (This, Slave);
-
-  return Slave;
-}
-
-EFI_STATUS
-EFIAPI
-MvSpiFreeSlave (
-  IN SPI_DEVICE *Slave
-  )
-{
-  FreePool (Slave);
-
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-EFIAPI
-MvSpiConfigRuntime (
-  IN SPI_DEVICE *Slave
-  )
-{
-  EFI_STATUS Status;
-  UINTN AlignedAddress;
-
-  //
-  // Host register base may be not aligned to the page size,
-  // which is not accepted when setting memory space attributes.
-  // Add one aligned page of memory space which covers the host
-  // controller registers.
-  //
-  AlignedAddress = Slave->HostRegisterBaseAddress & ~(SIZE_4KB - 1);
-
-  Status = gDS->AddMemorySpace (EfiGcdMemoryTypeMemoryMappedIo,
-                  AlignedAddress,
-                  SIZE_4KB,
-                  EFI_MEMORY_UC | EFI_MEMORY_RUNTIME);
-  if (EFI_ERROR (Status)) {
-    DEBUG ((DEBUG_ERROR, "%a: Failed to add memory space\n", __FUNCTION__));
-    return Status;
-  }
-
-  Status = gDS->SetMemorySpaceAttributes (AlignedAddress,
-                  SIZE_4KB,
-                  EFI_MEMORY_UC | EFI_MEMORY_RUNTIME);
-  if (EFI_ERROR (Status)) {
-    DEBUG ((DEBUG_ERROR, "%a: Failed to set memory attributes\n", __FUNCTION__));
-    gDS->RemoveMemorySpace (AlignedAddress, SIZE_4KB);
-    return Status;
-  }
-
-  return EFI_SUCCESS;
-}
-
-STATIC
-EFI_STATUS
-SpiMasterInitProtocol (
-  IN MARVELL_SPI_MASTER_PROTOCOL *SpiMasterProtocol
-  )
-{
-
-  SpiMasterProtocol->Init        = MvSpiInit;
-  SpiMasterProtocol->SetupDevice = MvSpiSetupSlave;
-  SpiMasterProtocol->FreeDevice  = MvSpiFreeSlave;
-  SpiMasterProtocol->Transfer    = MvSpiTransfer;
-  SpiMasterProtocol->ReadWrite   = MvSpiReadWrite;
-  SpiMasterProtocol->ConfigRuntime = MvSpiConfigRuntime;
-
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-EFIAPI
-SpiMasterEntryPoint (
-  IN EFI_HANDLE       ImageHandle,
-  IN EFI_SYSTEM_TABLE *SystemTable
-  )
-{
-  EFI_STATUS  Status;
-
-  mSpiMasterInstance = AllocateRuntimeZeroPool (sizeof (SPI_MASTER));
-  if (mSpiMasterInstance == NULL) {
-    return EFI_OUT_OF_RESOURCES;
-  }
-
-  EfiInitializeLock (&mSpiMasterInstance->Lock, TPL_NOTIFY);
-
-  SpiMasterInitProtocol (&mSpiMasterInstance->SpiMasterProtocol);
-
-  mSpiMasterInstance->Signature = SPI_MASTER_SIGNATURE;
-
-  Status = gBS->InstallMultipleProtocolInterfaces (
-                  &(mSpiMasterInstance->Handle),
-                  &gMarvellSpiMasterProtocolGuid,
-                  &(mSpiMasterInstance->SpiMasterProtocol),
-                  NULL
-                  );
-  if (EFI_ERROR (Status)) {
-    FreePool (mSpiMasterInstance);
-    return EFI_DEVICE_ERROR;
-  }
-
-  return EFI_SUCCESS;
-}
diff --git a/Silicon/Marvell/Drivers/Spi/MvSpiDxe.h b/Silicon/Marvell/Drivers/Spi/MvSpiDxe.h
deleted file mode 100644
index 50cdc02..0000000
--- a/Silicon/Marvell/Drivers/Spi/MvSpiDxe.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/*******************************************************************************
-Copyright (C) 2016 Marvell International Ltd.
-
-Marvell BSD License Option
-
-If you received this File from Marvell, you may opt to use, redistribute and/or
-modify this File under the following licensing terms.
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice,
-  this list of conditions and the following disclaimer.
-
-* Redistributions in binary form must reproduce the above copyright
-  notice, this list of conditions and the following disclaimer in the
-  documentation and/or other materials provided with the distribution.
-
-* Neither the name of Marvell nor the names of its contributors may be
-  used to endorse or promote products derived from this software without
-  specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-#ifndef __SPI_MASTER_H__
-#define __SPI_MASTER_H__
-
-#include <Library/IoLib.h>
-#include <Library/PcdLib.h>
-#include <Library/UefiLib.h>
-#include <Library/DebugLib.h>
-#include <Library/DxeServicesTableLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Uefi/UefiBaseType.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/UefiRuntimeLib.h>
-
-#include <Protocol/Spi.h>
-
-#define SPI_MASTER_SIGNATURE                      SIGNATURE_32 ('M', 'S', 'P', 'I')
-#define SPI_MASTER_FROM_SPI_MASTER_PROTOCOL(a)  CR (a, SPI_MASTER, SpiMasterProtocol, SPI_MASTER_SIGNATURE)
-
-// Marvell Flash Device Controller Registers
-#define SPI_CTRL_REG                    (0x00)
-#define SPI_CONF_REG                    (0x04)
-#define SPI_DATA_OUT_REG                (0x08)
-#define SPI_DATA_IN_REG                 (0x0c)
-#define SPI_INT_CAUSE_REG               (0x10)
-
-// Serial Memory Interface Control Register Masks
-#define SPI_CS_NUM_OFFSET               2
-#define SPI_CS_NUM_MASK                 (0x7 << SPI_CS_NUM_OFFSET)
-#define SPI_MEM_READY_MASK              (0x1 << 1)
-#define SPI_CS_EN_MASK                  (0x1 << 0)
-
-// Serial Memory Interface Configuration Register Masks
-#define SPI_BYTE_LENGTH_OFFSET          5
-#define SPI_BYTE_LENGTH                 (0x1  << SPI_BYTE_LENGTH_OFFSET)
-#define SPI_CPOL_OFFSET                 11
-#define SPI_CPOL_MASK                   (0x1 << SPI_CPOL_OFFSET)
-#define SPI_CPHA_OFFSET                 12
-#define SPI_CPHA_MASK                  (0x1 << SPI_CPHA_OFFSET)
-#define SPI_TXLSBF_OFFSET               13
-#define SPI_TXLSBF_MASK                 (0x1 << SPI_TXLSBF_OFFSET)
-#define SPI_RXLSBF_OFFSET               14
-#define SPI_RXLSBF_MASK                 (0x1 << SPI_RXLSBF_OFFSET)
-
-#define SPI_SPR_OFFSET                  0
-#define SPI_SPR_MASK                    (0xf << SPI_SPR_OFFSET)
-#define SPI_SPPR_0_OFFSET               4
-#define SPI_SPPR_0_MASK                 (0x1 << SPI_SPPR_0_OFFSET)
-#define SPI_SPPR_HI_OFFSET              6
-#define SPI_SPPR_HI_MASK                (0x3 << SPI_SPPR_HI_OFFSET)
-
-#define SPI_TRANSFER_BEGIN              0x01  // Assert CS before transfer
-#define SPI_TRANSFER_END                0x02  // Deassert CS after transfers
-
-#define SPI_TIMEOUT                     100000
-
-typedef struct {
-  MARVELL_SPI_MASTER_PROTOCOL SpiMasterProtocol;
-  UINTN                   Signature;
-  EFI_HANDLE              Handle;
-  EFI_LOCK                Lock;
-} SPI_MASTER;
-
-EFI_STATUS
-EFIAPI
-MvSpiTransfer (
-  IN MARVELL_SPI_MASTER_PROTOCOL *This,
-  IN SPI_DEVICE *Slave,
-  IN UINTN DataByteCount,
-  IN VOID *DataOut,
-  IN VOID *DataIn,
-  IN UINTN Flag
-  );
-
-EFI_STATUS
-EFIAPI
-MvSpiReadWrite (
-  IN  MARVELL_SPI_MASTER_PROTOCOL *This,
-  IN  SPI_DEVICE *Slave,
-  IN  UINT8 *Cmd,
-  IN  UINTN CmdSize,
-  IN  UINT8 *DataOut,
-  OUT UINT8 *DataIn,
-  IN  UINTN DataSize
-  );
-
-EFI_STATUS
-EFIAPI
-MvSpiInit (
-  IN MARVELL_SPI_MASTER_PROTOCOL     * This
-  );
-
-SPI_DEVICE *
-EFIAPI
-MvSpiSetupSlave (
-  IN MARVELL_SPI_MASTER_PROTOCOL     * This,
-  IN SPI_DEVICE *Slave,
-  IN UINTN Cs,
-  IN SPI_MODE Mode
-  );
-
-EFI_STATUS
-EFIAPI
-MvSpiFreeSlave (
-  IN SPI_DEVICE *Slave
-  );
-
-EFI_STATUS
-EFIAPI
-SpiMasterEntryPoint (
-  IN EFI_HANDLE       ImageHandle,
-  IN EFI_SYSTEM_TABLE *SystemTable
-  );
-
-#endif // __SPI_MASTER_H__
diff --git a/Silicon/Marvell/Drivers/Spi/MvSpiDxe.inf b/Silicon/Marvell/Drivers/Spi/MvSpiDxe.inf
deleted file mode 100644
index e7bc170..0000000
--- a/Silicon/Marvell/Drivers/Spi/MvSpiDxe.inf
+++ /dev/null
@@ -1,73 +0,0 @@
-#
-# Marvell BSD License Option
-#
-# If you received this File from Marvell, you may opt to use, redistribute
-# and/or modify this File under the following licensing terms.
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
-#
-# * Redistributions of source code must retain the above copyright notice,
-# this list of conditions and the following disclaimer.
-#
-# * Redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution.
-#
-# * Neither the name of Marvell nor the names of its contributors may be
-# used to endorse or promote products derived from this software without
-# specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = SpiMasterDxe
-  FILE_GUID                      = c19dbc8a-f4f9-43b0-aee5-802e3ed03d15
-  MODULE_TYPE                    = DXE_RUNTIME_DRIVER
-  VERSION_STRING                 = 1.0
-  ENTRY_POINT                    = SpiMasterEntryPoint
-
-[Sources]
-  MvSpiDxe.c
-  MvSpiDxe.h
-
-[Packages]
-  EmbeddedPkg/EmbeddedPkg.dec
-  MdePkg/MdePkg.dec
-  Silicon/Marvell/Marvell.dec
-
-[LibraryClasses]
-  NorFlashInfoLib
-  UefiBootServicesTableLib
-  UefiDriverEntryPoint
-  TimerLib
-  UefiLib
-  DebugLib
-  DxeServicesTableLib
-  MemoryAllocationLib
-  IoLib
-  UefiRuntimeLib
-
-[FixedPcd]
-  gMarvellTokenSpaceGuid.PcdSpiRegBase
-  gMarvellTokenSpaceGuid.PcdSpiClockFrequency
-  gMarvellTokenSpaceGuid.PcdSpiMaxFrequency
-
-[Protocols]
-  gMarvellSpiMasterProtocolGuid
-
-[Depex]
-  #
-  # MvSpiDxe must be loaded prior to MvSpiFlash driver
-  #
-  BEFORE gMarvellSpiFlashDxeGuid
-- 
2.7.4