* [PATCH edk2-platforms v2 0/4] Platform/NXP-Add LS1046A RDB Board Support
@ 2017-12-19 2:41 Vabhav
2017-12-19 2:41 ` [PATCH edk2-platforms v2 1/4] Silicon/NXP:SocLib support for initialization of peripherals Vabhav
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Vabhav @ 2017-12-19 2:41 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
Changes for v2:
(1)Format changes as per edk2 coding guidelines
(2)Changes made to use NXP Mmio BE library
(3)Commit message updated
(4)Changes ported to latest edk2
Following patches will add support of NXP LS1046A RDB board in edk2-platforms.
Our directory structure for added folders will be:
Silicon/NXP/
|-- Chassis
| |-- Chassis2
| | |-- Soc.c
| |-- LS1046aSocLib.inf
|-- Library
| `-- Pcf2129RtcLib
| |-- Pcf2129Rtc.h
| |-- Pcf2129RtcLib.c
| `-- Pcf2129RtcLib.inf
`-- LS1046A
|-- Include
| `-- SocSerDes.h
|-- LS1046A.dec
`-- LS1046A.dsc
Platform/NXP/
|-- LS1046aRdbPkg
| |-- Library
| | `-- PlatformLib
| | |-- ArmPlatformLib.c
| | |-- ArmPlatformLib.inf
| | |-- NxpQoriqLsHelper.S
| | `-- NxpQoriqLsMem.c
| |-- LS1046aRdbPkg.dec
| |-- LS1046aRdbPkg.dsc
| `-- LS1046aRdbPkg.fdf
|-- NxpQoriqLs.dec
|-- NxpQoriqLs.dsc
`-- Readme.md
Platform/NXP/LS1046aRdbPkg will host .dsc and .fdf files to support compilation for LS1046A RDB board.
Please review and look forward for your support in upstreaming our board in edk2-platforms.
Vabhav (4):
Silicon/NXP:SocLib support for initialization of peripherals
Silicon/NXP:Add support for PCF2129 Real Time Clock Library
Platform/NXP: Add support for ArmPlatformLib
Compilation:Add the fdf,dsc and dec files
Platform/NXP/Drivers/I2cDxe/I2cDxe.c | 17 +-
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 1 +
Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec | 30 ++
Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc | 73 ++++
Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf | 297 ++++++++++++++++
.../Library/PlatformLib/ArmPlatformLib.c | 106 ++++++
.../Library/PlatformLib/ArmPlatformLib.inf | 70 ++++
.../Library/PlatformLib/NxpQoriqLsHelper.S | 39 +++
.../Library/PlatformLib/NxpQoriqLsMem.c | 181 ++++++++++
Platform/NXP/NxpQoriqLs.dec | 1 +
Platform/NXP/NxpQoriqLs.dsc | 17 -
Platform/NXP/Readme.md | 2 +-
Silicon/NXP/Chassis/Chassis2/Soc.c | 47 +++
Silicon/NXP/Chassis/LS1043aSocLib.inf | 2 +
Silicon/NXP/Chassis/LS1046aSocLib.inf | 49 +++
Silicon/NXP/LS1046A/Include/SocSerDes.h | 55 +++
Silicon/NXP/LS1046A/LS1046A.dec | 22 ++
Silicon/NXP/LS1046A/LS1046A.dsc | 78 +++++
Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h | 43 +++
Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c | 375 +++++++++++++++++++++
.../NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf | 47 +++
21 files changed, 1526 insertions(+), 26 deletions(-)
create mode 100644 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec
create mode 100644 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
create mode 100644 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
create mode 100644 Silicon/NXP/Chassis/LS1046aSocLib.inf
create mode 100644 Silicon/NXP/LS1046A/Include/SocSerDes.h
create mode 100644 Silicon/NXP/LS1046A/LS1046A.dec
create mode 100644 Silicon/NXP/LS1046A/LS1046A.dsc
create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h
create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c
create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf
--
1.9.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH edk2-platforms v2 1/4] Silicon/NXP:SocLib support for initialization of peripherals
2017-12-19 2:41 [PATCH edk2-platforms v2 0/4] Platform/NXP-Add LS1046A RDB Board Support Vabhav
@ 2017-12-19 2:41 ` Vabhav
2017-12-19 2:41 ` [PATCH edk2-platforms v2 2/4] Silicon/NXP:Add support for PCF2129 Real Time Clock Library Vabhav
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Vabhav @ 2017-12-19 2:41 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
SocInit function to initialize peripherals and print board,
soc information.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
---
Silicon/NXP/Chassis/Chassis2/Soc.c | 47 ++++++++++++++++++++++++++++
Silicon/NXP/Chassis/LS1043aSocLib.inf | 2 ++
Silicon/NXP/Chassis/LS1046aSocLib.inf | 49 +++++++++++++++++++++++++++++
Silicon/NXP/LS1046A/Include/SocSerDes.h | 55 +++++++++++++++++++++++++++++++++
4 files changed, 153 insertions(+)
create mode 100644 Silicon/NXP/Chassis/LS1046aSocLib.inf
create mode 100644 Silicon/NXP/LS1046A/Include/SocSerDes.h
diff --git a/Silicon/NXP/Chassis/Chassis2/Soc.c b/Silicon/NXP/Chassis/Chassis2/Soc.c
index 2f57929..ebe690a 100644
--- a/Silicon/NXP/Chassis/Chassis2/Soc.c
+++ b/Silicon/NXP/Chassis/Chassis2/Soc.c
@@ -17,6 +17,7 @@
#include <Chassis.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib/MemLibInternals.h>
+#include <Library/BeIoLib.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
@@ -116,6 +117,42 @@ GetSysInfo (
}
/**
+ Function to select pins depending upon pcd using supplemental
+ configuration unit(SCFG) extended RCW controlled pinmux control
+ register which contains the bits to provide pin multiplexing control.
+ This register is reset on HRESET.
+ **/
+VOID
+ConfigScfgMux (VOID)
+{
+ CCSR_SCFG *Scfg;
+ UINT32 UsbPwrFault;
+
+ Scfg = (VOID *)PcdGet64 (PcdScfgBaseAddr);
+ // Configures functionality of the IIC3_SCL to USB2_DRVVBUS
+ // Configures functionality of the IIC3_SDA to USB2_PWRFAULT
+
+ // LS1043A
+ // Configures functionality of the IIC4_SCL to USB3_DRVVBUS
+ // Configures functionality of the IIC4_SDA to USB3_PWRFAULT
+
+ // LS1046A
+ // USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA
+ if (PcdGetBool (PcdMuxToUsb3))
+ BeMmioWrite32 ((UINTN)&Scfg->RcwPMuxCr0, CCSR_SCFG_RCWPMUXCRO_SELCR_USB);
+ else
+ BeMmioWrite32 ((UINTN)&Scfg->RcwPMuxCr0, CCSR_SCFG_RCWPMUXCRO_NOT_SELCR_USB);
+ BeMmioWrite32 ((UINTN)&Scfg->UsbDrvVBusSelCr, CCSR_SCFG_USBDRVVBUS_SELCR_USB1);
+ UsbPwrFault = (CCSR_SCFG_USBPWRFAULT_DEDICATED <<
+ CCSR_SCFG_USBPWRFAULT_USB3_SHIFT) |
+ (CCSR_SCFG_USBPWRFAULT_DEDICATED <<
+ CCSR_SCFG_USBPWRFAULT_USB2_SHIFT) |
+ (CCSR_SCFG_USBPWRFAULT_SHARED <<
+ CCSR_SCFG_USBPWRFAULT_USB1_SHIFT);
+ BeMmioWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault);
+ BeMmioWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault);
+}
+/**
Function to initialize SoC specific constructs
// CPU Info
// SoC Personality
@@ -141,5 +178,15 @@ SocInit (
PrintCpuInfo ();
PrintRCW ();
+ //
+ // Due to the extensive functionality present on the chip and the limited number of external
+ // signals available, several functional blocks share signal resources through multiplexing.
+ // In this case when there is alternate functionality between multiple functional blocks,
+ // the signal's function is determined at the chip level (rather than at the block level)
+ // typically by a reset configuration word (RCW) option. Some of the signals' function are
+ // determined externel to RCW at Power-on Reset Sequence.
+ //
+ ConfigScfgMux ();
+
return;
}
diff --git a/Silicon/NXP/Chassis/LS1043aSocLib.inf b/Silicon/NXP/Chassis/LS1043aSocLib.inf
index e6e7ac4..4b1880e 100644
--- a/Silicon/NXP/Chassis/LS1043aSocLib.inf
+++ b/Silicon/NXP/Chassis/LS1043aSocLib.inf
@@ -45,3 +45,5 @@
gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled
gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3
+ gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr
diff --git a/Silicon/NXP/Chassis/LS1046aSocLib.inf b/Silicon/NXP/Chassis/LS1046aSocLib.inf
new file mode 100644
index 0000000..9422a2a
--- /dev/null
+++ b/Silicon/NXP/Chassis/LS1046aSocLib.inf
@@ -0,0 +1,49 @@
+# @file
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = SocLib
+ FILE_GUID = 5e9a2b48-a92a-4d55-87ec-e5e14a292f35
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SocLib
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Platform/NXP/NxpQoriqLs.dec
+ Silicon/NXP/Chassis/Chassis2/Chassis2.dec
+ Silicon/NXP/LS1046A/LS1046A.dec
+
+[LibraryClasses]
+ BaseLib
+ BeIoLib
+ DebugLib
+ SerialPortLib
+
+[Sources.common]
+ Chassis.c
+ Chassis2/Soc.c
+ SerDes.c
+
+[FixedPcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
+ gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
+ gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled
+ gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
+ gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3
+ gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr
diff --git a/Silicon/NXP/LS1046A/Include/SocSerDes.h b/Silicon/NXP/LS1046A/Include/SocSerDes.h
new file mode 100644
index 0000000..4bc5e28
--- /dev/null
+++ b/Silicon/NXP/LS1046A/Include/SocSerDes.h
@@ -0,0 +1,55 @@
+/** @file
+ The Header file of SerDes Module
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __LS1046A_SERDES_H__
+#define __LS1046A_SERDES_H__
+
+#include <SerDes.h>
+
+SERDES_CONFIG SerDes1ConfigTbl[] = {
+ // SerDes 1
+ {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
+ {0x1133, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
+ {0x1333, {XFI_FM1_MAC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
+ {0x2333, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
+ {0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
+ {0x1040, {XFI_FM1_MAC9, NONE, QSGMII_FM1_A, NONE } },
+ {0x2040, {SGMII_2500_FM1_DTSEC9, NONE, QSGMII_FM1_A, NONE } },
+ {0x1163, {XFI_FM1_MAC9, XFI_FM1_MAC10, PCIE1, SGMII_FM1_DTSEC6 } },
+ {0x2263, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, PCIE1, SGMII_FM1_DTSEC6 } },
+ {0x3363, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, PCIE1, SGMII_FM1_DTSEC6 } },
+ {0x2223, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, SGMII_2500_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
+ {}
+};
+
+SERDES_CONFIG SerDes2ConfigTbl[] = {
+ // SerDes 2
+ {0x8888, {PCIE1, PCIE1, PCIE1, PCIE1 } },
+ {0x5559, {PCIE1, PCIE2, PCIE3, SATA } },
+ {0x5577, {PCIE1, PCIE2, PCIE3, PCIE3 } },
+ {0x5506, {PCIE1, PCIE2, NONE, PCIE3 } },
+ {0x0506, {NONE, PCIE2, NONE, PCIE3 } },
+ {0x0559, {NONE, PCIE2, PCIE3, SATA } },
+ {0x5A59, {PCIE1, SGMII_FM1_DTSEC2, PCIE3, SATA } },
+ {0x5A06, {PCIE1, SGMII_FM1_DTSEC2, NONE, PCIE3 } },
+ {}
+};
+
+SERDES_CONFIG *SerDesConfigTbl[] = {
+ SerDes1ConfigTbl,
+ SerDes2ConfigTbl
+};
+
+#endif /* __LS1046A_SERDES_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH edk2-platforms v2 2/4] Silicon/NXP:Add support for PCF2129 Real Time Clock Library
2017-12-19 2:41 [PATCH edk2-platforms v2 0/4] Platform/NXP-Add LS1046A RDB Board Support Vabhav
2017-12-19 2:41 ` [PATCH edk2-platforms v2 1/4] Silicon/NXP:SocLib support for initialization of peripherals Vabhav
@ 2017-12-19 2:41 ` Vabhav
2017-12-19 2:41 ` [PATCH edk2-platforms v2 3/4] Platform/NXP: Add support for ArmPlatformLib Vabhav
2017-12-19 2:41 ` [PATCH edk2-platforms v2 4/4] Compilation:Add the fdf, dsc and dec files Vabhav
3 siblings, 0 replies; 5+ messages in thread
From: Vabhav @ 2017-12-19 2:41 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
Adding support for NXP pcf2129 real time clock library
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
---
Platform/NXP/Drivers/I2cDxe/I2cDxe.c | 17 +-
Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h | 43 +++
Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c | 375 +++++++++++++++++++++
.../NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf | 47 +++
4 files changed, 474 insertions(+), 8 deletions(-)
create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h
create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c
create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf
diff --git a/Platform/NXP/Drivers/I2cDxe/I2cDxe.c b/Platform/NXP/Drivers/I2cDxe/I2cDxe.c
index 1f43f9a..e866ce6 100644
--- a/Platform/NXP/Drivers/I2cDxe/I2cDxe.c
+++ b/Platform/NXP/Drivers/I2cDxe/I2cDxe.c
@@ -538,7 +538,8 @@ StartRequest (
UINT32 Length;
UINT8 *Buffer;
UINT32 Flag;
- UINT8 RegAddress;
+ UINT32 RegAddress;
+ UINT32 OffsetLength;
RegAddress = 0;
@@ -548,7 +549,10 @@ StartRequest (
return EFI_INVALID_PARAMETER;
}
- for (Count = 0; Count < RequestPacket->OperationCount; Count++) {
+ OffsetLength = RequestPacket->Operation[0].LengthInBytes;
+ RegAddress = *RequestPacket->Operation[0].Buffer;
+
+ for (Count = 1; Count < RequestPacket->OperationCount; Count++) {
Flag = RequestPacket->Operation[Count].Flags;
Length = RequestPacket->Operation[Count].LengthInBytes;
Buffer = RequestPacket->Operation[Count].Buffer;
@@ -559,12 +563,9 @@ StartRequest (
return EFI_INVALID_PARAMETER;
}
- if (Flag == I2C_FLAG_WRITE && Count == 0) {
- RegAddress = *Buffer;
- continue;
- } else if (Flag == I2C_FLAG_READ) {
+ if (Flag == I2C_FLAG_READ) {
Ret = I2cDataRead (PcdGet32 (PcdI2cBus), SlaveAddress,
- RegAddress, sizeof(SlaveAddress)/8, Buffer, Length);
+ RegAddress, OffsetLength, Buffer, Length);
if (Ret != EFI_SUCCESS) {
DEBUG ((DEBUG_ERROR,"%a: I2c read operation failed (error %d)\n",
__FUNCTION__, Ret));
@@ -572,7 +573,7 @@ StartRequest (
}
} else if (Flag == I2C_FLAG_WRITE) {
Ret = I2cDataWrite (PcdGet32 (PcdI2cBus), SlaveAddress,
- RegAddress, sizeof(SlaveAddress)/8, Buffer, Length);
+ RegAddress, OffsetLength, Buffer, Length);
if (Ret != EFI_SUCCESS) {
DEBUG ((DEBUG_ERROR,"%a: I2c write operation failed (error %d)\n",
__FUNCTION__, Ret));
diff --git a/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h
new file mode 100644
index 0000000..735f697
--- /dev/null
+++ b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h
@@ -0,0 +1,43 @@
+/** Pcf2129Rtc.h
+*
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __PCF2129RTC_H__
+#define __PCF2129RTC_H__
+
+/*
+ * RTC register addresses
+ */
+#define PCF2129_CTRL1_REG_ADDR 0x00 // Control Register 1
+#define PCF2129_CTRL2_REG_ADDR 0x01 // Control Register 2
+#define PCF2129_CTRL3_REG_ADDR 0x02 // Control Register 3
+#define PCF2129_SEC_REG_ADDR 0x03
+#define PCF2129_MIN_REG_ADDR 0x04
+#define PCF2129_HR_REG_ADDR 0x05
+#define PCF2129_DAY_REG_ADDR 0x06
+#define PCF2129_WEEKDAY_REG_ADDR 0x07
+#define PCF2129_MON_REG_ADDR 0x08
+#define PCF2129_YR_REG_ADDR 0x09
+
+#define PCF2129_CTRL3_BIT_BLF BIT2 /* Battery Low Flag*/
+
+// Define EPOCH (1998-JANUARY-01) in the Julian Date representation
+#define EPOCH_JULIAN_DATE 2450815
+
+typedef struct {
+ UINTN OperationCount;
+ EFI_I2C_OPERATION SetAddressOp;
+ EFI_I2C_OPERATION GetSetDateTimeOp;
+} RTC_I2C_REQUEST;
+
+#endif // __PCF2129RTC_H__
diff --git a/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c
new file mode 100644
index 0000000..b4ee61f
--- /dev/null
+++ b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c
@@ -0,0 +1,375 @@
+/** @PCF2129RtcLib.c
+ Implement EFI RealTimeClock with runtime services via RTC Lib for PCF2129 RTC.
+
+ Based on RTC implementation available in
+ EmbeddedPkg/Library/TemplateRealTimeClockLib/RealTimeClockLib.c
+
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiDxe.h>
+#include <Base.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/RealTimeClockLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Protocol/I2cMaster.h>
+
+#include "Pcf2129Rtc.h"
+
+STATIC VOID *mDriverEventRegistration;
+STATIC EFI_I2C_MASTER_PROTOCOL *mI2cMaster;
+
+/**
+ returns Day of the week [0-6] 0=Sunday
+ Don't try to provide a Year that's before 1998, please !
+ **/
+UINTN
+EfiTimeToWday (
+ IN EFI_TIME *Time
+ )
+{
+ UINTN a;
+ UINTN y;
+ UINTN m;
+ UINTN JulianDate; // Absolute Julian Date representation of the supplied Time
+ UINTN EpochDays; // Number of days elapsed since EPOCH_JULIAN_DAY
+
+ a = (14 - Time->Month) / 12 ;
+ y = Time->Year + 4800 - a;
+ m = Time->Month + (12*a) - 3;
+
+ JulianDate = Time->Day + ((153*m + 2)/5) + (365*y) + (y/4) - (y/100) + (y/400) - 32045;
+
+ ASSERT (JulianDate >= EPOCH_JULIAN_DATE);
+ EpochDays = JulianDate - EPOCH_JULIAN_DATE;
+
+ // 4=1/1/1998 was a Thursday
+
+ return (EpochDays + 4) % 7;
+}
+
+/**
+ Write RTC register.
+
+ @param RtcRegAddr Register offset of RTC to write.
+ @param Val Value to be written
+
+**/
+
+STATIC
+VOID
+RtcWrite (
+ IN UINT8 RtcRegAddr,
+ IN UINT8 Val
+ )
+{
+ RTC_I2C_REQUEST Req;
+ EFI_STATUS Status;
+
+ Req.OperationCount = 2;
+
+ Req.SetAddressOp.Flags = 0;
+ Req.SetAddressOp.LengthInBytes = 0;
+ Req.SetAddressOp.Buffer = &RtcRegAddr;
+
+ Req.GetSetDateTimeOp.Flags = 0;
+ Req.GetSetDateTimeOp.LengthInBytes = sizeof (Val);
+ Req.GetSetDateTimeOp.Buffer = &Val;
+
+ Status = mI2cMaster->StartRequest (mI2cMaster, FixedPcdGet8 (PcdI2cSlaveAddress),
+ (VOID *)&Req,
+ NULL, NULL);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "RTC write error at Addr:0x%x\n", RtcRegAddr));
+ }
+
+}
+
+/**
+ Returns the current time and date information, and the time-keeping capabilities
+ of the hardware platform.
+
+ @param Time A pointer to storage to receive a snapshot of the current time.
+ @param Capabilities An optional pointer to a buffer to receive the real time clock
+ device's capabilities.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER Time is NULL.
+ @retval EFI_DEVICE_ERROR The time could not be retrieved due to hardware error.
+
+**/
+
+EFI_STATUS
+EFIAPI
+LibGetTime (
+ OUT EFI_TIME *Time,
+ OUT EFI_TIME_CAPABILITIES *Capabilities
+ )
+{
+ EFI_STATUS Status;
+ UINT8 Buffer[10];
+ RTC_I2C_REQUEST Req;
+ UINT8 RtcRegAddr;
+
+ Status = EFI_SUCCESS;
+ RtcRegAddr = PCF2129_CTRL1_REG_ADDR;
+ Buffer[0] = 0;
+
+ if (mI2cMaster == NULL) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ RtcWrite (PCF2129_CTRL1_REG_ADDR, Buffer[0]);
+
+ if (Time == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Req.OperationCount = 2;
+
+ Req.SetAddressOp.Flags = 0;
+ Req.SetAddressOp.LengthInBytes = 0;
+ Req.SetAddressOp.Buffer = &RtcRegAddr;
+
+ Req.GetSetDateTimeOp.Flags = I2C_FLAG_READ;
+ Req.GetSetDateTimeOp.LengthInBytes = sizeof (Buffer);
+ Req.GetSetDateTimeOp.Buffer = Buffer;
+
+ Status = mI2cMaster->StartRequest (mI2cMaster, FixedPcdGet8 (PcdI2cSlaveAddress),
+ (VOID *)&Req,
+ NULL, NULL);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "RTC read error at Addr:0x%x\n", RtcRegAddr));
+ }
+
+ if (Buffer[PCF2129_CTRL3_REG_ADDR] & PCF2129_CTRL3_BIT_BLF) {
+ DEBUG((DEBUG_INFO, "### Warning: RTC battery status low, check/replace RTC battery.\n"));
+ }
+
+ Time->Nanosecond = 0;
+ Time->Second = BcdToDecimal8 (Buffer[PCF2129_SEC_REG_ADDR] & 0x7F);
+ Time->Minute = BcdToDecimal8 (Buffer[PCF2129_MIN_REG_ADDR] & 0x7F);
+ Time->Hour = BcdToDecimal8 (Buffer[PCF2129_HR_REG_ADDR] & 0x3F);
+ Time->Day = BcdToDecimal8 (Buffer[PCF2129_DAY_REG_ADDR] & 0x3F);
+ Time->Month = BcdToDecimal8 (Buffer[PCF2129_MON_REG_ADDR] & 0x1F);
+ Time->Year = BcdToDecimal8 (Buffer[PCF2129_YR_REG_ADDR]) + ( BcdToDecimal8 (Buffer[PCF2129_YR_REG_ADDR]) >= 98 ? 1900 : 2000);
+
+ return Status;
+}
+
+/**
+ Sets the current local time and date information.
+
+ @param Time A pointer to the current time.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+ @retval EFI_DEVICE_ERROR The time could not be set due due to hardware error.
+
+**/
+
+EFI_STATUS
+EFIAPI
+LibSetTime (
+ IN EFI_TIME *Time
+ )
+{
+ UINT8 Buffer[8];
+ UINT8 Index;
+ EFI_STATUS Status;
+ RTC_I2C_REQUEST Req;
+ UINT8 RtcRegAddr;
+
+ Index = 0;
+ Status = EFI_SUCCESS;
+ RtcRegAddr = PCF2129_CTRL1_REG_ADDR;
+
+ if (mI2cMaster == NULL) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ // start register address
+ Buffer[Index++] = PCF2129_SEC_REG_ADDR;
+
+ // hours, minutes and seconds
+ Buffer[Index++] = DecimalToBcd8 (Time->Second);
+ Buffer[Index++] = DecimalToBcd8 (Time->Minute);
+ Buffer[Index++] = DecimalToBcd8 (Time->Hour);
+ Buffer[Index++] = DecimalToBcd8 (Time->Day);
+ Buffer[Index++] = EfiTimeToWday (Time) & 0x07;
+ Buffer[Index++] = DecimalToBcd8 (Time->Month);
+ Buffer[Index++] = DecimalToBcd8 (Time->Year % 100);
+
+ Req.OperationCount = 2;
+ Req.SetAddressOp.Flags = 0;
+ Req.SetAddressOp.LengthInBytes = 0;
+ Req.SetAddressOp.Buffer = &RtcRegAddr;
+
+ Req.GetSetDateTimeOp.Flags = 0;
+ Req.GetSetDateTimeOp.LengthInBytes = sizeof (Buffer);
+ Req.GetSetDateTimeOp.Buffer = Buffer;
+
+ Status = mI2cMaster->StartRequest (mI2cMaster, FixedPcdGet8 (PcdI2cSlaveAddress),
+ (VOID *)&Req,
+ NULL, NULL);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "RTC write error at Addr:0x%x\n", RtcRegAddr));
+ return Status;
+ }
+
+ return Status;
+}
+
+
+/**
+ Returns the current wakeup alarm clock setting.
+
+ @param Enabled Indicates if the alarm is currently enabled or disabled.
+ @param Pending Indicates if the alarm signal is pending and requires acknowledgement.
+ @param Time The current alarm setting.
+
+ @retval EFI_SUCCESS The alarm settings were returned.
+ @retval EFI_INVALID_PARAMETER Any parameter is NULL.
+ @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+LibGetWakeupTime (
+ OUT BOOLEAN *Enabled,
+ OUT BOOLEAN *Pending,
+ OUT EFI_TIME *Time
+ )
+{
+ // Not a required feature
+ return EFI_UNSUPPORTED;
+}
+
+
+/**
+ Sets the system wakeup alarm clock time.
+
+ @param Enabled Enable or disable the wakeup alarm.
+ @param Time If Enable is TRUE, the time to set the wakeup alarm for.
+
+ @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled. If
+ Enable is FALSE, then the wakeup alarm was disabled.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+ @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error.
+ @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetWakeupTime (
+ IN BOOLEAN Enabled,
+ OUT EFI_TIME *Time
+ )
+{
+ // Not a required feature
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Fixup internal data so that EFI can be call in virtual mode.
+ Call the passed in Child Notify event and convert any pointers in
+ lib to virtual mode.
+
+ @param[in] Event The Event that is being processed
+ @param[in] Context Event Context
+**/
+VOID
+EFIAPI
+LibRtcVirtualNotifyEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ //
+ // Only needed if you are going to support the OS calling RTC functions in virtual mode.
+ // You will need to call EfiConvertPointer (). To convert any stored physical addresses
+ // to virtual address. After the OS transistions to calling in virtual mode, all future
+ // runtime calls will be made in virtual mode.
+ //
+// EfiConvertPointer (0x0, (VOID**)&mI2cBaseAddress);
+ return;
+}
+
+STATIC
+VOID
+I2cDriverRegistrationEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ EFI_STATUS Status;
+ EFI_I2C_MASTER_PROTOCOL *I2cMaster;
+ UINTN BusFrequency;
+
+ Status = gBS->LocateProtocol (&gEfiI2cMasterProtocolGuid, NULL, (VOID **)&I2cMaster);
+
+ gBS->CloseEvent (Event);
+
+ ASSERT_EFI_ERROR (Status);
+
+ Status = I2cMaster->Reset (I2cMaster);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: I2CMaster->Reset () failed - %r\n",
+ __FUNCTION__, Status));
+ return;
+ }
+
+ BusFrequency = FixedPcdGet16 (PcdI2cSpeed);
+ Status = I2cMaster->SetBusFrequency (I2cMaster, &BusFrequency);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: I2CMaster->SetBusFrequency () failed - %r\n",
+ __FUNCTION__, Status));
+ return;
+ }
+
+ mI2cMaster = I2cMaster;
+}
+
+/**
+ This is the declaration of an EFI image entry point. This can be the entry point to an application
+ written to this specification, an EFI boot service driver, or an EFI runtime driver.
+
+ @param ImageHandle Handle that identifies the loaded image.
+ @param SystemTable System Table for this image.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+LibRtcInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ //
+ // Register a protocol registration notification callback on the driver
+ // binding protocol so we can attempt to connect our I2C master to it
+ // as soon as it appears.
+ //
+ EfiCreateProtocolNotifyEvent (
+ &gEfiI2cMasterProtocolGuid,
+ TPL_CALLBACK,
+ I2cDriverRegistrationEvent,
+ NULL,
+ &mDriverEventRegistration);
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf
new file mode 100644
index 0000000..8edcc73
--- /dev/null
+++ b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf
@@ -0,0 +1,47 @@
+#/** @Pcf2129RtcLib.inf
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = Pcf2129RtcLib
+ FILE_GUID = B661E02D-A90B-42AB-A5F9-CF841AAA43D9
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RealTimeClockLib
+
+
+[Sources.common]
+ Pcf2129RtcLib.c
+
+[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ Platform/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ DebugLib
+ UefiBootServicesTableLib
+ UefiLib
+
+[Protocols]
+ gEfiDriverBindingProtocolGuid ## CONSUMES
+ gEfiI2cMasterProtocolGuid ## CONSUMES
+
+[Pcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cBus
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cSlaveAddress
+
+[Depex]
+ gEfiI2cMasterProtocolGuid
--
1.9.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH edk2-platforms v2 3/4] Platform/NXP: Add support for ArmPlatformLib
2017-12-19 2:41 [PATCH edk2-platforms v2 0/4] Platform/NXP-Add LS1046A RDB Board Support Vabhav
2017-12-19 2:41 ` [PATCH edk2-platforms v2 1/4] Silicon/NXP:SocLib support for initialization of peripherals Vabhav
2017-12-19 2:41 ` [PATCH edk2-platforms v2 2/4] Silicon/NXP:Add support for PCF2129 Real Time Clock Library Vabhav
@ 2017-12-19 2:41 ` Vabhav
2017-12-19 2:41 ` [PATCH edk2-platforms v2 4/4] Compilation:Add the fdf, dsc and dec files Vabhav
3 siblings, 0 replies; 5+ messages in thread
From: Vabhav @ 2017-12-19 2:41 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="UTF-8", Size: 16010 bytes --]
Adding support of ArmPlatformLib for NXP LS1046ARDB board
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
---
.../Library/PlatformLib/ArmPlatformLib.c | 106 ++++++++++++
.../Library/PlatformLib/ArmPlatformLib.inf | 70 ++++++++
.../Library/PlatformLib/NxpQoriqLsHelper.S | 39 +++++
.../Library/PlatformLib/NxpQoriqLsMem.c | 181 +++++++++++++++++++++
4 files changed, 396 insertions(+)
create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
new file mode 100644
index 0000000..795c7a9
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
@@ -0,0 +1,106 @@
+/** ArmPlatformLib.c
+*
+* Contains board initialization functions.
+*
+* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoard.c
+*
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/IoLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Ppi/ArmMpCoreInfo.h>
+
+extern VOID SocInit (VOID);
+
+/**
+ Return the current Boot Mode
+
+ This function returns the boot reason on the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+ VOID
+ )
+{
+ return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+ Placeholder for Platform Initialization
+**/
+RETURN_STATUS
+ArmPlatformInitialize (
+ IN UINTN MpId
+ )
+{
+ SocInit ();
+ return RETURN_SUCCESS;
+}
+
+ARM_CORE_INFO LS1046aMpCoreInfoCTA72x4[] = {
+ {
+ // Cluster 0, Core 0
+ 0x0, 0x0,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)0,
+ (EFI_PHYSICAL_ADDRESS)0,
+ (EFI_PHYSICAL_ADDRESS)0,
+ (UINT64)0xFFFFFFFF
+ },
+};
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+ OUT UINTN *CoreCount,
+ OUT ARM_CORE_INFO **ArmCoreTable
+ )
+{
+ *CoreCount = sizeof (LS1046aMpCoreInfoCTA72x4) / sizeof (ARM_CORE_INFO);
+ *ArmCoreTable = LS1046aMpCoreInfoCTA72x4;
+
+ return EFI_SUCCESS;
+}
+
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &gArmMpCoreInfoPpiGuid,
+ &mMpCoreInfoPpi
+ }
+};
+
+VOID
+ArmPlatformGetPlatformPpiList (
+ OUT UINTN *PpiListSize,
+ OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
+ )
+{
+ *PpiListSize = sizeof (gPlatformPpiTable);
+ *PpiList = gPlatformPpiTable;
+}
+
+
+UINTN
+ArmPlatformGetCorePosition (
+ IN UINTN MpId
+ )
+{
+ return 1;
+}
diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
new file mode 100644
index 0000000..13a0ffb
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
@@ -0,0 +1,70 @@
+#/* @file
+# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = ArmPlatformLib
+ FILE_GUID = 177a95a8-27c2-4582-8ba9-c87aa3e0ba75
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmPlatformLib
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ Platform/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ ArmLib
+ SocLib
+
+[Sources.common]
+ NxpQoriqLsHelper.S | GCC
+ ArmPlatformLib.c
+ NxpQoriqLsMem.c
+
+[Ppis]
+ gArmMpCoreInfoPpiGuid
+
+[FeaturePcd]
+ gEmbeddedTokenSpaceGuid.PcdCacheEnable
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdArmPrimaryCore
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size
+ gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize
+ gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1Size
+ gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdDram2Size
+ gNxpQoriqLsTokenSpaceGuid.PcdDram3BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdDram3Size
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize
diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
new file mode 100644
index 0000000..55e750f
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
@@ -0,0 +1,39 @@
+# @file
+#
+# Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardHelper.S
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+#include <AsmMacroIoLibV8.h>
+#include <AutoGen.h>
+
+.text
+.align 2
+
+GCC_ASM_IMPORT(ArmReadMpidr)
+
+ASM_FUNC(ArmPlatformIsPrimaryCore)
+ tst x0, #3
+ cset x0, eq
+ ret
+
+ASM_FUNC(ArmPlatformPeiBootAction)
+EL1_OR_EL2(x0)
+1:
+2:
+ ret
+
+ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
+ MOV32 (x0, FixedPcdGet32(PcdArmPrimaryCore))
+ ldrh w0, [x0]
+ ret
diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
new file mode 100644
index 0000000..7022528
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
@@ -0,0 +1,181 @@
+/** NxpQoriqLsMem.c
+*
+* Board memory specific Library.
+*
+* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c
+*
+* Copyright (c) 2011, ARM Limited. All rights reserved.
+* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25
+
+#define CCSR_BASE_ADDR FixedPcdGet64 (PcdCcsrBaseAddr)
+#define CCSR_SIZE FixedPcdGet64 (PcdCcsrSize)
+#define IFC_REGION1_BASE_ADDR FixedPcdGet64 (PcdIfcRegion1BaseAddr)
+#define IFC_REGION1_SIZE FixedPcdGet64 (PcdIfcRegion1Size)
+#define IFC_REGION2_BASE_ADDR FixedPcdGet64 (PcdIfcRegion2BaseAddr)
+#define IFC_REGION2_SIZE FixedPcdGet64 (PcdIfcRegion2Size)
+#define QMAN_SWP_BASE_ADDR FixedPcdGet64 (PcdQmanSwpBaseAddr)
+#define QMAN_SWP_SIZE FixedPcdGet64 (PcdQmanSwpSize)
+#define BMAN_SWP_BASE_ADDR FixedPcdGet64 (PcdBmanSwpBaseAddr)
+#define BMAN_SWP_SIZE FixedPcdGet64 (PcdBmanSwpSize)
+#define PCI_EXP1_BASE_ADDR FixedPcdGet64 (PcdPciExp1BaseAddr)
+#define PCI_EXP1_BASE_SIZE FixedPcdGet64 (PcdPciExp1BaseSize)
+#define PCI_EXP2_BASE_ADDR FixedPcdGet64 (PcdPciExp2BaseAddr)
+#define PCI_EXP2_BASE_SIZE FixedPcdGet64 (PcdPciExp2BaseSize)
+#define PCI_EXP3_BASE_ADDR FixedPcdGet64 (PcdPciExp3BaseAddr)
+#define PCI_EXP3_BASE_SIZE FixedPcdGet64 (PcdPciExp3BaseSize)
+#define DRAM1_BASE_ADDR FixedPcdGet64 (PcdDram1BaseAddr)
+#define DRAM1_SIZE FixedPcdGet64 (PcdDram1Size)
+#define DRAM2_BASE_ADDR FixedPcdGet64 (PcdDram2BaseAddr)
+#define DRAM2_SIZE FixedPcdGet64 (PcdDram2Size)
+#define DRAM3_BASE_ADDR FixedPcdGet64 (PcdDram3BaseAddr)
+#define DRAM3_SIZE FixedPcdGet64 (PcdDram3Size)
+#define QSPI_REGION_BASE_ADDR FixedPcdGet64 (PcdQspiRegionBaseAddr)
+#define QSPI_REGION_SIZE FixedPcdGet64 (PcdQspiRegionSize)
+
+
+/**
+ Return the Virtual Memory Map of your platform
+
+ This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
+
+ @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
+ Virtual Memory mapping. This array must be ended by a zero-filled
+ entry
+
+**/
+
+VOID
+ArmPlatformGetVirtualMemoryMap (
+ IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
+ )
+{
+ ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;
+ UINTN Index = 0;
+ ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
+
+ ASSERT (VirtualMemoryMap != NULL);
+
+ VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages (EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
+ if (VirtualMemoryTable == NULL) {
+ return;
+ }
+
+ if (FeaturePcdGet (PcdCacheEnable) == TRUE) {
+ CacheAttributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+ } else {
+ CacheAttributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+ }
+
+ // DRAM1 (Must be 1st entry)
+ VirtualMemoryTable[Index].PhysicalBase = DRAM1_BASE_ADDR;
+ VirtualMemoryTable[Index].VirtualBase = DRAM1_BASE_ADDR;
+ VirtualMemoryTable[Index].Length = DRAM1_SIZE;
+ VirtualMemoryTable[Index].Attributes = CacheAttributes;
+
+ // CCSR Space
+ VirtualMemoryTable[++Index].PhysicalBase = CCSR_BASE_ADDR;
+ VirtualMemoryTable[Index].VirtualBase = CCSR_BASE_ADDR;
+ VirtualMemoryTable[Index].Length = CCSR_SIZE;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // IFC region 1
+ //
+ // A-009241 : Unaligned write transactions to IFC may result in corruption of data
+ // Affects : IFC
+ // Description: 16 byte unaligned write from system bus to IFC may result in extra unintended
+ // writes on external IFC interface that can corrupt data on external flash.
+ // Impact : Data corruption on external flash may happen in case of unaligned writes to
+ // IFC memory space.
+ // Workaround: Following are the workarounds:
+ // • For write transactions from core, IFC interface memories (including IFC SRAM)
+ // should be configured as “device type" memory in MMU.
+ // • For write transactions from non-core masters (like system DMA), the address
+ // should be 16 byte aligned and the data size should be multiple of 16 bytes.
+ //
+ VirtualMemoryTable[++Index].PhysicalBase = IFC_REGION1_BASE_ADDR;
+ VirtualMemoryTable[Index].VirtualBase = IFC_REGION1_BASE_ADDR;
+ VirtualMemoryTable[Index].Length = IFC_REGION1_SIZE;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // QMAN SWP
+ VirtualMemoryTable[++Index].PhysicalBase = QMAN_SWP_BASE_ADDR;
+ VirtualMemoryTable[Index].VirtualBase = QMAN_SWP_BASE_ADDR;
+ VirtualMemoryTable[Index].Length = QMAN_SWP_SIZE;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+
+ // BMAN SWP
+ VirtualMemoryTable[++Index].PhysicalBase = BMAN_SWP_BASE_ADDR;
+ VirtualMemoryTable[Index].VirtualBase = BMAN_SWP_BASE_ADDR;
+ VirtualMemoryTable[Index].Length = BMAN_SWP_SIZE;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+
+ // IFC region 2
+ VirtualMemoryTable[++Index].PhysicalBase = IFC_REGION2_BASE_ADDR;
+ VirtualMemoryTable[Index].VirtualBase = IFC_REGION2_BASE_ADDR;
+ VirtualMemoryTable[Index].Length = IFC_REGION2_SIZE;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // DRAM2
+ VirtualMemoryTable[++Index].PhysicalBase = DRAM2_BASE_ADDR;
+ VirtualMemoryTable[Index].VirtualBase = DRAM2_BASE_ADDR;
+ VirtualMemoryTable[Index].Length = DRAM2_SIZE;
+ VirtualMemoryTable[Index].Attributes = CacheAttributes;
+
+ // PCIe1
+ VirtualMemoryTable[++Index].PhysicalBase = PCI_EXP1_BASE_ADDR;
+ VirtualMemoryTable[Index].VirtualBase = PCI_EXP1_BASE_ADDR;
+ VirtualMemoryTable[Index].Length = PCI_EXP1_BASE_SIZE;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // PCIe2
+ VirtualMemoryTable[++Index].PhysicalBase = PCI_EXP2_BASE_ADDR;
+ VirtualMemoryTable[Index].VirtualBase = PCI_EXP2_BASE_ADDR;
+ VirtualMemoryTable[Index].Length = PCI_EXP2_BASE_SIZE;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // PCIe3
+ VirtualMemoryTable[++Index].PhysicalBase = PCI_EXP3_BASE_ADDR;
+ VirtualMemoryTable[Index].VirtualBase = PCI_EXP3_BASE_ADDR;
+ VirtualMemoryTable[Index].Length = PCI_EXP3_BASE_SIZE;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // DRAM3
+ VirtualMemoryTable[++Index].PhysicalBase = DRAM3_BASE_ADDR;
+ VirtualMemoryTable[Index].VirtualBase = DRAM3_BASE_ADDR;
+ VirtualMemoryTable[Index].Length = DRAM3_SIZE;
+ VirtualMemoryTable[Index].Attributes = CacheAttributes;
+
+ // QSPI region
+ VirtualMemoryTable[++Index].PhysicalBase = QSPI_REGION_BASE_ADDR;
+ VirtualMemoryTable[Index].VirtualBase = QSPI_REGION_BASE_ADDR;
+ VirtualMemoryTable[Index].Length = QSPI_REGION_SIZE;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+
+ // End of Table
+ VirtualMemoryTable[++Index].PhysicalBase = 0;
+ VirtualMemoryTable[Index].VirtualBase = 0;
+ VirtualMemoryTable[Index].Length = 0;
+ VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
+
+ ASSERT ((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
+
+ *VirtualMemoryMap = VirtualMemoryTable;
+}
--
1.9.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH edk2-platforms v2 4/4] Compilation:Add the fdf, dsc and dec files
2017-12-19 2:41 [PATCH edk2-platforms v2 0/4] Platform/NXP-Add LS1046A RDB Board Support Vabhav
` (2 preceding siblings ...)
2017-12-19 2:41 ` [PATCH edk2-platforms v2 3/4] Platform/NXP: Add support for ArmPlatformLib Vabhav
@ 2017-12-19 2:41 ` Vabhav
3 siblings, 0 replies; 5+ messages in thread
From: Vabhav @ 2017-12-19 2:41 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
Adding firmware device,description and declaration
files to enable compilation for NXP LS1046ARDB board.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
---
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 1 +
Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec | 30 +++
Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc | 73 +++++++
Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf | 297 +++++++++++++++++++++++++++
Platform/NXP/NxpQoriqLs.dec | 1 +
Platform/NXP/NxpQoriqLs.dsc | 17 --
Platform/NXP/Readme.md | 2 +-
Silicon/NXP/LS1046A/LS1046A.dec | 22 ++
Silicon/NXP/LS1046A/LS1046A.dsc | 78 +++++++
9 files changed, 503 insertions(+), 18 deletions(-)
create mode 100644 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec
create mode 100644 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
create mode 100644 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
create mode 100644 Silicon/NXP/LS1046A/LS1046A.dec
create mode 100644 Silicon/NXP/LS1046A/LS1046A.dsc
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index 1951e82..4840076 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -47,6 +47,7 @@
#
gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE
gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1
+ gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3|TRUE
#
# Big Endian IPs
diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec
new file mode 100644
index 0000000..bdede59
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec
@@ -0,0 +1,30 @@
+#/** LS1046a board package.
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ PACKAGE_NAME = LS1046aRdbPkg
+ PACKAGE_GUID = 6eba6648-d853-4eb3-9761-528b82d5ab04
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+[Includes.common]
+ Include # Root include for the package
+
diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
new file mode 100644
index 0000000..9d2482b
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
@@ -0,0 +1,73 @@
+#/** LS1046ARDB Board package.
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ #
+ # Defines for default states. These can be changed on the command line.
+ # -D FLAG=VALUE
+ #
+ PLATFORM_NAME = LS1046aRdbPkg
+ PLATFORM_GUID = 60169ec4-d2b4-44f8-825e-f8684fd42e4f
+ OUTPUT_DIRECTORY = Build/LS1046aRdbPkg
+ FLASH_DEFINITION = edk2-platforms/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
+
+!include ../NxpQoriqLs.dsc
+!include ../../../Silicon/NXP/LS1046A/LS1046A.dsc
+
+[LibraryClasses.common]
+ ArmPlatformLib|edk2-platforms/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
+ ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
+ SerialPortLib|edk2-platforms/Platform/NXP/Library/DUartPortLib/DUartPortLib.inf
+ BeIoLib|edk2-platforms/Platform/NXP/Library/BeIoLib/BeIoLib.inf
+ SocLib|edk2-platforms/Silicon/NXP/Chassis/LS1046aSocLib.inf
+ RealTimeClockLib|edk2-platforms/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf
+
+[PcdsFixedAtBuild.common]
+ #
+ # Board Specific Pcds
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|TRUE
+ gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x2
+ gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3|FALSE
+
+ #
+ # Big Endian IPs
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
+ gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|TRUE
+
+ #
+ # I2C controller Pcds
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cBus|3
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed|100000
+
+ #
+ # RTC Pcds
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cSlaveAddress|0x51
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+ edk2-platforms/Platform/NXP/Drivers/WatchDog/WatchDogDxe.inf
+ edk2-platforms/Platform/NXP/Drivers/I2cDxe/I2cDxe.inf
diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
new file mode 100644
index 0000000..169cef0
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
@@ -0,0 +1,297 @@
+# LS1046aRdbPkg.fdf
+#
+# FLASH layout file for LS1046a board.
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into the Flash Device Image. Each FD section
+# defines one flash "device" image. A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash" image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.LS1046aRdb_EFI]
+BaseAddress = 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The base address of the FLASH Device.
+Size = 0x000ED850|gArmTokenSpaceGuid.PcdFdSize #The size in bytes of the FLASH Device
+ErasePolarity = 1
+BlockSize = 0x1
+NumBlocks = 0xED850
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+0x00000000|0x000ED850
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = FVMAIN_COMPACT
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+FvNameGuid = 1037c42b-8452-4c41-aac7-41e6c31468da
+BlockSize = 0x1
+NumBlocks = 0 # This FV gets compressed so make it just big enough
+FvAlignment = 8 # FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+ #
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)
+ #
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+ INF edk2-platforms/Platform/NXP/Drivers/WatchDog/WatchDogDxe.inf
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+ INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+
+ #
+ # Multiple Console IO support
+ #
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+ INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+ INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
+
+ #
+ # Network modules
+ #
+ INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+ INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+ INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+ INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+ INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+ INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+ INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+!if $(NETWORK_IP6_ENABLE) == TRUE
+ INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf
+ INF NetworkPkg/TcpDxe/TcpDxe.inf
+ INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf
+ INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
+ INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
+ INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
+!else
+ INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+!endif
+
+ INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ INF FatPkg/FatPei/FatPei.inf
+ INF FatPkg/EnhancedFatDxe/Fat.inf
+
+ #
+ # UEFI application (Shell Embedded Boot Loader)
+ #
+ INF ShellPkg/Application/Shell/Shell.inf
+
+ #
+ # Bds
+ #
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+ INF edk2-platforms/Platform/NXP/Drivers/I2cDxe/I2cDxe.inf
+
+[FV.FVMAIN_COMPACT]
+FvAlignment = 8
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF ArmPlatformPkg/PrePi/PeiUniCore.inf
+
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FVMAIN
+ }
+ }
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+
+############################################################################
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #
+############################################################################
+#
+#[Rule.Common.DXE_DRIVER]
+# FILE DRIVER = $(NAMED_GUID) {
+# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+# COMPRESS PI_STD {
+# GUIDED {
+# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+# UI STRING="$(MODULE_NAME)" Optional
+# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+# }
+# }
+# }
+#
+############################################################################
+
+[Rule.Common.SEC]
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+ TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.PEI_CORE]
+ FILE PEI_CORE = $(NAMED_GUID) {
+ TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING ="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM]
+ FILE PEIM = $(NAMED_GUID) {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM.TIANOCOMPRESSED]
+ FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+ }
+
+[Rule.Common.DXE_CORE]
+ FILE DXE_CORE = $(NAMED_GUID) {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+
+[Rule.Common.UEFI_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_APPLICATION]
+ FILE APPLICATION = $(NAMED_GUID) {
+ UI STRING ="$(MODULE_NAME)" Optional
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.UEFI_DRIVER.BINARY]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.UEFI_APPLICATION.BINARY]
+ FILE APPLICATION = $(NAMED_GUID) {
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
diff --git a/Platform/NXP/NxpQoriqLs.dec b/Platform/NXP/NxpQoriqLs.dec
index fd07eee..52102bf 100644
--- a/Platform/NXP/NxpQoriqLs.dec
+++ b/Platform/NXP/NxpQoriqLs.dec
@@ -30,6 +30,7 @@
gNxpQoriqLsTokenSpaceGuid.PcdI2cBus|0|UINT32|0x00000001
gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed|0|UINT32|0x00000002
gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|0|UINT32|0x00000003
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cSlaveAddress|0|UINT32|0x00000004
#
# Pcds for base address and size
diff --git a/Platform/NXP/NxpQoriqLs.dsc b/Platform/NXP/NxpQoriqLs.dsc
index 768a9e8..9399182 100644
--- a/Platform/NXP/NxpQoriqLs.dsc
+++ b/Platform/NXP/NxpQoriqLs.dsc
@@ -34,7 +34,6 @@
ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
- ArmTrustZoneLib|ArmPlatformPkg/Drivers/ArmTrustZone/ArmTrustZone.inf
ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
@@ -62,7 +61,6 @@
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
- EfiFileLib|EmbeddedPkg/Library/EfiFileLib/EfiFileLib.inf
PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
@@ -87,7 +85,6 @@
ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf
- BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
@@ -139,7 +136,6 @@
ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
- PeCoffLib|EmbeddedPkg/Library/DxeHobPeCoffLib/DxeHobPeCoffLib.inf
PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
[LibraryClasses.common.DXE_DRIVER]
@@ -168,7 +164,6 @@
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
- PeCoffLib|EmbeddedPkg/Library/DxeHobPeCoffLib/DxeHobPeCoffLib.inf
[LibraryClasses.AARCH64]
#
@@ -291,7 +286,6 @@
gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
# Size of the region reserved for fixed address allocations (Reserved 32MB)
- gArmTokenSpaceGuid.PcdArmLinuxKernelMaxOffset|0x08000000
gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x08000000
gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x0
gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x94A00000
@@ -306,8 +300,6 @@
gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
# Use the serial console for both ConIn & ConOut
- gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi();"
- gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()"
gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|16000
!ifdef $(NO_SHELL_PROFILES)
@@ -335,7 +327,6 @@
MdeModulePkg/Core/Dxe/DxeMain.inf {
<LibraryClasses>
NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
- NULL|EmbeddedPkg/Library/LzmaHobCustomDecompressLib/LzmaHobCustomDecompressLib.inf
}
MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
<LibraryClasses>
@@ -355,7 +346,6 @@
EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
# FDT installation
- EmbeddedPkg/Drivers/FdtPlatformDxe/FdtPlatformDxe.inf
MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
@@ -424,12 +414,6 @@
ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
- ShellPkg/Library/UefiDpLib/UefiDpLib.inf {
- <LibraryClasses>
- TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf
- PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
- DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
- }
ShellPkg/Application/Shell/Shell.inf {
<LibraryClasses>
NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
@@ -440,7 +424,6 @@
NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
- NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf
!ifdef $(INCLUDE_DP)
NULL|ShellPkg/Library/UefiDpLib/UefiDpLib.inf
!endif #$(INCLUDE_DP)
diff --git a/Platform/NXP/Readme.md b/Platform/NXP/Readme.md
index 2c36f43..f6822fd 100644
--- a/Platform/NXP/Readme.md
+++ b/Platform/NXP/Readme.md
@@ -12,4 +12,4 @@ user need to run only build command.
board-name : LS1043 / LS1046 / LS2088
build-candidate : DEBUG / RELEASE
-Currently, support for LS1043 is provided.
+Currently, support for LS1043,LS1046 is provided.
diff --git a/Silicon/NXP/LS1046A/LS1046A.dec b/Silicon/NXP/LS1046A/LS1046A.dec
new file mode 100644
index 0000000..5f41319
--- /dev/null
+++ b/Silicon/NXP/LS1046A/LS1046A.dec
@@ -0,0 +1,22 @@
+# LS1046A.dec
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+
+[Guids.common]
+ gNxpLs1046ATokenSpaceGuid = {0x1edb40ad, 0x1178, 0x407f, {0x8f, 0x1a, 0x64, 0x20, 0x8a, 0x16, 0x33, 0xd1}}
+
+[Includes]
+ Include
diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc b/Silicon/NXP/LS1046A/LS1046A.dsc
new file mode 100644
index 0000000..4e7230a
--- /dev/null
+++ b/Silicon/NXP/LS1046A/LS1046A.dsc
@@ -0,0 +1,78 @@
+# LS1046A board package.
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsDynamicDefault.common]
+
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x1410000
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x1420000
+
+[PcdsFixedAtBuild.common]
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x21c0500
+
+ #
+ # LS1046a board Specific PCDs
+ # XX (DRAM - Region 1 2GB)
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x80000000
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000
+
+ #
+ # CCSR Address Space and other attached Memories
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000
+ gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x01EE1000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x60000000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x20000000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0620000000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x00E0000000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x2EA
+ gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000
+ gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000
+ gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000
+ gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0080000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x4000000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x800000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x4800000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x800000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x5000000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x800000000
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr|0x0080000000
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1Size|0x0080000000
+ gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr|0x0880000000
+ gNxpQoriqLsTokenSpaceGuid.PcdDram2Size|0x0780000000
+ gNxpQoriqLsTokenSpaceGuid.PcdDram3BaseAddr|0x8800000000
+ gNxpQoriqLsTokenSpaceGuid.PcdDram3Size|0x7800000000
+ gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x1570000
+ gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x01EE0000
+ gNxpQoriqLsTokenSpaceGuid.PcdWdog1BaseAddr|0x02AD0000
+ gNxpQoriqLsTokenSpaceGuid.PcdWdog2BaseAddr|0x02AE0000
+ gNxpQoriqLsTokenSpaceGuid.PcdWdog3BaseAddr|0x02A70000
+ gNxpQoriqLsTokenSpaceGuid.PcdWdog4BaseAddr|0x02A80000
+ gNxpQoriqLsTokenSpaceGuid.PcdWdog5BaseAddr|0x02A90000
+ gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x01560000
+ gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02180000
+ gNxpQoriqLsTokenSpaceGuid.PcdI2c1BaseAddr|0x02190000
+ gNxpQoriqLsTokenSpaceGuid.PcdI2c2BaseAddr|0x021A0000
+ gNxpQoriqLsTokenSpaceGuid.PcdI2c3BaseAddr|0x021B0000
+ gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
+
+##
--
1.9.1
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2017-12-19 2:41 [PATCH edk2-platforms v2 0/4] Platform/NXP-Add LS1046A RDB Board Support Vabhav
2017-12-19 2:41 ` [PATCH edk2-platforms v2 1/4] Silicon/NXP:SocLib support for initialization of peripherals Vabhav
2017-12-19 2:41 ` [PATCH edk2-platforms v2 2/4] Silicon/NXP:Add support for PCF2129 Real Time Clock Library Vabhav
2017-12-19 2:41 ` [PATCH edk2-platforms v2 3/4] Platform/NXP: Add support for ArmPlatformLib Vabhav
2017-12-19 2:41 ` [PATCH edk2-platforms v2 4/4] Compilation:Add the fdf, dsc and dec files Vabhav
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