* [PATCH edk2-platforms 0/4] NXP:LS2088A RDB Board Support
@ 2017-12-22 10:51 Wasim Khan
2017-12-22 10:51 ` [PATCH edk2-platforms 1/4] Platform/NXP: Add support for ArmPlatformLib Wasim Khan
` (4 more replies)
0 siblings, 5 replies; 7+ messages in thread
From: Wasim Khan @ 2017-12-22 10:51 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
In Silicon/NXP, we are keeping our SoC specific information and remaining code will be kept in Platform/NXP.
Following patches will add support of NXP LS2088A RDB board in edk2-platforms.
Platform/NXP/LS2088aRdbPkg will host .dsc and .fdf files to support compilation for LS2088A RDB board.
Looking forward for your kind support in upstreaming LS2088 RDB board support in edk2-platforms.
Wasim Khan (4):
Platform/NXP: Add support for ArmPlatformLib
Silicon/Maxim: Added Support for DS3232 RTC Library
Silicon/NXP:SocLib support for initialization of peripherals
Compilation : Add the fdf, dsc and dec files.
.../LS2088aRdbPkg/Include/Library/PlatformLib.h | 28 ++
Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec | 29 ++
Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc | 95 ++++++
Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf | 197 +++++++++++
.../Library/PlatformLib/ArmPlatformLib.c | 106 ++++++
.../Library/PlatformLib/ArmPlatformLib.inf | 80 +++++
.../Library/PlatformLib/NxpQoriqLsHelper.S | 35 ++
.../Library/PlatformLib/NxpQoriqLsMem.c | 196 +++++++++++
Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc | 98 ++++++
Platform/NXP/NxpQoriqLs.dec | 1 +
Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h | 49 +++
Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c | 370 +++++++++++++++++++++
.../Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec | 31 ++
.../Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf | 50 +++
Silicon/NXP/Chassis/Chassis.c | 32 ++
Silicon/NXP/Chassis/Chassis.h | 17 +
Silicon/NXP/Chassis/Chassis3/Chassis3.dec | 19 ++
Silicon/NXP/Chassis/Chassis3/Errata.c | 62 ++++
Silicon/NXP/Chassis/Chassis3/SerDes.h | 92 +++++
Silicon/NXP/Chassis/Chassis3/Soc.c | 171 ++++++++++
Silicon/NXP/Chassis/Chassis3/Soc.h | 159 +++++++++
Silicon/NXP/Chassis/LS2088aSocLib.inf | 53 +++
Silicon/NXP/LS2088A/Include/SocSerDes.h | 67 ++++
Silicon/NXP/LS2088A/LS2088A.dec | 22 ++
Silicon/NXP/LS2088A/LS2088A.dsc | 101 ++++++
25 files changed, 2160 insertions(+)
create mode 100755 Platform/NXP/LS2088aRdbPkg/Include/Library/PlatformLib.h
create mode 100644 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec
create mode 100755 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
create mode 100644 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
create mode 100644 Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc
create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h
create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c
create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec
create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf
create mode 100644 Silicon/NXP/Chassis/Chassis3/Chassis3.dec
create mode 100644 Silicon/NXP/Chassis/Chassis3/Errata.c
create mode 100644 Silicon/NXP/Chassis/Chassis3/SerDes.h
create mode 100644 Silicon/NXP/Chassis/Chassis3/Soc.c
create mode 100644 Silicon/NXP/Chassis/Chassis3/Soc.h
create mode 100644 Silicon/NXP/Chassis/LS2088aSocLib.inf
create mode 100644 Silicon/NXP/LS2088A/Include/SocSerDes.h
create mode 100644 Silicon/NXP/LS2088A/LS2088A.dec
create mode 100644 Silicon/NXP/LS2088A/LS2088A.dsc
--
2.7.4
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH edk2-platforms 1/4] Platform/NXP: Add support for ArmPlatformLib
2017-12-22 10:51 [PATCH edk2-platforms 0/4] NXP:LS2088A RDB Board Support Wasim Khan
@ 2017-12-22 10:51 ` Wasim Khan
2017-12-22 10:51 ` [PATCH edk2-platforms 2/4] Silicon/Maxim: Added Support for DS3232 RTC Library Wasim Khan
` (3 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Wasim Khan @ 2017-12-22 10:51 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
This patch adds support of adding ArmPlatformLib
for NXP LS2088ARDB board
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
.../Library/PlatformLib/ArmPlatformLib.c | 106 +++++++++++
.../Library/PlatformLib/ArmPlatformLib.inf | 80 +++++++++
.../Library/PlatformLib/NxpQoriqLsHelper.S | 35 ++++
.../Library/PlatformLib/NxpQoriqLsMem.c | 196 +++++++++++++++++++++
4 files changed, 417 insertions(+)
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
new file mode 100644
index 0000000..90f14ba
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
@@ -0,0 +1,106 @@
+/** ArmPlatformLib.c
+*
+* Contains board initialization functions.
+*
+* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoard.c
+*
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Ppi/ArmMpCoreInfo.h>
+
+extern VOID SocInit (VOID);
+
+/**
+ Return the current Boot Mode
+
+ This function returns the boot reason on the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+ VOID
+ )
+{
+ return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+ Placeholder for Platform Initialization
+
+**/
+EFI_STATUS
+ArmPlatformInitialize (
+ IN UINTN MpId
+ )
+{
+ SocInit ();
+
+ return EFI_SUCCESS;
+}
+
+ARM_CORE_INFO LS2088aMpCoreInfoCTA72x4[] = {
+ {
+ // Cluster 0, Core 0
+ 0x0, 0x0,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)0,
+ (EFI_PHYSICAL_ADDRESS)0,
+ (EFI_PHYSICAL_ADDRESS)0,
+ (UINT64)0xFFFFFFFF
+ },
+};
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+ OUT UINTN *CoreCount,
+ OUT ARM_CORE_INFO **ArmCoreTable
+ )
+{
+ *CoreCount = sizeof (LS2088aMpCoreInfoCTA72x4) / sizeof (ARM_CORE_INFO);
+ *ArmCoreTable = LS2088aMpCoreInfoCTA72x4;
+
+ return EFI_SUCCESS;
+}
+
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &gArmMpCoreInfoPpiGuid,
+ &mMpCoreInfoPpi
+ }
+};
+
+VOID
+ArmPlatformGetPlatformPpiList (
+ OUT UINTN *PpiListSize,
+ OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
+ )
+{
+ *PpiListSize = sizeof (gPlatformPpiTable);
+ *PpiList = gPlatformPpiTable;
+}
+
+
+UINTN
+ArmPlatformGetCorePosition (
+ IN UINTN MpId
+ )
+{
+ return 1;
+}
diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
new file mode 100644
index 0000000..bac6d26
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
@@ -0,0 +1,80 @@
+#/** @file
+#
+# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#**/
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = PlatformLib
+ FILE_GUID = d1361285-8a47-421c-9efd-6b262c9093fc
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmPlatformLib
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ Platform/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ ArmLib
+ SocLib
+
+[Sources.common]
+ ArmPlatformLib.c
+ NxpQoriqLsHelper.S | GCC
+ NxpQoriqLsMem.c
+
+
+[Ppis]
+ gArmMpCoreInfoPpiGuid
+
+[FeaturePcd]
+ gEmbeddedTokenSpaceGuid.PcdCacheEnable
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdArmPrimaryCore
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2Size
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseSize
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1Size
+ gNxpQoriqLsTokenSpaceGuid.PcdDramMemSize
+ gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdDram2Size
+ gNxpQoriqLsTokenSpaceGuid.PcdMcHighMemSupport
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McRamSize
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McPortalBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McPortalSize
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2NiPortalsBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2NiPortalsSize
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalsBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalSize
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalsCacheSize
+
diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
new file mode 100644
index 0000000..1917b02
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
@@ -0,0 +1,35 @@
+#/** @file
+#
+# Copyright (c) 2012-2013, ARM Limited. All rights reserved.
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+#include <AsmMacroIoLibV8.h>
+#include <AutoGen.h>
+
+.text
+.align 2
+
+GCC_ASM_IMPORT(ArmReadMpidr)
+
+ASM_FUNC(ArmPlatformIsPrimaryCore)
+ tst x0, #3
+ cset x0, eq
+ ret
+
+ASM_FUNC(ArmPlatformPeiBootAction)
+ ret
+
+ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
+ MOV32 (x0, FixedPcdGet32(PcdArmPrimaryCore))
+ ldrh w0, [x0]
+ ret
diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
new file mode 100644
index 0000000..f2ea308
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
@@ -0,0 +1,196 @@
+/** NxpQoriqLsMem.c
+*
+* Board memory specific Library.
+*
+* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c
+*
+* Copyright (c) 2011, ARM Limited. All rights reserved.
+* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25
+
+//
+// Calculate the MC (Management Complex) base address and DDR size based on
+// if the MC is loaded in DDR low memory region or in DDR high memory region.
+//
+#if FixedPcdGetBool (PcdMcHighMemSupport)
+#define DDR_MEM_SIZE FixedPcdGet64 (PcdDramMemSize) - FixedPcdGet64 (PcdDpaa2McRamSize)
+#define MC_BASE_ADDR FixedPcdGet64 (PcdDram2BaseAddr) + DDR_MEM_SIZE
+#else
+#define DDR_MEM_SIZE FixedPcdGet64 (PcdDramMemSize)
+#define MC_BASE_ADDR FixedPcdGet64 (PcdDram1BaseAddr) - FixedPcdGet64 (PcdDpaa2McRamSize)
+#endif
+
+
+/**
+ Return the Virtual Memory Map of your platform
+
+ This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
+
+ @param VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
+ Virtual Memory mapping. This array must be ended by a zero-filled
+ entry
+
+**/
+
+VOID
+ArmPlatformGetVirtualMemoryMap (
+ IN ARM_MEMORY_REGION_DESCRIPTOR ** VirtualMemoryMap
+ )
+{
+ ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;
+ UINTN Index;
+ ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
+
+ Index = 0;
+
+ ASSERT (VirtualMemoryMap != NULL);
+
+ VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages (
+ EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
+
+ if (VirtualMemoryTable == NULL) {
+ return;
+ }
+
+ if (FeaturePcdGet (PcdCacheEnable) == TRUE) {
+ CacheAttributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+ } else {
+ CacheAttributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+ }
+
+ // DRAM1 (Must be 1st entry)
+ VirtualMemoryTable[Index].PhysicalBase = FixedPcdGet64 (PcdDram1BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDram1BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDram1Size);
+ VirtualMemoryTable[Index].Attributes = CacheAttributes;
+
+ // CCSR Space
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdCcsrBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdCcsrBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // IFC region 1
+ //
+ // A-009241 : Unaligned write transactions to IFC may result in corruption of data
+ // Affects : IFC
+ // Description: 16 byte unaligned write from system bus to IFC may result in extra unintended
+ // writes on external IFC interface that can corrupt data on external flash.
+ // Impact : Data corruption on external flash may happen in case of unaligned writes to
+ // IFC memory space.
+ // Workaround: Following are the workarounds:
+ // For write transactions from core, IFC interface memories (including IFC SRAM)
+ // should be configured as device type memory in MMU.
+ // For write transactions from non-core masters (like system DMA), the address
+ // should be 16 byte aligned and the data size should be multiple of 16 bytes.
+ //
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion1Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // IFC region 2
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion2Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // QSPI region 1
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQspiRegionSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+
+ // QSPI region 2
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQspiRegion2BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQspiRegion2BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQspiRegion2Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+
+ // DRAM2
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDram2BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDram2BaseAddr);
+ VirtualMemoryTable[Index].Length = DDR_MEM_SIZE;
+ VirtualMemoryTable[Index].Attributes = CacheAttributes;
+
+ // MC private DRAM
+ VirtualMemoryTable[++Index].PhysicalBase = MC_BASE_ADDR;
+ VirtualMemoryTable[Index].VirtualBase = MC_BASE_ADDR;
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDpaa2McRamSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // PCIe1
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp1BaseSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // PCIe2
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp2BaseSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // PCIe3
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp3BaseSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // PCIe4
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp4BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp4BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp4BaseSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // DPAA2 MC Portals region
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDpaa2McPortalBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDpaa2McPortalBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDpaa2McPortalSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // DPAA2 NI Portals region
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDpaa2NiPortalsBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDpaa2NiPortalsBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDpaa2NiPortalsSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // DPAA2 QBMAN Portals - cache enabled region
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDpaa2QBmanPortalsBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDpaa2QBmanPortalsBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDpaa2QBmanPortalsCacheSize);
+ VirtualMemoryTable[Index].Attributes = CacheAttributes;
+
+ // DPAA2 QBMAN Portals - cache inhibited region
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDpaa2QBmanPortalsBaseAddr) + FixedPcdGet64 (PcdDpaa2QBmanPortalsCacheSize);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDpaa2QBmanPortalsBaseAddr) + FixedPcdGet64 (PcdDpaa2QBmanPortalsCacheSize);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDpaa2QBmanPortalSize) - FixedPcdGet64 (PcdDpaa2QBmanPortalsCacheSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // End of Table
+ VirtualMemoryTable[++Index].PhysicalBase = 0;
+ VirtualMemoryTable[Index].VirtualBase = 0;
+ VirtualMemoryTable[Index].Length = 0;
+ VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
+
+ ASSERT ((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
+
+ *VirtualMemoryMap = VirtualMemoryTable;
+}
--
2.7.4
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH edk2-platforms 2/4] Silicon/Maxim: Added Support for DS3232 RTC Library
2017-12-22 10:51 [PATCH edk2-platforms 0/4] NXP:LS2088A RDB Board Support Wasim Khan
2017-12-22 10:51 ` [PATCH edk2-platforms 1/4] Platform/NXP: Add support for ArmPlatformLib Wasim Khan
@ 2017-12-22 10:51 ` Wasim Khan
2017-12-22 10:51 ` [PATCH edk2-platforms 3/4] Silicon/NXP:SocLib support for initialization of peripherals Wasim Khan
` (2 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Wasim Khan @ 2017-12-22 10:51 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
This patch adds support for DS3232 RTC Library
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h | 49 +++
Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c | 370 +++++++++++++++++++++
.../Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec | 31 ++
.../Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf | 50 +++
4 files changed, 500 insertions(+)
create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h
create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c
create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec
create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf
diff --git a/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h
new file mode 100644
index 0000000..cd1a321
--- /dev/null
+++ b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h
@@ -0,0 +1,49 @@
+/** Ds3232Rtc.h
+*
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __DS3232RTC_H__
+#define __DS3232RTC_H__
+
+//RTC time register
+#define DS3232_SEC_REG_ADDR 0x00
+#define DS3232_MIN_REG_ADDR 0x01
+#define DS3232_HR_REG_ADDR 0x02
+#define DS3232_DAY_REG_ADDR 0x03
+#define DS3232_DATE_REG_ADDR 0x04
+#define DS3232_MON_REG_ADDR 0x05
+#define DS3232_YR_REG_ADDR 0x06
+
+#define DS3232_SEC_BIT_CH 0x80 // Clock Halt (in Register 0)
+
+//RTC control register
+#define DS3232_CTL_REG_ADDR 0x0e
+#define DS3232_STAT_REG_ADDR 0x0f
+
+#define START_YEAR 1970
+#define END_YEAR 2070
+
+//TIME MASKS
+#define MASK_SEC 0x7F
+#define MASK_MIN 0x7F
+#define MASK_HOUR 0x3F
+#define MASK_DAY 0x3F
+#define MASK_MONTH 0x1F
+
+typedef struct {
+ UINTN OperationCount;
+ EFI_I2C_OPERATION SetAddressOp;
+ EFI_I2C_OPERATION GetSetDateTimeOp;
+} RTC_I2C_REQUEST;
+
+#endif // __DS3232RTC_H__
diff --git a/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c
new file mode 100644
index 0000000..a1f5226
--- /dev/null
+++ b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c
@@ -0,0 +1,370 @@
+/** Ds3232RtcLib.c
+* Implement EFI RealTimeClock via RTC Lib for DS3232 RTC.
+*
+* Based on RTC implementation available in
+* EmbeddedPkg/Library/TemplateRealTimeClockLib/RealTimeClockLib.c
+*
+* Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <PiDxe.h>
+#include <Base.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/RealTimeClockLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Protocol/I2cMaster.h>
+
+#include "Ds3232Rtc.h"
+
+STATIC VOID *mDriverEventRegistration;
+STATIC EFI_I2C_MASTER_PROTOCOL *mI2cMaster;
+
+/**
+ Read RTC register.
+
+ @param SlaveDeviceAddress Slave device address offset of RTC to be read.
+ @param RtcRegAddr Register offset of RTC to be read.
+
+ @retval Register Value read
+
+**/
+STATIC
+UINT8
+RtcRead (
+ IN UINT8 SlaveDeviceAddress,
+ IN UINT8 RtcRegAddr
+ )
+{
+ RTC_I2C_REQUEST Req;
+ EFI_STATUS Status;
+ UINT8 Val;
+
+ Val = 0;
+
+ Req.OperationCount = 2;
+
+ Req.SetAddressOp.Flags = 0;
+ Req.SetAddressOp.LengthInBytes = 1;
+ Req.SetAddressOp.Buffer = &RtcRegAddr;
+
+ Req.GetSetDateTimeOp.Flags = I2C_FLAG_READ;
+ Req.GetSetDateTimeOp.LengthInBytes = sizeof (Val);
+ Req.GetSetDateTimeOp.Buffer = &Val;
+
+ Status = mI2cMaster->StartRequest (mI2cMaster, SlaveDeviceAddress,
+ (VOID *)&Req,
+ NULL, NULL);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "RTC read error at Addr:0x%x\n", RtcRegAddr));
+ }
+
+ return Val;
+}
+
+/**
+ Write RTC register.
+
+ @param SlaveDeviceAddress Slave device address offset of RTC to be read.
+ @param RtcRegAddr Register offset of RTC to write.
+ @param Val Value to be written
+
+**/
+STATIC
+VOID
+RtcWrite (
+ IN UINT8 SlaveDeviceAddress,
+ IN UINT8 RtcRegAddr,
+ IN UINT8 Val
+ )
+{
+ RTC_I2C_REQUEST Req;
+ EFI_STATUS Status;
+
+ Req.OperationCount = 2;
+
+ Req.SetAddressOp.Flags = 0;
+ Req.SetAddressOp.LengthInBytes = 1;
+ Req.SetAddressOp.Buffer = &RtcRegAddr;
+
+ Req.GetSetDateTimeOp.Flags = 0;
+ Req.GetSetDateTimeOp.LengthInBytes = sizeof (Val);
+ Req.GetSetDateTimeOp.Buffer = &Val;
+
+ Status = mI2cMaster->StartRequest (mI2cMaster, SlaveDeviceAddress,
+ (VOID *)&Req,
+ NULL, NULL);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "RTC write error at Addr:0x%x\n", RtcRegAddr));
+ }
+}
+
+/**
+ Configure the MUX device connected to I2C.
+
+ @param RegValue Value to write on mux device register address
+
+**/
+VOID
+ConfigureMuxDevice (
+ IN UINT8 RegValue
+ )
+{
+ RtcWrite (FixedPcdGet8 (PcdMuxDeviceAddress), FixedPcdGet8 (PcdMuxControlRegOffset), RegValue);
+}
+
+/**
+ Returns the current time and date information, and the time-keeping capabilities
+ of the hardware platform.
+
+ @param Time A pointer to storage to receive a snapshot of the current time.
+ @param Capabilities An optional pointer to a buffer to receive the real time clock
+ device's capabilities.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER Time is NULL.
+ @retval EFI_DEVICE_ERROR The time could not be retrieved due to hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+LibGetTime (
+ OUT EFI_TIME *Time,
+ OUT EFI_TIME_CAPABILITIES *Capabilities
+ )
+{
+ EFI_STATUS Status;
+ UINT8 Second;
+ UINT8 Minute;
+ UINT8 Hour;
+ UINT8 Day;
+ UINT8 Month;
+ UINT8 Year;
+
+ if (mI2cMaster == NULL) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ Status = EFI_SUCCESS;
+
+ //
+ // Check if the I2C device is connected though a MUX device.
+ //
+ if (FixedPcdGetBool (PcdIsRtcDeviceMuxed)) {
+ // Switch to the channel connected to Ds3232 RTC
+ ConfigureMuxDevice (FixedPcdGet8 (PcdMuxRtcChannelValue));
+ }
+
+ Second = RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_SEC_REG_ADDR);
+ Minute = RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_MIN_REG_ADDR);
+ Hour = RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_HR_REG_ADDR);
+ Day = RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_DATE_REG_ADDR);
+ Month = RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_MON_REG_ADDR);
+ Year = RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_YR_REG_ADDR);
+
+ if (Second & DS3232_SEC_BIT_CH) {
+ DEBUG ((DEBUG_ERROR, "### Warning: RTC oscillator has stopped\n"));
+ /* clear the CH flag */
+ RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_SEC_REG_ADDR,
+ RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_SEC_REG_ADDR) & ~DS3232_SEC_BIT_CH);
+ Status = EFI_DEVICE_ERROR;
+ goto EXIT;
+ }
+
+ Time->Second = BcdToDecimal8 (Second & MASK_SEC);
+ Time->Minute = BcdToDecimal8 (Minute & MASK_MIN);
+ Time->Hour = BcdToDecimal8 (Hour & MASK_HOUR);
+ Time->Day = BcdToDecimal8 (Day & MASK_DAY);
+ Time->Month = BcdToDecimal8 (Month & MASK_MONTH);
+
+ //
+ // RTC can save year 1970 to 2069
+ // On writing Year, save year % 100
+ // On Reading reversing the operation e.g. 2012
+ // write = 12 (2012 % 100)
+ // read = 2012 (12 + 2000)
+ //
+ Time->Year = BcdToDecimal8 (Year) +
+ (BcdToDecimal8 (Year) >= 70 ? START_YEAR - 70 : END_YEAR -70);
+
+EXIT:
+ if (FixedPcdGetBool (PcdIsRtcDeviceMuxed)) {
+ // Switch to the default channel
+ ConfigureMuxDevice (FixedPcdGet8 (PcdMuxDefaultChannelValue));
+ }
+
+ return Status;
+}
+
+/**
+ Sets the current local time and date information.
+
+ @param Time A pointer to the current time.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetTime (
+ IN EFI_TIME *Time
+ )
+{
+ if (mI2cMaster == NULL) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ if (Time->Year < START_YEAR || Time->Year >= END_YEAR){
+ DEBUG ((DEBUG_ERROR, "WARNING: Year should be between 1970 and 2069!\n"));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Check if the I2C device is connected though a MUX device.
+ //
+ if (FixedPcdGetBool (PcdIsRtcDeviceMuxed)) {
+ // Switch to the channel connected to Ds3232 RTC
+ ConfigureMuxDevice (FixedPcdGet8 (PcdMuxRtcChannelValue));
+ }
+
+ RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_YR_REG_ADDR, DecimalToBcd8 (Time->Year % 100));
+ RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_MON_REG_ADDR, DecimalToBcd8 (Time->Month));
+ RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_DATE_REG_ADDR, DecimalToBcd8 (Time->Day));
+ RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_HR_REG_ADDR, DecimalToBcd8 (Time->Hour));
+ RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_MIN_REG_ADDR, DecimalToBcd8 (Time->Minute));
+ RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_SEC_REG_ADDR, DecimalToBcd8 (Time->Second));
+
+ if (FixedPcdGetBool (PcdIsRtcDeviceMuxed)) {
+ // Switch to the default channel
+ ConfigureMuxDevice (FixedPcdGet8 (PcdMuxDefaultChannelValue));
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Returns the current wakeup alarm clock setting.
+
+ @param Enabled Indicates if the alarm is currently enabled or disabled.
+ @param Pending Indicates if the alarm signal is pending and requires acknowledgement.
+ @param Time The current alarm setting.
+
+ @retval EFI_SUCCESS The alarm settings were returned.
+ @retval EFI_INVALID_PARAMETER Any parameter is NULL.
+ @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+LibGetWakeupTime (
+ OUT BOOLEAN *Enabled,
+ OUT BOOLEAN *Pending,
+ OUT EFI_TIME *Time
+ )
+{
+ // Not a required feature
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Sets the system wakeup alarm clock time.
+
+ @param Enabled Enable or disable the wakeup alarm.
+ @param Time If Enable is TRUE, the time to set the wakeup alarm for.
+
+ @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled. If
+ Enable is FALSE, then the wakeup alarm was disabled.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+ @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error.
+ @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetWakeupTime (
+ IN BOOLEAN Enabled,
+ OUT EFI_TIME *Time
+ )
+{
+ // Not a required feature
+ return EFI_UNSUPPORTED;
+}
+
+STATIC
+VOID
+I2cDriverRegistrationEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ EFI_STATUS Status;
+ EFI_I2C_MASTER_PROTOCOL *I2cMaster;
+ UINTN BusFrequency;
+
+ Status = gBS->LocateProtocol (&gEfiI2cMasterProtocolGuid, NULL, (VOID **)&I2cMaster);
+
+ gBS->CloseEvent (Event);
+
+ ASSERT_EFI_ERROR (Status);
+
+ Status = I2cMaster->Reset (I2cMaster);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: I2CMaster->Reset () failed - %r\n",
+ __FUNCTION__, Status));
+ return;
+ }
+
+ BusFrequency = FixedPcdGet16 (PcdI2cBusFrequency);
+ Status = I2cMaster->SetBusFrequency (I2cMaster, &BusFrequency);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: I2CMaster->SetBusFrequency () failed - %r\n",
+ __FUNCTION__, Status));
+ return;
+ }
+
+ mI2cMaster = I2cMaster;
+}
+
+/**
+ This is the declaration of an EFI image entry point. This can be the entry point to an application
+ written to this specification, an EFI boot service driver.
+
+ @param ImageHandle Handle that identifies the loaded image.
+ @param SystemTable System Table for this image.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+LibRtcInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ //
+ // Register a protocol registration notification callback on the driver
+ // binding protocol so we can attempt to connect our I2C master to it
+ // as soon as it appears.
+ //
+ EfiCreateProtocolNotifyEvent (
+ &gEfiI2cMasterProtocolGuid,
+ TPL_CALLBACK,
+ I2cDriverRegistrationEvent,
+ NULL,
+ &mDriverEventRegistration);
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec
new file mode 100644
index 0000000..4471d57
--- /dev/null
+++ b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec
@@ -0,0 +1,31 @@
+#/** @file
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ DEC_SPECIFICATION = 0x0001001A
+ PACKAGE_NAME = Ds3232RtcLib
+ PACKAGE_GUID = 0b4192f7-e404-4019-b2e5-1e6004da3313
+ PACKAGE_VERSION = 0.1
+
+[Guids]
+ gDs3232RtcLibTokenSpaceGuid = { 0x7960fc51, 0x0832, 0x4f0b, { 0xb4, 0x22, 0x53, 0x87, 0x03, 0xaa, 0x85, 0xda }}
+
+[PcdsFixedAtBuild]
+ gDs3232RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0|UINT8|0x00000001
+ gDs3232RtcLibTokenSpaceGuid.PcdI2cBusFrequency|0|UINT32|0x00000002
+ gDs3232RtcLibTokenSpaceGuid.PcdIsRtcDeviceMuxed|FALSE|BOOLEAN|0x00000003
+ gDs3232RtcLibTokenSpaceGuid.PcdMuxDeviceAddress|0|UINT8|0x00000004
+ gDs3232RtcLibTokenSpaceGuid.PcdMuxControlRegOffset|0|UINT8|0x00000005
+ gDs3232RtcLibTokenSpaceGuid.PcdMuxRtcChannelValue|0|UINT8|0x00000006
+ gDs3232RtcLibTokenSpaceGuid.PcdMuxDefaultChannelValue|0|UINT8|0x00000007
diff --git a/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf
new file mode 100644
index 0000000..836fc64
--- /dev/null
+++ b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf
@@ -0,0 +1,50 @@
+# @Ds3232RtcLib.inf
+#
+# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+# Copyright (c) 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = Ds3232RtcLib
+ FILE_GUID = 97f1f2c2-51e1-47ad-9660-70b33da1fe71
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RealTimeClockLib
+
+[Sources.common]
+ Ds3232RtcLib.c
+
+[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec
+
+[LibraryClasses]
+ DebugLib
+ UefiBootServicesTableLib
+ UefiLib
+
+[Protocols]
+ gEfiDriverBindingProtocolGuid ## CONSUMES
+ gEfiI2cMasterProtocolGuid ## CONSUMES
+
+[FixedPcd]
+ gDs3232RtcLibTokenSpaceGuid.PcdI2cSlaveAddress
+ gDs3232RtcLibTokenSpaceGuid.PcdI2cBusFrequency
+ gDs3232RtcLibTokenSpaceGuid.PcdIsRtcDeviceMuxed
+ gDs3232RtcLibTokenSpaceGuid.PcdMuxDeviceAddress
+ gDs3232RtcLibTokenSpaceGuid.PcdMuxControlRegOffset
+ gDs3232RtcLibTokenSpaceGuid.PcdMuxRtcChannelValue
+ gDs3232RtcLibTokenSpaceGuid.PcdMuxDefaultChannelValue
+
+[Depex]
+ gEfiI2cMasterProtocolGuid
--
2.7.4
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH edk2-platforms 3/4] Silicon/NXP:SocLib support for initialization of peripherals
2017-12-22 10:51 [PATCH edk2-platforms 0/4] NXP:LS2088A RDB Board Support Wasim Khan
2017-12-22 10:51 ` [PATCH edk2-platforms 1/4] Platform/NXP: Add support for ArmPlatformLib Wasim Khan
2017-12-22 10:51 ` [PATCH edk2-platforms 2/4] Silicon/Maxim: Added Support for DS3232 RTC Library Wasim Khan
@ 2017-12-22 10:51 ` Wasim Khan
2017-12-22 10:51 ` [PATCH edk2-platforms 4/4] Compilation : Add the fdf, dsc and dec files Wasim Khan
2018-01-02 15:55 ` [PATCH edk2-platforms 0/4] NXP:LS2088A RDB Board Support Ard Biesheuvel
4 siblings, 0 replies; 7+ messages in thread
From: Wasim Khan @ 2017-12-22 10:51 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
Added SocInit function that initializes peripherals
and print board and soc information for LS2088ARDB Board.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
.../LS2088aRdbPkg/Include/Library/PlatformLib.h | 28 ++++
Silicon/NXP/Chassis/Chassis.c | 32 ++++
Silicon/NXP/Chassis/Chassis.h | 17 ++
Silicon/NXP/Chassis/Chassis3/Chassis3.dec | 19 +++
Silicon/NXP/Chassis/Chassis3/Errata.c | 62 ++++++++
Silicon/NXP/Chassis/Chassis3/SerDes.h | 92 +++++++++++
Silicon/NXP/Chassis/Chassis3/Soc.c | 171 +++++++++++++++++++++
Silicon/NXP/Chassis/Chassis3/Soc.h | 159 +++++++++++++++++++
Silicon/NXP/Chassis/LS2088aSocLib.inf | 53 +++++++
Silicon/NXP/LS2088A/Include/SocSerDes.h | 67 ++++++++
10 files changed, 700 insertions(+)
create mode 100755 Platform/NXP/LS2088aRdbPkg/Include/Library/PlatformLib.h
create mode 100644 Silicon/NXP/Chassis/Chassis3/Chassis3.dec
create mode 100644 Silicon/NXP/Chassis/Chassis3/Errata.c
create mode 100644 Silicon/NXP/Chassis/Chassis3/SerDes.h
create mode 100644 Silicon/NXP/Chassis/Chassis3/Soc.c
create mode 100644 Silicon/NXP/Chassis/Chassis3/Soc.h
create mode 100644 Silicon/NXP/Chassis/LS2088aSocLib.inf
create mode 100644 Silicon/NXP/LS2088A/Include/SocSerDes.h
diff --git a/Platform/NXP/LS2088aRdbPkg/Include/Library/PlatformLib.h b/Platform/NXP/LS2088aRdbPkg/Include/Library/PlatformLib.h
new file mode 100755
index 0000000..15181c7
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/Include/Library/PlatformLib.h
@@ -0,0 +1,28 @@
+/** LS2088aRdb.h
+* Header defining the LS2088aRdb constants (Base addresses, sizes, flags)
+*
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __LS2088aRDB_PLATFORM_H__
+#define __LS2088aRDB_PLATFORM_H__
+
+#define DCSR_BASE 0x700000000ULL
+#define DCSR_USB_PHY1 0x4600000
+#define DCSR_USB_PHY2 0x4610000
+#define DCSR_USB_PHY_RX_OVRD_IN_HI 0x1006
+#define USB_PHY_RX_EQ_VAL_1 0x0000
+#define USB_PHY_RX_EQ_VAL_2 0x0080
+#define USB_PHY_RX_EQ_VAL_3 0x0380
+#define USB_PHY_RX_EQ_VAL_4 0x0b80
+
+#endif //__LS2088aRDB_PLATFORM_H__
diff --git a/Silicon/NXP/Chassis/Chassis.c b/Silicon/NXP/Chassis/Chassis.c
index a6a77c2..3d3a8b1 100644
--- a/Silicon/NXP/Chassis/Chassis.c
+++ b/Silicon/NXP/Chassis/Chassis.c
@@ -44,6 +44,7 @@ GurRead (
*/
STATIC CPU_TYPE CpuTypeList[] = {
CPU_TYPE_ENTRY (LS1043A, LS1043A, 4),
+ CPU_TYPE_ENTRY (LS2088A, LS2088A, 8),
};
/*
@@ -138,6 +139,37 @@ CpuNumCores (
}
UINT32
+QoriqCoreToCluster (
+ IN UINTN Core
+ )
+{
+ CCSR_GUR *GurBase;
+ UINTN ClusterIndex;
+ UINTN Count;
+ UINT32 Cluster;
+ UINT32 Type;
+ UINTN InitiatorIndex;
+
+ GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+ ClusterIndex = 0;
+ Count = 0;
+ do {
+ Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
+ for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
+ Type = InitiatorType (Cluster, InitiatorIndex);
+ if (Type) {
+ if (Count == Core)
+ return ClusterIndex;
+ Count++;
+ }
+ }
+ ClusterIndex++;
+ } while (CHECK_CLUSTER (Cluster));
+
+ return -1; // cannot identify the cluster
+}
+
+UINT32
QoriqCoreToType (
IN UINTN Core
)
diff --git a/Silicon/NXP/Chassis/Chassis.h b/Silicon/NXP/Chassis/Chassis.h
index 4bdb4d0..324bfe9 100644
--- a/Silicon/NXP/Chassis/Chassis.h
+++ b/Silicon/NXP/Chassis/Chassis.h
@@ -56,6 +56,7 @@ CpuMaskNext (
#define SVR_WO_E 0xFFFFFE
#define SVR_LS1043A 0x879200
+#define SVR_LS2088A 0x870901
#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
#define SVR_MINOR(svr) (((svr) >> 0) & 0xf)
@@ -141,4 +142,20 @@ CpuNumCores (
VOID
);
+/*
+ * Return the type of initiator for core/hardware accelerator for given core index.
+ */
+UINT32
+QoriqCoreToType (
+ IN UINTN Core
+ );
+
+/*
+ * Return the cluster of initiator for core/hardware accelerator for given core index.
+ */
+UINT32
+QoriqCoreToCluster (
+ IN UINTN Core
+ );
+
#endif /* __CHASSIS_H__ */
diff --git a/Silicon/NXP/Chassis/Chassis3/Chassis3.dec b/Silicon/NXP/Chassis/Chassis3/Chassis3.dec
new file mode 100644
index 0000000..a2cdca4
--- /dev/null
+++ b/Silicon/NXP/Chassis/Chassis3/Chassis3.dec
@@ -0,0 +1,19 @@
+#/** @file
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+
+[Includes]
+ .
diff --git a/Silicon/NXP/Chassis/Chassis3/Errata.c b/Silicon/NXP/Chassis/Chassis3/Errata.c
new file mode 100644
index 0000000..78b1472
--- /dev/null
+++ b/Silicon/NXP/Chassis/Chassis3/Errata.c
@@ -0,0 +1,62 @@
+/** @Errata.c
+*
+* Copyright (c) 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/ArmLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PlatformLib.h>
+
+/**
+ * A-009007: USB3PHY observing intermittent failure in receive compliance tests at
+ * higher jitter frequency using default register values
+ * Affects: USB
+ * Description: Receive compliance tests may fail intermittently at high jitter frequencies using default register
+ * values.
+ * Impact: Receive compliance test fails at default register setting.
+ **/
+
+STATIC
+VOID
+UsbErratumA009007 (
+ VOID
+ )
+{
+ VOID *UsbPhyRxOvrdInHi = (VOID *)(DCSR_BASE + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+ ArmDataMemoryBarrier ();
+ MmioWrite16 ((UINTN)UsbPhyRxOvrdInHi, USB_PHY_RX_EQ_VAL_1);
+ ArmDataMemoryBarrier ();
+ MmioWrite16 ((UINTN)UsbPhyRxOvrdInHi, USB_PHY_RX_EQ_VAL_2);
+ ArmDataMemoryBarrier ();
+ MmioWrite16 ((UINTN)UsbPhyRxOvrdInHi, USB_PHY_RX_EQ_VAL_3);
+ ArmDataMemoryBarrier ();
+ MmioWrite16 ((UINTN)UsbPhyRxOvrdInHi, USB_PHY_RX_EQ_VAL_4);
+ UsbPhyRxOvrdInHi = (VOID *)(DCSR_BASE + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+ ArmDataMemoryBarrier ();
+ MmioWrite16 ((UINTN)UsbPhyRxOvrdInHi, USB_PHY_RX_EQ_VAL_1);
+ ArmDataMemoryBarrier ();
+ MmioWrite16 ((UINTN)UsbPhyRxOvrdInHi, USB_PHY_RX_EQ_VAL_2);
+ ArmDataMemoryBarrier ();
+ MmioWrite16 ((UINTN)UsbPhyRxOvrdInHi, USB_PHY_RX_EQ_VAL_3);
+ ArmDataMemoryBarrier ();
+ MmioWrite16 ((UINTN)UsbPhyRxOvrdInHi, USB_PHY_RX_EQ_VAL_4);
+}
+
+VOID
+ApplyErratum (
+ VOID
+ )
+{
+ if (PcdGetBool (PcdUsbErratumA009007))
+ UsbErratumA009007 ();
+}
diff --git a/Silicon/NXP/Chassis/Chassis3/SerDes.h b/Silicon/NXP/Chassis/Chassis3/SerDes.h
new file mode 100644
index 0000000..4cb270a
--- /dev/null
+++ b/Silicon/NXP/Chassis/Chassis3/SerDes.h
@@ -0,0 +1,92 @@
+/** SerDes.h
+ The Header file of SerDes Module for Chassis 3
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __SERDES_H__
+#define __SERDES_H__
+
+#include <Uefi/UefiBaseType.h>
+
+#define SRDS_MAX_LANES 8
+
+//
+// SerDes lane protocols/devices
+//
+typedef enum {
+ NONE = 0,
+ PCIE1,
+ PCIE2,
+ PCIE3,
+ PCIE4,
+ SATA1,
+ SATA2,
+ XAUI1,
+ XAUI2,
+ XFI1,
+ XFI2,
+ XFI3,
+ XFI4,
+ XFI5,
+ XFI6,
+ XFI7,
+ XFI8,
+ SGMII1,
+ SGMII2,
+ SGMII3,
+ SGMII4,
+ SGMII5,
+ SGMII6,
+ SGMII7,
+ SGMII8,
+ SGMII9,
+ SGMII10,
+ SGMII11,
+ SGMII12,
+ SGMII13,
+ SGMII14,
+ SGMII15,
+ SGMII16,
+ QSGMII_A,
+ QSGMII_B,
+ QSGMII_C,
+ QSGMII_D,
+ // Number of entries in this enum
+ SERDES_PRTCL_COUNT
+} SERDES_PROTOCOL;
+
+typedef enum {
+ SRDS_1 = 0,
+ SRDS_2,
+ SRDS_MAX_NUM
+} SERDES_NUMBER;
+
+typedef struct {
+ UINT16 Protocol;
+ UINT8 SrdsLane[SRDS_MAX_LANES];
+} SERDES_CONFIG;
+
+typedef
+VOID
+SERDES_PROBE_LANES_CALLBACK (
+ IN SERDES_PROTOCOL LaneProtocol,
+ IN VOID *Arg
+ );
+
+VOID
+SerDesProbeLanes(
+ IN SERDES_PROBE_LANES_CALLBACK *SerDesLaneProbeCallback,
+ IN VOID *Arg
+ );
+
+#endif /* __SERDES_H */
diff --git a/Silicon/NXP/Chassis/Chassis3/Soc.c b/Silicon/NXP/Chassis/Chassis3/Soc.c
new file mode 100644
index 0000000..7e6fd08
--- /dev/null
+++ b/Silicon/NXP/Chassis/Chassis3/Soc.c
@@ -0,0 +1,171 @@
+/** @Soc.c
+ SoC specific Library containg functions to initialize various SoC components
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Chassis.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib/MemLibInternals.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PrintLib.h>
+#include <Library/SerialPortLib.h>
+
+#include "Soc.h"
+
+VOID
+GetSysInfo (
+ OUT SYS_INFO *PtrSysInfo
+ )
+{
+ UINT32 Index;
+ CCSR_GUR *GurBase;
+ CCSR_CLT_CTRL *ClkBase;
+ CCSR_CLK_CLUSTER *ClkGrp[2] = {
+ (void *) (FSL_CLK_GRPA_ADDR),
+ (void *) (FSL_CLK_GRPB_ADDR)
+ };
+
+ const UINT8 CoreCplxPll[16] = {
+ [0] = 0, // CC1 PPL / 1
+ [1] = 0, // CC1 PPL / 2
+ [2] = 0, // CC1 PPL / 4
+ [4] = 1, // CC2 PPL / 1
+ [5] = 1, // CC2 PPL / 2
+ [6] = 1, // CC2 PPL / 4
+ [8] = 2, // CC3 PPL / 1
+ [9] = 2, // CC3 PPL / 2
+ [10] = 2, // CC3 PPL / 4
+ [12] = 3, // CC4 PPL / 1
+ [13] = 3, // CC4 PPL / 2
+ [14] = 3, // CC4 PPL / 4
+ };
+
+ const UINT8 CoreCplxPllDivisor[16] = {
+ [0] = 1, // CC1 PPL / 1
+ [1] = 2, // CC1 PPL / 2
+ [2] = 4, // CC1 PPL / 4
+ [4] = 1, // CC2 PPL / 1
+ [5] = 2, // CC2 PPL / 2
+ [6] = 4, // CC2 PPL / 4
+ [8] = 1, // CC3 PPL / 1
+ [9] = 2, // CC3 PPL / 2
+ [10] = 4, // CC3 PPL / 4
+ [12] = 1, // CC4 PPL / 1
+ [13] = 2, // CC4 PPL / 2
+ [14] = 4, // CC4 PPL / 4
+ };
+
+ INT32 CcGroup[12] = FSL_CLUSTER_CLOCKS;
+ UINTN PllCount, Cluster;
+ UINTN FreqCPll[NUM_CC_PLLS];
+ UINTN PllRatio[NUM_CC_PLLS];
+ UINTN SysClk;
+ UINT32 Cpu, CPllSel, CplxPll;
+ VOID *offset;
+
+ InternalMemZeroMem (PtrSysInfo, sizeof (SYS_INFO));
+ GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+ ClkBase = (VOID *)PcdGet64 (PcdClkBaseAddr);
+ SysClk = CLK_FREQ;
+
+ PtrSysInfo->FreqSystemBus = SysClk;
+ PtrSysInfo->FreqDdrBus = PcdGet64 (PcdDdrClk);
+ PtrSysInfo->FreqDdrBus2 = PcdGet64 (PcdDdrClk);
+
+ PtrSysInfo->FreqSystemBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
+ CHASSIS3_RCWSR_0_SYS_PLL_RAT_SHIFT) &
+ CHASSIS3_RCWSR_0_SYS_PLL_RAT_MASK;
+
+ //
+ // Platform clock is half of platform PLL
+ //
+ PtrSysInfo->FreqSystemBus /= PcdGet32 (PcdPlatformFreqDiv);
+
+ PtrSysInfo->FreqDdrBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
+ CHASSIS3_RCWSR_0_MEM_PLL_RAT_SHIFT) &
+ CHASSIS3_RCWSR_0_MEM_PLL_RAT_MASK;
+ PtrSysInfo->FreqDdrBus2 *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
+ CHASSIS3_RCWSR_0_MEM2_PLL_RAT_SHIFT) &
+ CHASSIS3_RCWSR_0_MEM2_PLL_RAT_MASK;
+
+ for (PllCount = 0; PllCount < NUM_CC_PLLS; PllCount++) {
+ offset = (void *)((UINTN)ClkGrp[PllCount/3] +
+ __builtin_offsetof (CCSR_CLK_CLUSTER, PllnGsr[PllCount%3].Gsr));
+ PllRatio[PllCount] = (GurRead ((UINTN)offset) >> 1) & 0x3f;
+ FreqCPll[PllCount] = SysClk * PllRatio[PllCount];
+ }
+
+ ForEachCpu(Index, Cpu, CpuNumCores(), CpuMask()) {
+ Cluster = QoriqCoreToCluster (Cpu);
+ ASSERT_EFI_ERROR (Cluster);
+ CPllSel = (GurRead ((UINTN)&ClkBase->ClkCnCsr[Cluster].Csr) >> 27) & 0xf;
+ CplxPll = CoreCplxPll[CPllSel];
+ CplxPll += CcGroup[Cluster] - 1;
+ PtrSysInfo->FreqProcessor[Cpu] = FreqCPll[CplxPll] / CoreCplxPllDivisor[CPllSel];
+ }
+ PtrSysInfo->FreqSdhc = PtrSysInfo->FreqSystemBus/PcdGet32(PcdPlatformFreqDiv);
+}
+
+/**
+ Perform the early initialization.
+ This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
+
+**/
+VOID
+SocInit (
+ VOID
+ )
+{
+ CHAR8 Buffer[100];
+ UINTN CharCount;
+
+ //
+ // Apply Errata
+ //
+ ApplyErratum ();
+
+ //
+ // Initialize SMMU
+ //
+ SmmuInit();
+
+ //
+ // Initialize the Serial Port.
+ // Early serial port initialization is required to print RCW, Soc and CPU infomation at
+ // the begining of UEFI boot.
+ //
+ SerialPortInitialize ();
+
+ CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "\nUEFI firmware (version %s built at %a on %a)\n\r",
+ (CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);
+ SerialPortWrite ((UINT8 *) Buffer, CharCount);
+
+ //
+ // Print CPU information
+ //
+ PrintCpuInfo();
+
+ //
+ // Print Reset Controll Word
+ //
+ PrintRCW();
+
+ //
+ // Print Soc Personality information
+ //
+ PrintSoc();
+}
+
diff --git a/Silicon/NXP/Chassis/Chassis3/Soc.h b/Silicon/NXP/Chassis/Chassis3/Soc.h
new file mode 100644
index 0000000..44c2e07
--- /dev/null
+++ b/Silicon/NXP/Chassis/Chassis3/Soc.h
@@ -0,0 +1,159 @@
+/** Soc.h
+* Header defining the Base addresses, sizes, flags etc for chassis 1
+*
+* Copyright (c) 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __SOC_H__
+#define __SOC_H__
+
+#define MAX_CPUS 16
+#define FSL_CLK_GRPA_ADDR 0x01300000
+#define FSL_CLK_GRPB_ADDR 0x01310000
+#define NUM_CC_PLLS 6
+#define CLK_FREQ 100000000
+
+#define FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } /* LS208x */
+#define TP_CLUSTER_EOC_MASK 0x80000000 /* Mask for End of clusters */
+#define CHECK_CLUSTER(Cluster) ((Cluster & TP_CLUSTER_EOC_MASK) != TP_CLUSTER_EOC_MASK)
+
+// RCW SERDES MACRO
+#define RCWSR_INDEX 28
+#define RCWSR_SRDS1_PRTCL_MASK 0x00ff0000
+#define RCWSR_SRDS1_PRTCL_SHIFT 16
+#define RCWSR_SRDS2_PRTCL_MASK 0xff000000
+#define RCWSR_SRDS2_PRTCL_SHIFT 24
+
+// SMMU Defintions
+#define SMMU_BASE_ADDR 0x05000000
+#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
+#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10)
+#define SMMU_REG_IDR1 (SMMU_BASE_ADDR + 0x24)
+#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400)
+#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410)
+
+#define SACR_PAGESIZE_MASK 0x00010000
+#define SCR0_CLIENTPD_MASK 0x00000001
+#define SCR0_USFCFG_MASK 0x00000400
+
+typedef struct {
+ UINTN FreqProcessor[MAX_CPUS];
+ UINTN FreqSystemBus;
+ UINTN FreqDdrBus;
+ UINTN FreqDdrBus2;
+ UINTN FreqLocalBus;
+ UINTN FreqSdhc;
+ UINTN FreqFman[1];
+ UINTN FreqQman;
+ UINTN FreqPme;
+}SYS_INFO;
+
+///
+/// Device Configuration and Pin Control
+///
+typedef struct {
+ UINT32 PorSr1; // POR status register 1
+ UINT32 PorSr2; // POR status register 2
+ UINT8 Res008[0x20-0x8];
+ UINT32 GppOrCr1; // General-purpose POR configuration register
+ UINT32 GppOrCr2; // General-purpose POR configuration register 2
+ UINT32 DcfgFuseSr; // Fuse status register */
+ UINT32 GppOrCr3;
+ UINT32 GppOrCr4;
+ UINT8 Res034[0x70-0x34];
+ UINT32 DevDisr; // Device disable control register
+ UINT32 DevDisr2; // Device disable control register 2
+ UINT32 DevDisr3; // Device disable control register 3
+ UINT32 DevDisr4; // Device disable control register 4
+ UINT32 DevDisr5; // Device disable control register 5
+ UINT32 DevDisr6; // Device disable control register 6
+ UINT32 DevDisr7; // Device disable control register 7
+ UINT8 Res08c[0x90-0x8c];
+ UINT32 CoreDisrUpper; // CORE DISR Uppper for support of 64 cores
+ UINT32 CoreDisrLower; // CORE DISR Lower for support of 64 cores
+ UINT8 Res098[0xa0-0x98];
+ UINT32 Pvr; // Processor version
+ UINT32 Svr; // System version
+ UINT32 Mvr; // Manufacturing version
+ UINT8 Res0ac[0x100-0xac];
+ UINT32 RcwSr[32]; // Reset control word status
+#define CHASSIS3_RCWSR_0_SYS_PLL_RAT_SHIFT 2
+#define CHASSIS3_RCWSR_0_SYS_PLL_RAT_MASK 0x1f
+#define CHASSIS3_RCWSR_0_MEM_PLL_RAT_SHIFT 10
+#define CHASSIS3_RCWSR_0_MEM_PLL_RAT_MASK 0x3f
+#define CHASSIS3_RCWSR_0_MEM2_PLL_RAT_SHIFT 18
+#define CHASSIS3_RCWSR_0_MEM2_PLL_RAT_MASK 0x3f
+ UINT8 Res180[0x200-0x180];
+ UINT32 ScratchRw[32]; // Scratch Read/Write
+ UINT8 Res280[0x300-0x280];
+ UINT32 ScratchW1R[4]; // Scratch Read (Write once)
+ UINT8 Res310[0x400-0x310];
+ UINT32 BootLocPtrL; // Low addr : Boot location pointer
+ UINT32 BootLocPtrH; // High addr : Boot location pointer
+ UINT8 Res408[0x500-0x408];
+ UINT8 Res500[0x740-0x500];
+ UINT32 TpItyp[64];
+ struct {
+ UINT32 Upper;
+ UINT32 Lower;
+ } TpCluster[3];
+ UINT8 Res858[0x1000-0x858];
+} CCSR_GUR;
+
+///
+/// Clocking
+///
+typedef struct {
+ struct {
+ UINT32 Csr; // core cluster n clock control status
+ UINT8 Res04[0x20-0x04];
+ } ClkCnCsr[8];
+} CCSR_CLT_CTRL;
+
+///
+/// Clock Cluster
+///
+typedef struct {
+ struct {
+ UINT8 Res00[0x10];
+ UINT32 Csr; // core cluster n clock control status
+ UINT8 Res14[0x20-0x14];
+ } HwnCsr[3];
+ UINT8 Res60[0x80-0x60];
+ struct {
+ UINT32 Gsr; // core cluster n clock general status
+ UINT8 Res84[0xa0-0x84];
+ } PllnGsr[3];
+ UINT8 Rese0[0x100-0xe0];
+} CCSR_CLK_CLUSTER;
+
+VOID
+GetSysInfo (
+ OUT SYS_INFO *
+ );
+
+UINT32
+EFIAPI
+GurRead (
+ IN UINTN Address
+ );
+
+/**
+ Apply Chassis Specific Errata
+
+**/
+VOID
+ApplyErratum (
+ VOID
+ );
+
+#endif /* __SOC_H__ */
diff --git a/Silicon/NXP/Chassis/LS2088aSocLib.inf b/Silicon/NXP/Chassis/LS2088aSocLib.inf
new file mode 100644
index 0000000..4b7648b
--- /dev/null
+++ b/Silicon/NXP/Chassis/LS2088aSocLib.inf
@@ -0,0 +1,53 @@
+# @file
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = SocLib
+ FILE_GUID = 3b233a6a-0ee1-42a3-a7f7-c285b5ba80dc
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SocLib
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Platform/NXP/NxpQoriqLs.dec
+ Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec
+ Silicon/NXP/Chassis/Chassis3/Chassis3.dec
+ Silicon/NXP/LS2088A/LS2088A.dec
+
+[LibraryClasses]
+ ArmLib
+ BaseLib
+ BeIoLib
+ DebugLib
+ SerialPortLib
+
+[Sources.common]
+ Chassis.c
+ Chassis3/Soc.c
+ Chassis3/Errata.c
+ SerDes.c
+
+[FixedPcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
+ gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
+ gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled
+ gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
+ gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdDdrClk
+ gNxpQoriqLsTokenSpaceGuid.PcdUsbErratumA009007
diff --git a/Silicon/NXP/LS2088A/Include/SocSerDes.h b/Silicon/NXP/LS2088A/Include/SocSerDes.h
new file mode 100644
index 0000000..f631ccb
--- /dev/null
+++ b/Silicon/NXP/LS2088A/Include/SocSerDes.h
@@ -0,0 +1,67 @@
+/** @file
+ The Header file of SerDes Module for LS2088A
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __SOC_SERDES_H__
+#define __SOC_SERDES_H__
+
+#include <SerDes.h>
+
+SERDES_CONFIG SerDes1ConfigTbl[] = {
+ // SerDes 1
+ { 0x03, { PCIE2, PCIE2, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } },
+ { 0x05, { PCIE2, PCIE2, PCIE2, PCIE2, SGMII4, SGMII3, SGMII2, SGMII1 } },
+ { 0x07, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, SGMII1 } },
+ { 0x09, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, SGMII1 } },
+ { 0x0A, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, SGMII1 } },
+ { 0x0C, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, SGMII1 } },
+ { 0x0E, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, SGMII1 } },
+ { 0x26, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, XFI2, XFI1 } },
+ { 0x28, { SGMII8, SGMII7, SGMII6, SGMII5, XFI4, XFI3, XFI2, XFI1 } },
+ { 0x2A, { XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } },
+ { 0x2B, { SGMII8, SGMII7, SGMII6, SGMII5, XAUI1, XAUI1, XAUI1, XAUI1 } },
+ { 0x32, { XAUI2, XAUI2, XAUI2, XAUI2, XAUI1, XAUI1, XAUI1, XAUI1 } },
+ { 0x33, { PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_D, QSGMII_C, QSGMII_B, QSGMII_A } },
+ { 0x35, { QSGMII_D, QSGMII_C, QSGMII_B, PCIE2, XFI4, XFI3, XFI2, XFI1 } },
+ {}
+};
+
+SERDES_CONFIG SerDes2ConfigTbl[] = {
+ // SerDes 2
+ { 0x07, { SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, SGMII16 } },
+ { 0x09, { SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, SGMII16 } },
+ { 0x0A, { SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, SGMII16 } },
+ { 0x0C, { SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, SGMII16 } },
+ { 0x0E, { SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, SGMII16 } },
+ { 0x3D, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } },
+ { 0x3E, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } },
+ { 0x3F, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } },
+ { 0x40, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } },
+ { 0x41, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } },
+ { 0x42, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } },
+ { 0x43, { PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } },
+ { 0x44, { PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } },
+ { 0x45, { SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, PCIE4, PCIE4 } },
+ { 0x47, { PCIE3, SGMII10, SGMII11, SGMII12, PCIE4, SGMII14, SGMII15, SGMII16 } },
+ { 0x49, { SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1, SATA2 } },
+ { 0x4A, { SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1, SATA2 } },
+ {}
+};
+
+SERDES_CONFIG *SerDesConfigTbl[] = {
+ SerDes1ConfigTbl,
+ SerDes2ConfigTbl
+};
+
+#endif /* __SOC_SERDES_H */
--
2.7.4
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH edk2-platforms 4/4] Compilation : Add the fdf, dsc and dec files.
2017-12-22 10:51 [PATCH edk2-platforms 0/4] NXP:LS2088A RDB Board Support Wasim Khan
` (2 preceding siblings ...)
2017-12-22 10:51 ` [PATCH edk2-platforms 3/4] Silicon/NXP:SocLib support for initialization of peripherals Wasim Khan
@ 2017-12-22 10:51 ` Wasim Khan
2018-01-02 15:55 ` [PATCH edk2-platforms 0/4] NXP:LS2088A RDB Board Support Ard Biesheuvel
4 siblings, 0 replies; 7+ messages in thread
From: Wasim Khan @ 2017-12-22 10:51 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
Added firware device, description and declaration files for LS2088ARDB.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec | 29 ++++
Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc | 95 +++++++++++++
Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf | 197 +++++++++++++++++++++++++++
Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc | 98 +++++++++++++
Platform/NXP/NxpQoriqLs.dec | 1 +
Silicon/NXP/LS2088A/LS2088A.dec | 22 +++
Silicon/NXP/LS2088A/LS2088A.dsc | 101 ++++++++++++++
7 files changed, 543 insertions(+)
create mode 100644 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec
create mode 100755 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
create mode 100644 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
create mode 100644 Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc
create mode 100644 Silicon/NXP/LS2088A/LS2088A.dec
create mode 100644 Silicon/NXP/LS2088A/LS2088A.dsc
diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec
new file mode 100644
index 0000000..93d2e5a
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec
@@ -0,0 +1,29 @@
+# LS2088aRdbPkg.dec
+# LS2088a board package.
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+ PACKAGE_NAME = LS2088aRdbPkg
+ PACKAGE_GUID = 474e0c59-5f77-4060-82dd-9025ee4f4939
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+[Includes.common]
+ Include # Root include for the package
diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
new file mode 100755
index 0000000..dbc4d33
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
@@ -0,0 +1,95 @@
+# LS2088aRdbPkg.dsc
+#
+# LS2088ARDB Board package.
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ #
+ # Defines for default states. These can be changed on the command line.
+ # -D FLAG=VALUE
+ #
+ PLATFORM_NAME = LS2088aRdbPkg
+ PLATFORM_GUID = be06d8bc-05eb-44d6-b39f-191e93617ebd
+ OUTPUT_DIRECTORY = Build/LS2088aRdbPkg
+ FLASH_DEFINITION = edk2-platforms/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
+ DEFINE MC_HIGH_MEM = TRUE
+
+!include ../NxpQoriqLs.dsc
+!include ../../../Silicon/NXP/LS2088A/LS2088A.dsc
+
+[LibraryClasses.common]
+ ArmPlatformLib|edk2-platforms/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
+ ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
+ SerialPortLib|edk2-platforms/Platform/NXP/Library/DUartPortLib/DUartPortLib.inf
+ BeIoLib|edk2-platforms/Platform/NXP/Library/BeIoLib/BeIoLib.inf
+ SocLib|edk2-platforms/Silicon/NXP/Chassis/LS2088aSocLib.inf
+ RealTimeClockLib|edk2-platforms/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf
+
+[PcdsFixedAtBuild.common]
+ #
+ # Board Specific Pcds
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|TRUE
+ gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x2
+ gNxpQoriqLsTokenSpaceGuid.PcdDdrClk|133333333
+
+ #
+ # NV Storage PCDs.
+ #
+ gArmTokenSpaceGuid.PcdVFPEnabled|1
+ gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x580000000
+ gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x580300000
+
+ #
+ # I2C controller Pcds
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cBus|0
+
+ #
+ # RTC Pcds
+ #
+ gDs3232RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0x68
+ gDs3232RtcLibTokenSpaceGuid.PcdI2cBusFrequency|100000
+ gDs3232RtcLibTokenSpaceGuid.PcdIsRtcDeviceMuxed|TRUE
+ gDs3232RtcLibTokenSpaceGuid.PcdMuxDeviceAddress|0x75
+ gDs3232RtcLibTokenSpaceGuid.PcdMuxControlRegOffset|0x09
+ gDs3232RtcLibTokenSpaceGuid.PcdMuxRtcChannelValue|0x09
+ gDs3232RtcLibTokenSpaceGuid.PcdMuxDefaultChannelValue|0x08
+
+ #
+ # Errata Pcds
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdUsbErratumA009007|TRUE
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+
+
+ #
+ # WatchDog
+ #
+ ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
+
+ #
+ # I2c
+ #
+ edk2-platforms/Platform/NXP/Drivers/I2cDxe/I2cDxe.inf
diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
new file mode 100644
index 0000000..f5d2f0a
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
@@ -0,0 +1,197 @@
+# LS2088aRdbPkg.fdf
+#
+# FLASH layout file for LS2088a board.
+#
+# Copyright (c) 2016, Freescale Ltd. All rights reserved.
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into the Flash Device Image. Each FD section
+# defines one flash "device" image. A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash" image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.LS2088aRdb_EFI]
+BaseAddress = 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The base address of the FLASH Device.
+Size = 0x00100000|gArmTokenSpaceGuid.PcdFdSize #The size in bytes of the FLASH Device
+ErasePolarity = 1
+BlockSize = 0x1
+NumBlocks = 0x00100000
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+0x00000000|0x00100000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = FVMAIN_COMPACT
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+FvNameGuid = 1037c42b-8452-4c41-aac7-41e6c31468da
+BlockSize = 0x1
+NumBlocks = 0 # This FV gets compressed so make it just big enough
+FvAlignment = 8 # FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+ #
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)
+ #
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+ INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+ INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+ INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+
+ #
+ # Multiple Console IO support
+ #
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+ INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+ INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
+
+ #
+ # Network modules
+ #
+ INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+ INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+ INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+ INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+ INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+ INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+ INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+!if $(NETWORK_IP6_ENABLE) == TRUE
+ INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf
+ INF NetworkPkg/TcpDxe/TcpDxe.inf
+ INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf
+ INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
+ INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
+ INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
+!else
+ INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+!endif
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ INF FatPkg/FatPei/FatPei.inf
+ INF FatPkg/EnhancedFatDxe/Fat.inf
+
+ #
+ # UEFI application (Shell Embedded Boot Loader)
+ #
+ INF ShellPkg/Application/Shell/Shell.inf
+
+ #
+ # Bds
+ #
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+ INF edk2-platforms/Platform/NXP/Drivers/I2cDxe/I2cDxe.inf
+
+[FV.FVMAIN_COMPACT]
+FvAlignment = 8
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF ArmPlatformPkg/PrePi/PeiUniCore.inf
+
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FVMAIN
+ }
+ }
+
+!include $(WORKSPACE)/ArmVirtPkg/ArmVirtRules.fdf.inc
diff --git a/Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc b/Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc
new file mode 100644
index 0000000..e3cd598
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc
@@ -0,0 +1,98 @@
+## @file
+# FDF include file with FD definition that defines an empty variable store.
+#
+# Copyright (c) 2016, Freescale Semiconductor. All rights reserved.
+# Copyright (c) 2016, Linaro, Ltd. All rights reserved.
+# Copyright (C) 2014, Red Hat, Inc.
+# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+#
+# This program and the accompanying materials are licensed and made available
+# under the terms and conditions of the BSD License which accompanies this
+# distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+# IMPLIED.
+#
+##
+
+[FD.LS2088aRdbNv_EFI]
+
+BaseAddress = 0x580300000|gNxpQoriqLsTokenSpaceGuid.PcdNvFdBase #The base address of the FLASH device
+Size = 0x000C0000|gNxpQoriqLsTokenSpaceGuid.PcdNvFdSize #The size in bytes of the FLASH device
+ErasePolarity = 1
+BlockSize = 0x1
+NumBlocks = 0xC0000
+
+#
+# Place NV Storage just above Platform Data Base
+#
+DEFINE NVRAM_AREA_VARIABLE_BASE = 0x00000000
+DEFINE NVRAM_AREA_VARIABLE_SIZE = 0x00040000
+DEFINE FTW_WORKING_BASE = $(NVRAM_AREA_VARIABLE_BASE) + $(NVRAM_AREA_VARIABLE_SIZE)
+DEFINE FTW_WORKING_SIZE = 0x00040000
+DEFINE FTW_SPARE_BASE = $(FTW_WORKING_BASE) + $(FTW_WORKING_SIZE)
+DEFINE FTW_SPARE_SIZE = 0x00040000
+
+#############################################################################
+# LS2088ARDB NVRAM Area
+# LS2088ARDB NVRAM Area contains: Variable + FTW Working + FTW Spare
+#############################################################################
+
+
+$(NVRAM_AREA_VARIABLE_BASE)|$(NVRAM_AREA_VARIABLE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+#NV_VARIABLE_STORE
+DATA = {
+ ## This is the EFI_FIRMWARE_VOLUME_HEADER
+ # ZeroVector []
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ # FileSystemGuid: gEfiSystemNvDataFvGuid =
+ # { 0xFFF12B8D, 0x7696, 0x4C8B,
+ # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
+ 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+ 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+ # FvLength: 0xC0000
+ 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00,
+ # Signature "_FVH" # Attributes
+ 0x5f, 0x46, 0x56, 0x48, 0x36, 0x0E, 0x00, 0x00,
+ # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision
+ 0x48, 0x00, 0xFA, 0xF5, 0x00, 0x00, 0x00, 0x02,
+ # Blockmap[0]: 0x3 Blocks * 0x40000 Bytes / Block
+ 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
+ # Blockmap[1]: End
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ ## This is the VARIABLE_STORE_HEADER
+ # It is compatible with SECURE_BOOT_ENABLE == FALSE as well.
+ # Signature: gEfiAuthenticatedVariableGuid =
+ # { 0xaaf32c78, 0x947b, 0x439a,
+ # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}
+ 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
+ 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
+ # Size: 0x40000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
+ # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x3ffb8
+ # This can speed up the Variable Dispatch a bit.
+ 0xB8, 0xFF, 0x03, 0x00,
+ # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+ 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FTW_WORKING_BASE)|$(FTW_WORKING_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#NV_FTW_WORKING
+DATA = {
+ # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
+ # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
+ 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
+ 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
+ # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+ 0x5b, 0xe7, 0xc6, 0x86, 0xFE, 0xFF, 0xFF, 0xFF,
+ # WriteQueueSize: UINT64
+ 0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FTW_SPARE_BASE)|$(FTW_SPARE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+#NV_FTW_SPARE
diff --git a/Platform/NXP/NxpQoriqLs.dec b/Platform/NXP/NxpQoriqLs.dec
index 85a9784..a55ff7a 100644
--- a/Platform/NXP/NxpQoriqLs.dec
+++ b/Platform/NXP/NxpQoriqLs.dec
@@ -233,6 +233,7 @@
gNxpQoriqLsTokenSpaceGuid.PcdMdioBustCount|0x0|UINT8|0x000002EE
gNxpQoriqLsTokenSpaceGuid.PcdDpaa2Wriop1Mdio1Addr|0x0|UINT64|0x000002EF
gNxpQoriqLsTokenSpaceGuid.PcdDpaa2Wriop1Mdio2Addr|0x0|UINT64|0x000002F0
+ gNxpQoriqLsTokenSpaceGuid.PcdMcHighMemSupport|FALSE|BOOLEAN|0x000002F1
#
# USB Pcds
diff --git a/Silicon/NXP/LS2088A/LS2088A.dec b/Silicon/NXP/LS2088A/LS2088A.dec
new file mode 100644
index 0000000..8539c63
--- /dev/null
+++ b/Silicon/NXP/LS2088A/LS2088A.dec
@@ -0,0 +1,22 @@
+# LS2088A.dec
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+
+[Guids.common]
+ gNxpLs2088ATokenSpaceGuid = {0xaf770da7, 0x264c, 0x4857, {0x9d, 0xed, 0x56, 0x5e, 0x2c, 0x08, 0x7e, 0x26}}
+
+[Includes]
+ Include
diff --git a/Silicon/NXP/LS2088A/LS2088A.dsc b/Silicon/NXP/LS2088A/LS2088A.dsc
new file mode 100644
index 0000000..4d1b399
--- /dev/null
+++ b/Silicon/NXP/LS2088A/LS2088A.dsc
@@ -0,0 +1,101 @@
+# LS2088A.dsc
+# LS2088A Soc package.
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsDynamicDefault.common]
+
+ #
+ # ARM General Interrupt Controller
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x6000000
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x6100000
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x00
+
+[PcdsFixedAtBuild.common]
+
+ gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x0C000000
+ gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|266666666 #266MHz
+
+ ## Serial Terminal
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x21c0600
+
+ #
+ # ARM L2x0 PCDs
+ gArmTokenSpaceGuid.PcdL2x0ControllerBase|0x10900000
+
+ #
+ # UEFI Region in System Memory
+ #
+
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000
+
+ #
+ # CCSR Address Space and other attached Memories
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000
+ gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x1370000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x30000000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x10000000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x510000000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0xF0000000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x3EEA
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x20000000
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x10000000
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2BaseAddr|0x400000000
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2Size|0x10000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x2000000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x800000000 # 32 GB
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x2800000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x800000000 # 32 GB
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x3000000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x800000000 # 32 GB
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr|0x3800000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseSize|0x800000000 # 32 GB
+ gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExBase|0x8080000000 # Extended System Memory Base
+ gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExSize|0x0380000000 # 14GB Extended System Memory Size
+!if $(MC_HIGH_MEM) == TRUE # Management Complex loaded at the end of DDR2
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr|0x0080000000 # Actual base address (0x0080000000)
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1Size|0x0080000000 # 2 GB
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McRamSize|0x80000000 # 2GB (PcdDpaa2McRamSize must be 512MB aligned)
+ gNxpQoriqLsTokenSpaceGuid.PcdMcHighMemSupport|1
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x0080000000 # Actual base
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x0080000000 # 2G
+!else
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr|0x00A0000000 # Actual base address (0x0080000000) + 512MB
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1Size|0x0060000000 # 2GB - 512MB
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McRamSize|0x20000000 # 512MB (Fixed)
+ gNxpQoriqLsTokenSpaceGuid.PcdMcHighMemSupport|0
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00A0000000 # Actual base + 512MB
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x0060000000 # 2G - 512MB
+!endif
+ gNxpQoriqLsTokenSpaceGuid.PcdDramMemSize|0x380000000 # 14 GB
+ gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr|0x8080000000
+ gNxpQoriqLsTokenSpaceGuid.PcdDram2Size|0x8800000000 # 512 GB
+ gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr|0x3100000
+ gNxpQoriqLsTokenSpaceGuid.PcdUsbSize|0x10000
+ gNxpQoriqLsTokenSpaceGuid.PcdNumUsbController|2
+ gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x1E00000
+ gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x02140000
+ gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02000000
+ gNxpQoriqLsTokenSpaceGuid.PcdI2c1BaseAddr|0x02010000
+ gNxpQoriqLsTokenSpaceGuid.PcdI2c2BaseAddr|0x02020000
+ gNxpQoriqLsTokenSpaceGuid.PcdI2c3BaseAddr|0x02030000
+ gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
+
+##
--
2.7.4
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH edk2-platforms 0/4] NXP:LS2088A RDB Board Support
2017-12-22 10:51 [PATCH edk2-platforms 0/4] NXP:LS2088A RDB Board Support Wasim Khan
` (3 preceding siblings ...)
2017-12-22 10:51 ` [PATCH edk2-platforms 4/4] Compilation : Add the fdf, dsc and dec files Wasim Khan
@ 2018-01-02 15:55 ` Ard Biesheuvel
2018-01-03 4:52 ` Meenakshi Aggarwal
4 siblings, 1 reply; 7+ messages in thread
From: Ard Biesheuvel @ 2018-01-02 15:55 UTC (permalink / raw)
To: Wasim Khan, Meenakshi Aggarwal
Cc: Leif Lindholm, Kinney, Michael D, edk2-devel@lists.01.org,
Udit Kumar, Varun Sethi
Hello Wasim, Udit, Meenakshi,
I kind of lost track of all the patches you have been sending over the
past month or so.
Could one of you please send a quick summary of all the patches that
are in flight at the moment, and for which platforms?
Thanks,
Ard.
On 22 December 2017 at 10:51, Wasim Khan <wasim.khan@nxp.com> wrote:
> In Silicon/NXP, we are keeping our SoC specific information and remaining code will be kept in Platform/NXP.
>
> Following patches will add support of NXP LS2088A RDB board in edk2-platforms.
>
> Platform/NXP/LS2088aRdbPkg will host .dsc and .fdf files to support compilation for LS2088A RDB board.
>
> Looking forward for your kind support in upstreaming LS2088 RDB board support in edk2-platforms.
>
> Wasim Khan (4):
> Platform/NXP: Add support for ArmPlatformLib
> Silicon/Maxim: Added Support for DS3232 RTC Library
> Silicon/NXP:SocLib support for initialization of peripherals
> Compilation : Add the fdf, dsc and dec files.
>
> .../LS2088aRdbPkg/Include/Library/PlatformLib.h | 28 ++
> Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec | 29 ++
> Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc | 95 ++++++
> Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf | 197 +++++++++++
> .../Library/PlatformLib/ArmPlatformLib.c | 106 ++++++
> .../Library/PlatformLib/ArmPlatformLib.inf | 80 +++++
> .../Library/PlatformLib/NxpQoriqLsHelper.S | 35 ++
> .../Library/PlatformLib/NxpQoriqLsMem.c | 196 +++++++++++
> Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc | 98 ++++++
> Platform/NXP/NxpQoriqLs.dec | 1 +
> Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h | 49 +++
> Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c | 370 +++++++++++++++++++++
> .../Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec | 31 ++
> .../Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf | 50 +++
> Silicon/NXP/Chassis/Chassis.c | 32 ++
> Silicon/NXP/Chassis/Chassis.h | 17 +
> Silicon/NXP/Chassis/Chassis3/Chassis3.dec | 19 ++
> Silicon/NXP/Chassis/Chassis3/Errata.c | 62 ++++
> Silicon/NXP/Chassis/Chassis3/SerDes.h | 92 +++++
> Silicon/NXP/Chassis/Chassis3/Soc.c | 171 ++++++++++
> Silicon/NXP/Chassis/Chassis3/Soc.h | 159 +++++++++
> Silicon/NXP/Chassis/LS2088aSocLib.inf | 53 +++
> Silicon/NXP/LS2088A/Include/SocSerDes.h | 67 ++++
> Silicon/NXP/LS2088A/LS2088A.dec | 22 ++
> Silicon/NXP/LS2088A/LS2088A.dsc | 101 ++++++
> 25 files changed, 2160 insertions(+)
> create mode 100755 Platform/NXP/LS2088aRdbPkg/Include/Library/PlatformLib.h
> create mode 100644 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec
> create mode 100755 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
> create mode 100644 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> create mode 100644 Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc
> create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h
> create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c
> create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec
> create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf
> create mode 100644 Silicon/NXP/Chassis/Chassis3/Chassis3.dec
> create mode 100644 Silicon/NXP/Chassis/Chassis3/Errata.c
> create mode 100644 Silicon/NXP/Chassis/Chassis3/SerDes.h
> create mode 100644 Silicon/NXP/Chassis/Chassis3/Soc.c
> create mode 100644 Silicon/NXP/Chassis/Chassis3/Soc.h
> create mode 100644 Silicon/NXP/Chassis/LS2088aSocLib.inf
> create mode 100644 Silicon/NXP/LS2088A/Include/SocSerDes.h
> create mode 100644 Silicon/NXP/LS2088A/LS2088A.dec
> create mode 100644 Silicon/NXP/LS2088A/LS2088A.dsc
>
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH edk2-platforms 0/4] NXP:LS2088A RDB Board Support
2018-01-02 15:55 ` [PATCH edk2-platforms 0/4] NXP:LS2088A RDB Board Support Ard Biesheuvel
@ 2018-01-03 4:52 ` Meenakshi Aggarwal
0 siblings, 0 replies; 7+ messages in thread
From: Meenakshi Aggarwal @ 2018-01-03 4:52 UTC (permalink / raw)
To: Ard Biesheuvel, Wasim Khan, Meenakshi Aggarwal
Cc: Leif Lindholm, Kinney, Michael D, edk2-devel@lists.01.org,
Udit Kumar, Varun Sethi
Hi Ard,
Thanks for your time.
Below is the sequence in which we have sent the patches.
1. [PATCH edk2-platforms] [PATCH v3 0/9] Platform/NXP [27/11/2017] V3
This patch-set adds support for LS1043 platform, it includes patches for platform initialization and all necessary drivers to support architecture protocols.
2. [PATCH 0/4] Platform/NXP-Adding NXP NOR IP [19/12/2017] V2
This patch-set adds support for IFC NOR driver and enables it for LS1043 Soc.
3. [PATCH 0/4] Platform/NXP-Add LS1046A RDB Board Support [19/12/2017] V2
This patch-set adds support for LS1046 platform, it includes patches for platform initialization and all necessary drivers to support architecture protocols.
4. [PATCH 0/3] Platform/NXP-Adding NXP MMC Host Driver [1/12/2017] V1
This patch-set adds support for MMC Host driver and enables it for LS1043 Soc.
5. [PATCH edk2-platforms 0/3] Platform/NXP-Added NXP PCI Host Bridge Driver [22/12/2017] V1
This patch-set adds support for PCI Host bridge driver and enables it for LS1043 Soc.
V2 is in progress on basis of your comments.
6. [PATCH edk2-platforms 0/4] NXP:LS2088A RDB Board Support [22/12/2017] V1
This patch-set adds support for LS2088 platform, it includes patches for platform initialization and all necessary drivers to support architecture protocols.
7. [PATCH edk2-platforms 0/3] Cover letter:Pci Emulation and SATA support [22/12/2017] V1
This patch-set adds support for SATA on PCI Emulation layer and enables it for LS1046 Soc.
V2 in progress on basis of your comment (using NonDiscoverablePciDevice Layer rather Pci Emulation layer).
Please let us know if you need any other information.
Thanks,
NXP Team
> -----Original Message-----
> From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org]
> Sent: Tuesday, January 02, 2018 9:26 PM
> To: Wasim Khan <wasim.khan@nxp.com>; Meenakshi Aggarwal
> <meenakshi.aggarwal@freescale.com>
> Cc: Leif Lindholm <leif.lindholm@linaro.org>; Kinney, Michael D
> <michael.d.kinney@intel.com>; edk2-devel@lists.01.org; Udit Kumar
> <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>
> Subject: Re: [PATCH edk2-platforms 0/4] NXP:LS2088A RDB Board Support
>
> Hello Wasim, Udit, Meenakshi,
>
> I kind of lost track of all the patches you have been sending over the
> past month or so.
> Could one of you please send a quick summary of all the patches that
> are in flight at the moment, and for which platforms?
>
> Thanks,
> Ard.
>
>
> On 22 December 2017 at 10:51, Wasim Khan <wasim.khan@nxp.com> wrote:
> > In Silicon/NXP, we are keeping our SoC specific information and remaining
> code will be kept in Platform/NXP.
> >
> > Following patches will add support of NXP LS2088A RDB board in edk2-
> platforms.
> >
> > Platform/NXP/LS2088aRdbPkg will host .dsc and .fdf files to support
> compilation for LS2088A RDB board.
> >
> > Looking forward for your kind support in upstreaming LS2088 RDB board
> support in edk2-platforms.
> >
> > Wasim Khan (4):
> > Platform/NXP: Add support for ArmPlatformLib
> > Silicon/Maxim: Added Support for DS3232 RTC Library
> > Silicon/NXP:SocLib support for initialization of peripherals
> > Compilation : Add the fdf, dsc and dec files.
> >
> > .../LS2088aRdbPkg/Include/Library/PlatformLib.h | 28 ++
> > Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec | 29 ++
> > Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc | 95 ++++++
> > Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf | 197 +++++++++++
> > .../Library/PlatformLib/ArmPlatformLib.c | 106 ++++++
> > .../Library/PlatformLib/ArmPlatformLib.inf | 80 +++++
> > .../Library/PlatformLib/NxpQoriqLsHelper.S | 35 ++
> > .../Library/PlatformLib/NxpQoriqLsMem.c | 196 +++++++++++
> > Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc | 98 ++++++
> > Platform/NXP/NxpQoriqLs.dec | 1 +
> > Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h | 49 +++
> > Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c | 370
> +++++++++++++++++++++
> > .../Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec | 31 ++
> > .../Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf | 50 +++
> > Silicon/NXP/Chassis/Chassis.c | 32 ++
> > Silicon/NXP/Chassis/Chassis.h | 17 +
> > Silicon/NXP/Chassis/Chassis3/Chassis3.dec | 19 ++
> > Silicon/NXP/Chassis/Chassis3/Errata.c | 62 ++++
> > Silicon/NXP/Chassis/Chassis3/SerDes.h | 92 +++++
> > Silicon/NXP/Chassis/Chassis3/Soc.c | 171 ++++++++++
> > Silicon/NXP/Chassis/Chassis3/Soc.h | 159 +++++++++
> > Silicon/NXP/Chassis/LS2088aSocLib.inf | 53 +++
> > Silicon/NXP/LS2088A/Include/SocSerDes.h | 67 ++++
> > Silicon/NXP/LS2088A/LS2088A.dec | 22 ++
> > Silicon/NXP/LS2088A/LS2088A.dsc | 101 ++++++
> > 25 files changed, 2160 insertions(+)
> > create mode 100755
> Platform/NXP/LS2088aRdbPkg/Include/Library/PlatformLib.h
> > create mode 100644 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec
> > create mode 100755 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
> > create mode 100644 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
> > create mode 100644
> Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
> > create mode 100644
> Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> > create mode 100644
> Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
> > create mode 100644
> Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> > create mode 100644 Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc
> > create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h
> > create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c
> > create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec
> > create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf
> > create mode 100644 Silicon/NXP/Chassis/Chassis3/Chassis3.dec
> > create mode 100644 Silicon/NXP/Chassis/Chassis3/Errata.c
> > create mode 100644 Silicon/NXP/Chassis/Chassis3/SerDes.h
> > create mode 100644 Silicon/NXP/Chassis/Chassis3/Soc.c
> > create mode 100644 Silicon/NXP/Chassis/Chassis3/Soc.h
> > create mode 100644 Silicon/NXP/Chassis/LS2088aSocLib.inf
> > create mode 100644 Silicon/NXP/LS2088A/Include/SocSerDes.h
> > create mode 100644 Silicon/NXP/LS2088A/LS2088A.dec
> > create mode 100644 Silicon/NXP/LS2088A/LS2088A.dsc
> >
> > --
> > 2.7.4
> >
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2018-01-03 4:47 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-12-22 10:51 [PATCH edk2-platforms 0/4] NXP:LS2088A RDB Board Support Wasim Khan
2017-12-22 10:51 ` [PATCH edk2-platforms 1/4] Platform/NXP: Add support for ArmPlatformLib Wasim Khan
2017-12-22 10:51 ` [PATCH edk2-platforms 2/4] Silicon/Maxim: Added Support for DS3232 RTC Library Wasim Khan
2017-12-22 10:51 ` [PATCH edk2-platforms 3/4] Silicon/NXP:SocLib support for initialization of peripherals Wasim Khan
2017-12-22 10:51 ` [PATCH edk2-platforms 4/4] Compilation : Add the fdf, dsc and dec files Wasim Khan
2018-01-02 15:55 ` [PATCH edk2-platforms 0/4] NXP:LS2088A RDB Board Support Ard Biesheuvel
2018-01-03 4:52 ` Meenakshi Aggarwal
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox