From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
To: <ard.biesheuvel@linaro.org>, <leif.lindholm@linaro.org>,
<michael.d.kinney@intel.com>, <edk2-devel@lists.01.org>
Subject: [PATCH edk2-platforms 2/3] PciEmulation : Add support for Pci Emulation layer.
Date: Fri, 22 Dec 2017 17:46:43 +0530 [thread overview]
Message-ID: <1513945005-30002-3-git-send-email-meenakshi.aggarwal@nxp.com> (raw)
In-Reply-To: <1513945005-30002-1-git-send-email-meenakshi.aggarwal@nxp.com>
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SATA and USB will use this pci emulation layer
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Platform/NXP/Drivers/PciEmulation/PciEmulation.c | 624 +++++++++++++++++++++
Platform/NXP/Drivers/PciEmulation/PciEmulation.h | 306 ++++++++++
Platform/NXP/Drivers/PciEmulation/PciEmulation.inf | 54 ++
.../NXP/Drivers/PciEmulation/PciRootBridgeIo.c | 286 ++++++++++
Platform/NXP/NxpQoriqLs.dec | 9 +-
5 files changed, 1277 insertions(+), 2 deletions(-)
create mode 100644 Platform/NXP/Drivers/PciEmulation/PciEmulation.c
create mode 100755 Platform/NXP/Drivers/PciEmulation/PciEmulation.h
create mode 100644 Platform/NXP/Drivers/PciEmulation/PciEmulation.inf
create mode 100644 Platform/NXP/Drivers/PciEmulation/PciRootBridgeIo.c
diff --git a/Platform/NXP/Drivers/PciEmulation/PciEmulation.c b/Platform/NXP/Drivers/PciEmulation/PciEmulation.c
new file mode 100644
index 0000000..6635eb4
--- /dev/null
+++ b/Platform/NXP/Drivers/PciEmulation/PciEmulation.c
@@ -0,0 +1,624 @@
+/** PciEmulation.c
+ Provides all functions of PCI Host Bridge Resource Allocation Protocol
+
+ Reference taken from PCI Emulation implementation in
+ Omap35xxPkg/PciEmulation/
+
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PciEmulation.h"
+
+EFI_PCI_IO_DEVICE_PATH PciIoDevicePathTemplate =
+{
+ {
+ { ACPI_DEVICE_PATH, ACPI_DP, { sizeof (ACPI_HID_DEVICE_PATH), 0 } },
+ EISA_PNP_ID(0x0A03), // HID
+ 0 // UID
+ },
+ {
+ { HARDWARE_DEVICE_PATH, HW_PCI_DP, { sizeof (PCI_DEVICE_PATH), 0 } },
+ 0,
+ 0
+ },
+ { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0} }
+};
+
+EFI_STATUS
+PciIoPollMem (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 BarIndex,
+ IN UINT64 Offset,
+ IN UINT64 Mask,
+ IN UINT64 Value,
+ IN UINT64 Delay,
+ OUT UINT64 *Result
+ )
+{
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+PciIoMemRead (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 BarIndex,
+ IN UINT64 Offset,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ EFI_PCI_IO_PRIVATE_DATA *Private;
+
+ Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This);
+
+ return PciRootBridgeIoMemRead (&Private->RootBridge.Io,
+ (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
+ Private->ConfigSpace->Device.Bar[0] + Offset,
+ Count,
+ Buffer
+ );
+}
+
+EFI_STATUS
+PciIoMemWrite (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 BarIndex,
+ IN UINT64 Offset,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ EFI_PCI_IO_PRIVATE_DATA *Private;
+
+ Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This);
+
+ return PciRootBridgeIoMemWrite (&Private->RootBridge.Io,
+ (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
+ Private->ConfigSpace->Device.Bar[0] + Offset,
+ Count,
+ Buffer
+ );
+}
+
+EFI_STATUS
+PciIoIoWrite (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 BarIndex,
+ IN UINT64 Offset,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Enable a PCI driver to read PCI controller registers in PCI configuration space.
+
+ @param[in] This A pointer to the EFI_PCI_IO_PROTOCOL instance.
+ @param[in] Width Signifies the width of the memory operations.
+ @param[in] Offset The offset within the PCI configuration space for
+ the PCI controller.
+ @param[in] Count The number of PCI configuration operations to
+ perform. Bytes moved is Width size * Count,
+ starting at Offset.
+
+ @param[in out] Buffer The destination buffer to store the results.
+
+ @retval EFI_SUCCESS The data was read from the PCI controller.
+ @retval EFI_INVALID_PARAMETER "Width" is invalid.
+ @retval EFI_INVALID_PARAMETER "Buffer" is NULL.
+
+**/
+EFI_STATUS
+PciIoPciRead (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT32 Offset,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ EFI_PCI_IO_PRIVATE_DATA *Private;
+ EFI_STATUS Status;
+ UINT64 Address;
+
+ Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This);
+
+ if ((Width < 0) || (Width >= EfiPciIoWidthMaximum) || (Buffer == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Address = (UINT64)((UINT8 *)Private->ConfigSpace + Offset);
+ Status = PciRootBridgeIoMemRW (FALSE,
+ (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,
+ Address,
+ Count,
+ Buffer
+ );
+
+ return Status;
+}
+
+/**
+ Enable a PCI driver to write PCI controller registers in PCI configuration space.
+
+ @param[in] This A pointer to the EFI_PCI_IO_PROTOCOL instance.
+ @param[in] Width Signifies the width of the memory operations.
+ @param[in] Offset The offset within the PCI configuration space for
+ the PCI controller.
+ @param[in] Count The number of PCI configuration operations to
+ perform. Bytes moved is Width size * Count,
+ starting at Offset.
+
+ @param[in out] Buffer The source buffer to write data from.
+
+ @retval EFI_SUCCESS The data was read from the PCI controller.
+ @retval EFI_INVALID_PARAMETER "Width" is invalid.
+ @retval EFI_INVALID_PARAMETER "Buffer" is NULL.
+
+**/
+EFI_STATUS
+PciIoPciWrite (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT32 Offset,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ EFI_PCI_IO_PRIVATE_DATA *Private;
+
+ Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This);
+
+ if ((Width < 0) || (Width >= EfiPciIoWidthMaximum) || (Buffer == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return PciRootBridgeIoMemRW (TRUE,
+ (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
+ (UINT64)(Private->ConfigSpace + Offset),
+ Count,
+ Buffer
+ );
+}
+
+EFI_STATUS
+PciIoCopyMem (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 DestBarIndex,
+ IN UINT64 DestOffset,
+ IN UINT8 SrcBarIndex,
+ IN UINT64 SrcOffset,
+ IN UINTN Count
+ )
+{
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+PciIoMap (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_OPERATION Operation,
+ IN VOID *HostAddress,
+ IN OUT UINTN *NumberOfBytes,
+ OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
+ OUT VOID **Mapping
+ )
+{
+ DMA_MAP_OPERATION DmaOperation;
+
+ if (Operation == EfiPciIoOperationBusMasterRead) {
+ DmaOperation = MapOperationBusMasterRead;
+ } else if (Operation == EfiPciIoOperationBusMasterWrite) {
+ DmaOperation = MapOperationBusMasterWrite;
+ } else if (Operation == EfiPciIoOperationBusMasterCommonBuffer) {
+ DmaOperation = MapOperationBusMasterCommonBuffer;
+ } else {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return DmaMap (DmaOperation, HostAddress, NumberOfBytes, DeviceAddress, Mapping);
+}
+
+EFI_STATUS
+PciIoUnmap (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN VOID *Mapping
+ )
+{
+ return DmaUnmap (Mapping);
+}
+
+/**
+ Allocate pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer
+ mapping.
+
+ @param[in] This A pointer to the EFI_PCI_IO_PROTOCOL instance.
+ @param[in] Type This parameter is not used and must be ignored.
+ @param[in] MemoryType The type of memory to allocate, EfiBootServicesData or
+ EfiRuntimeServicesData.
+ @param[in] Pages The number of pages to allocate.
+ @param[out] HostAddress A pointer to store the base system memory address of
+ the allocated range.
+ @param[in] Attributes The requested bit mask of attributes for the allocated
+ range. Only the attributes,
+ EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE and
+ EFI_PCI_ATTRIBUTE_MEMORY_CACHED may be used with this
+ function. If any other bits are set, then EFI_UNSUPPORTED
+ is returned. This function ignores this bit mask.
+
+ @retval EFI_SUCCESS The requested memory pages were allocated.
+ @retval EFI_INVALID_PARAMETER HostAddress is NULL.
+ @retval EFI_INVALID_PARAMETER MemoryType is invalid.
+ @retval EFI_UNSUPPORTED Attributes is unsupported.
+ @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
+
+**/
+EFI_STATUS
+PciIoAllocateBuffer (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_ALLOCATE_TYPE Type,
+ IN EFI_MEMORY_TYPE MemoryType,
+ IN UINTN Pages,
+ OUT VOID **HostAddress,
+ IN UINT64 Attributes
+ )
+{
+ if (Attributes &
+ (~(EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE |
+ EFI_PCI_ATTRIBUTE_MEMORY_CACHED))) {
+ return EFI_UNSUPPORTED;
+ }
+
+ return DmaAllocateBuffer (MemoryType, Pages, HostAddress);
+}
+
+/**
+ Frees memory that was allocated with AllocateBuffer().
+
+ The FreeBuffer() function frees memory that was allocated with AllocateBuffer().
+
+ @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param Pages The number of pages to free.
+ @param HostAddress The base system memory address of the allocated range.
+
+ @retval EFI_SUCCESS The requested memory pages were freed.
+ @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
+ was not allocated with AllocateBuffer().
+
+**/
+
+EFI_STATUS
+PciIoFreeBuffer (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN UINTN Pages,
+ IN VOID *HostAddress
+ )
+{
+ return DmaFreeBuffer (Pages, HostAddress);
+}
+
+EFI_STATUS
+PciIoFlush (
+ IN EFI_PCI_IO_PROTOCOL *This
+ )
+{
+ //
+ // not supported yet
+ //
+ return EFI_SUCCESS;
+}
+
+/**
+ Retrieves this PCI controller's current PCI bus number, device number, and function number.
+
+ @param[in] This A pointer to the EFI_PCI_IO_PROTOCOL instance.
+ @param[out] SegmentNumber The PCI controller's current PCI segment number.
+ @param[out] BusNumber The PCI controller's current PCI bus number.
+ @param[out] DeviceNumber The PCI controller's current PCI device number.
+ @param[out] FunctionNumber The PCI controller’s current PCI function number.
+
+ @retval EFI_SUCCESS The PCI controller location was returned.
+ @retval EFI_INVALID_PARAMETER At least one out of the four output parameters is
+ a NULL pointer.
+**/
+EFI_STATUS
+PciIoGetLocation (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ OUT UINTN *SegmentNumber,
+ OUT UINTN *BusNumber,
+ OUT UINTN *DeviceNumber,
+ OUT UINTN *FunctionNumber
+ )
+{
+ EFI_PCI_IO_PRIVATE_DATA *Private;
+
+ if ((SegmentNumber == NULL) || (BusNumber == NULL) ||
+ (DeviceNumber == NULL) || (FunctionNumber == NULL) ) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This);
+ *SegmentNumber = Private->Segment;
+ *BusNumber = 0xff;
+ *DeviceNumber = 0;
+ *FunctionNumber = 0;
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Performs an operation on the attributes that this PCI controller supports.
+
+ The operations include getting the set of supported attributes, retrieving
+ the current attributes, setting the current attributes, enabling attributes,
+ and disabling attributes.
+
+ @param[in] This A pointer to the EFI_PCI_IO_PROTOCOL instance.
+ @param[in] Operation The operation to perform on the attributes for this
+ PCI controller.
+ @param[in] Attributes The mask of attributes that are used for Set,
+ Enable and Disable operations.
+ @param[out] Result A pointer to the result mask of attributes that are
+ returned for the Get and Supported operations. This
+ is an optional parameter that may be NULL for the
+ Set, Enable, and Disable operations.
+
+ @retval EFI_SUCCESS The operation on the PCI controller's
+ attributes was completed. If the operation
+ was Get or Supported, then the attribute mask
+ is returned in Result.
+ @retval EFI_INVALID_PARAMETER Operation is greater than or equal to
+ EfiPciIoAttributeOperationMaximum.
+ @retval EFI_INVALID_PARAMETER Operation is Get and Result is NULL.
+ @retval EFI_INVALID_PARAMETER Operation is Supported and Result is NULL.
+
+**/
+EFI_STATUS
+PciIoAttributes (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,
+ IN UINT64 Attributes,
+ OUT UINT64 *Result OPTIONAL
+ )
+{
+ switch (Operation) {
+ case EfiPciIoAttributeOperationGet:
+ case EfiPciIoAttributeOperationSupported:
+ if (Result == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+ //
+ // We are not a real PCI device so just say things we kind of do
+ //
+ *Result = EFI_PCI_DEVICE_ENABLE;
+ break;
+
+ case EfiPciIoAttributeOperationSet:
+ case EfiPciIoAttributeOperationEnable:
+ case EfiPciIoAttributeOperationDisable:
+ if (Attributes & (~EFI_PCI_DEVICE_ENABLE)) {
+ return EFI_UNSUPPORTED;
+ }
+ //
+ // Since we are not a real PCI device no enable/set or disable operations exist.
+ //
+ break;
+
+ default:
+ return EFI_INVALID_PARAMETER;
+ };
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+PciIoGetBarAttributes (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN UINT8 BarIndex,
+ OUT UINT64 *Supports, OPTIONAL
+ OUT VOID **Resources OPTIONAL
+ )
+{
+ if (Supports == NULL && Resources == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+PciIoSetBarAttributes (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN UINT64 Attributes,
+ IN UINT8 BarIndex,
+ IN OUT UINT64 *Offset,
+ IN OUT UINT64 *Length
+ )
+{
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+}
+
+EFI_PCI_IO_PROTOCOL PciIoTemplate =
+{
+ PciIoPollMem,
+ 0,
+ { PciIoMemRead, PciIoMemWrite },
+ { 0, PciIoIoWrite },
+ { PciIoPciRead, PciIoPciWrite },
+ PciIoCopyMem,
+ PciIoMap,
+ PciIoUnmap,
+ PciIoAllocateBuffer,
+ PciIoFreeBuffer,
+ PciIoFlush,
+ PciIoGetLocation,
+ PciIoAttributes,
+ PciIoGetBarAttributes,
+ PciIoSetBarAttributes,
+ 0,
+ 0
+};
+
+EFI_STATUS
+PciInstallDevice (
+ IN UINTN DeviceId,
+ IN PHYSICAL_ADDRESS MemoryStart,
+ IN UINT64 MemorySize,
+ IN UINTN ClassCode1,
+ IN UINTN ClassCode2,
+ IN UINTN ClassCode3
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
+ EFI_PCI_IO_PRIVATE_DATA *Private;
+
+ //
+ // Create a private structure
+ //
+ Private = AllocatePool (sizeof (EFI_PCI_IO_PRIVATE_DATA));
+ if (Private == NULL) {
+ Status = EFI_OUT_OF_RESOURCES;
+ DEBUG ((DEBUG_ERROR, "Failed to allocate memory for EFI_PCI_IO_PRIVATE_DATA\n"));
+ return Status;
+ }
+
+ Private->Signature = EFI_PCI_IO_PRIVATE_DATA_SIGNATURE; // Fill in signature
+ Private->RootBridge.Signature = PCI_ROOT_BRIDGE_SIGNATURE; // Fake Root Bridge structure needs a signature too
+ Private->RootBridge.MemoryStart = MemoryStart; // Get the controller register base
+ Private->Segment = 0; // Default to segment zero
+
+ //
+ // Calculate the total size of the controller.
+ //
+ Private->RootBridge.MemorySize = MemorySize;
+
+ //
+ // HBA reset
+ //
+ if (PCI_CLASS_MASS_STORAGE_SATADPA == ClassCode2) {
+ MmioWrite32 ((Private->RootBridge.MemoryStart + HBA_GHC), HBA_RESET);
+ }
+
+ //
+ // Create fake PCI config space
+ //
+ Private->ConfigSpace = AllocateZeroPool (sizeof (PCI_TYPE00));
+ if (Private->ConfigSpace == NULL) {
+ Status = EFI_OUT_OF_RESOURCES;
+ DEBUG ((DEBUG_ERROR, "Failed to allocate memory for PCI_TYPE00\n"));
+ FreePool (Private);
+ return Status;
+ }
+
+ //
+ // Configure PCI config space
+ //
+ Private->ConfigSpace->Hdr.VendorId = 0xFFFF; // Invalid vendor Id as it is not an actual device.
+ Private->ConfigSpace->Hdr.DeviceId = 0x0000; // Not relevant as the vendor id is not valid.
+ Private->ConfigSpace->Hdr.ClassCode[0] = ClassCode1;
+ Private->ConfigSpace->Hdr.ClassCode[1] = ClassCode2;
+ Private->ConfigSpace->Hdr.ClassCode[2] = ClassCode3;
+ Private->ConfigSpace->Device.Bar[0] = Private->RootBridge.MemoryStart;
+
+ Handle = NULL;
+
+ // Unique device path.
+ CopyMem (&Private->DevicePath, &PciIoDevicePathTemplate, sizeof (PciIoDevicePathTemplate));
+ Private->DevicePath.AcpiDevicePath.UID = 0;
+ Private->DevicePath.PciDevicePath.Device = DeviceId;
+
+ // Copy protocol structure
+ CopyMem (&Private->PciIoProtocol, &PciIoTemplate, sizeof (PciIoTemplate));
+
+ Status = gBS->InstallMultipleProtocolInterfaces (&Handle,
+ &gEfiPciIoProtocolGuid,
+ &Private->PciIoProtocol,
+ &gEfiDevicePathProtocolGuid,
+ &Private->DevicePath,
+ NULL);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "PciInstallDevice InstallMultipleProtocolInterfaces () failed.\n"));
+ FreePool (Private->ConfigSpace);
+ FreePool (Private);
+ }
+
+ return Status;
+}
+
+EFI_STATUS
+PciEmulationEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ BOOLEAN SuccessFlag;
+ UINT8 DeviceId;
+ UINTN ControllerAddr;
+
+ DeviceId = 0;
+
+ while (DeviceId < PcdGet32 (PcdNumUsbController)) {
+ ControllerAddr = PcdGet32 (PcdUsbBaseAddr) + (DeviceId * PcdGet32 (PcdUsbSize));
+ Status = InitializeUsbController (ControllerAddr);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "USB HC initialization Failed for %d (0x%x)\n",
+ ControllerAddr, Status));
+ continue;
+ }
+
+ Status = PciInstallDevice (DeviceId, ControllerAddr, PcdGet32 (PcdUsbSize),
+ PCI_IF_XHCI, PCI_CLASS_SERIAL_USB,
+ PCI_CLASS_SERIAL);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "PciEmulation: failed to install USB %d device\n", DeviceId));
+ } else {
+ SuccessFlag = TRUE;
+ }
+ DeviceId++;
+ }
+
+ while (DeviceId < (PcdGet32 (PcdNumUsbController) + PcdGet32 (PcdNumSataController))) {
+ ControllerAddr = PcdGet32 (PcdSataBaseAddr) +
+ ((DeviceId - PcdGet32 (PcdNumUsbController)) * PcdGet32 (PcdSataSize));
+
+ Status = PciInstallDevice (DeviceId, ControllerAddr, PcdGet32 (PcdSataSize),
+ PCI_IF_MASS_STORAGE_SATA, PCI_CLASS_MASS_STORAGE_SATADPA,
+ PCI_CLASS_MASS_STORAGE);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "PciEmulation: failed to install SATA %d device\n",
+ DeviceId - PcdGet32 (PcdNumUsbController)));
+ } else {
+ SuccessFlag = TRUE;
+ }
+ DeviceId++;
+ }
+
+ if (SuccessFlag) {
+ return EFI_SUCCESS;
+ } else {
+ return Status;
+ }
+}
diff --git a/Platform/NXP/Drivers/PciEmulation/PciEmulation.h b/Platform/NXP/Drivers/PciEmulation/PciEmulation.h
new file mode 100755
index 0000000..870d870
--- /dev/null
+++ b/Platform/NXP/Drivers/PciEmulation/PciEmulation.h
@@ -0,0 +1,306 @@
+/** PciEmulation.h
+ Provides all declararyion of PCI Root Bridge IO Protocol
+
+ Reference taken from PCI Emulation implementation in
+ Omap35xxPkg/PciEmulation/
+
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCI_EMULATION_H_
+#define _PCI_EMULATION_H_
+
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/Pci.h>
+#include <IndustryStandard/Pci22.h>
+#include <IndustryStandard/Pci30.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DmaLib.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PciLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <PiDxe.h>
+#include <Protocol/DevicePath.h>
+#include <Protocol/EmbeddedExternalDevice.h>
+#include <Protocol/PciHostBridgeResourceAllocation.h>
+#include <Protocol/PciIo.h>
+#include <Protocol/PciRootBridgeIo.h>
+
+
+#define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32 ('P', 'C', 'I', '3')
+#define EFI_PCI_IO_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('P', 'C', 'I', 'L')
+#define EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(a) CR (a, EFI_PCI_IO_PRIVATE_DATA, PciIoProtocol, EFI_PCI_IO_PRIVATE_DATA_SIGNATURE)
+#define INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) CR (a, PCI_ROOT_BRIDGE, Io, PCI_ROOT_BRIDGE_SIGNATURE)
+
+
+#define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL
+#define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL
+#define EFI_RESOURCE_SATISFIED 0x0000000000000000ULL
+
+#define HBA_GHC 0x04
+#define HBA_RESET 0x80000001
+
+typedef struct {
+ ACPI_HID_DEVICE_PATH AcpiDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
+} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
+
+
+#define ACPI_CONFIG_IO 0
+#define ACPI_CONFIG_MMIO 1
+#define ACPI_CONFIG_BUS 2
+
+typedef struct {
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR Desc[3];
+ EFI_ACPI_END_TAG_DESCRIPTOR EndDesc;
+} ACPI_CONFIG_INFO;
+
+
+
+typedef struct {
+ UINT32 Signature;
+ EFI_HANDLE Handle;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io;
+ EFI_PCI_ROOT_BRIDGE_DEVICE_PATH DevicePath;
+ UINT8 StartBus;
+ UINT8 EndBus;
+ UINT16 Type;
+ UINT32 MemoryStart;
+ UINT32 MemorySize;
+ UINTN IoOffset;
+ UINT32 IoStart;
+ UINT32 IoSize;
+ UINT64 PciAttributes;
+ ACPI_CONFIG_INFO *Config;
+} PCI_ROOT_BRIDGE;
+
+
+typedef struct {
+ ACPI_HID_DEVICE_PATH AcpiDevicePath;
+ PCI_DEVICE_PATH PciDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
+} EFI_PCI_IO_DEVICE_PATH;
+
+typedef struct {
+ UINT32 Signature;
+ EFI_PCI_IO_DEVICE_PATH DevicePath;
+ EFI_PCI_IO_PROTOCOL PciIoProtocol;
+ PCI_TYPE00 *ConfigSpace;
+ PCI_ROOT_BRIDGE RootBridge;
+ UINTN Segment;
+} EFI_PCI_IO_PRIVATE_DATA;
+
+//
+// Driver Instance Data Prototypes
+//
+
+typedef struct {
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation;
+ UINTN NumberOfBytes;
+ UINTN NumberOfPages;
+ EFI_PHYSICAL_ADDRESS HostAddress;
+ EFI_PHYSICAL_ADDRESS MappedHostAddress;
+} MAP_INFO;
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoPollMem (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINT64 Mask,
+ IN UINT64 Value,
+ IN UINT64 Delay,
+ OUT UINT64 *Result
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoPollIo (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINT64 Mask,
+ IN UINT64 Value,
+ IN UINT64 Delay,
+ OUT UINT64 *Result
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoMemRead (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoMemWrite (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoIoRead (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 UserAddress,
+ IN UINTN Count,
+ IN OUT VOID *UserBuffer
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoIoWrite (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 UserAddress,
+ IN UINTN Count,
+ IN OUT VOID *UserBuffer
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoCopyMem (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 DestAddress,
+ IN UINT64 SrcAddress,
+ IN UINTN Count
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoPciRead (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoPciWrite (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoMap (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation,
+ IN VOID *HostAddress,
+ IN OUT UINTN *NumberOfBytes,
+ OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
+ OUT VOID **Mapping
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoUnmap (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN VOID *Mapping
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoAllocateBuffer (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_ALLOCATE_TYPE Type,
+ IN EFI_MEMORY_TYPE MemoryType,
+ IN UINTN Pages,
+ OUT VOID **HostAddress,
+ IN UINT64 Attributes
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoFreeBuffer (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN UINTN Pages,
+ OUT VOID *HostAddress
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoFlush (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoGetAttributes (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ OUT UINT64 *Supported,
+ OUT UINT64 *Attributes
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoConfiguration (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ OUT VOID **Resources
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoSetAttributes (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN UINT64 Attributes,
+ IN OUT UINT64 *ResourceBase,
+ IN OUT UINT64 *ResourceLength
+ );
+
+//
+// Private Function Prototypes
+//
+//
+EFI_STATUS
+PciRootBridgeIoMemRW (
+ IN BOOLEAN Write,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ );
+
+BOOLEAN
+PciIoMemAddressValid (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN UINT64 Address
+ );
+
+EFI_STATUS
+EFIAPI
+InitializeUsbController (
+ IN UINTN UsbReg
+ );
+
+#endif
diff --git a/Platform/NXP/Drivers/PciEmulation/PciEmulation.inf b/Platform/NXP/Drivers/PciEmulation/PciEmulation.inf
new file mode 100644
index 0000000..10fcb4b
--- /dev/null
+++ b/Platform/NXP/Drivers/PciEmulation/PciEmulation.inf
@@ -0,0 +1,54 @@
+/* PciEmulation.inf
+# Component description file for PCI Host Bridge driver
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+*/
+
+[Defines]
+ INF_VERSION = 0x0001000A
+ BASE_NAME = PciEmulation
+ FILE_GUID = 196e7c2a-37b2-4b85-8683-7185c055fd5b
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = PciEmulationEntryPoint
+
+[Sources.common]
+ PciRootBridgeIo.c
+ PciEmulation.c
+
+[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Platform/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ DmaLib
+ UefiDriverEntryPoint
+ UsbHcdLibrary
+
+[FixedPcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdUsbSize
+ gNxpQoriqLsTokenSpaceGuid.PcdNumUsbController
+ gNxpQoriqLsTokenSpaceGuid.PcdSataBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdSataSize
+ gNxpQoriqLsTokenSpaceGuid.PcdNumSataController
+
+[Protocols]
+ gEfiPciRootBridgeIoProtocolGuid
+ gEfiDevicePathProtocolGuid
+ gEfiPciHostBridgeResourceAllocationProtocolGuid
+ gEfiPciIoProtocolGuid
+
+[Depex]
+ TRUE
diff --git a/Platform/NXP/Drivers/PciEmulation/PciRootBridgeIo.c b/Platform/NXP/Drivers/PciEmulation/PciRootBridgeIo.c
new file mode 100644
index 0000000..4020cbe
--- /dev/null
+++ b/Platform/NXP/Drivers/PciEmulation/PciRootBridgeIo.c
@@ -0,0 +1,286 @@
+/** PciRootBridgeIo.c
+ PCI Root Bridge Io Protocol implementation
+
+ Reference taken from PCI Emulation implementation in
+ Omap35xxPkg/PciEmulation/
+
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PciEmulation.h"
+
+//
+// Lookup table for increment values based on transfer widths
+//
+UINT8 mInStride[] = {
+ 1, // EfiPciWidthUint8
+ 2, // EfiPciWidthUint16
+ 4, // EfiPciWidthUint32
+ 8, // EfiPciWidthUint64
+ 0, // EfiPciWidthFifoUint8
+ 0, // EfiPciWidthFifoUint16
+ 0, // EfiPciWidthFifoUint32
+ 0, // EfiPciWidthFifoUint64
+ 1, // EfiPciWidthFillUint8
+ 2, // EfiPciWidthFillUint16
+ 4, // EfiPciWidthFillUint32
+ 8 // EfiPciWidthFillUint64
+};
+
+//
+// Lookup table for increment values based on transfer widths
+//
+UINT8 mOutStride[] = {
+ 1, // EfiPciWidthUint8
+ 2, // EfiPciWidthUint16
+ 4, // EfiPciWidthUint32
+ 8, // EfiPciWidthUint64
+ 1, // EfiPciWidthFifoUint8
+ 2, // EfiPciWidthFifoUint16
+ 4, // EfiPciWidthFifoUint32
+ 8, // EfiPciWidthFifoUint64
+ 0, // EfiPciWidthFillUint8
+ 0, // EfiPciWidthFillUint16
+ 0, // EfiPciWidthFillUint32
+ 0 // EfiPciWidthFillUint64
+};
+
+
+BOOLEAN
+PciRootBridgeMemAddressValid (
+ IN PCI_ROOT_BRIDGE *Private,
+ IN UINT64 Address
+ )
+{
+ if ((Address >= Private->MemoryStart) &&
+ (Address < (Private->MemoryStart + Private->MemorySize))) {
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+EFI_STATUS
+PciRootBridgeIoMemRW (
+ IN BOOLEAN Write,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ UINT8 InStride;
+ UINT8 OutStride;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth;
+ UINT8 *Uint8Buffer;
+
+ InStride = mInStride[Width];
+ OutStride = mOutStride[Width];
+ OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
+ for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
+ if (Write) {
+ switch (OperationWidth) {
+ case EfiPciWidthUint8:
+ MmioWrite8 ((UINTN)Address, *Uint8Buffer);
+ break;
+ case EfiPciWidthUint16:
+ MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
+ break;
+ case EfiPciWidthUint32:
+ MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
+ break;
+ case EfiPciWidthUint64:
+ MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
+ break;
+ default:
+ //
+ // The RootBridgeIoCheckParameter call above will ensure that this
+ // path is not taken.
+ //
+ ASSERT (FALSE);
+ break;
+ }
+ } else {
+ switch (OperationWidth) {
+ case EfiPciWidthUint8:
+ *Uint8Buffer = MmioRead8 ((UINTN)Address);
+ break;
+ case EfiPciWidthUint16:
+ *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
+ break;
+ case EfiPciWidthUint32:
+ *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
+ break;
+ case EfiPciWidthUint64:
+ *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
+ break;
+ default:
+ //
+ // The RootBridgeIoCheckParameter call above will ensure that this
+ // path is not taken.
+ //
+ ASSERT (FALSE);
+ break;
+ }
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
+
+ @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param Width Signifies the width of the memory operations.
+ @param Address The base address of the memory operations.
+ @param Count The number of memory operations to perform.
+ @param Buffer For read operations, the destination buffer to store the results. For write
+ operations, the source buffer to write data from.
+
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+
+**/
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoMemRead (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ PCI_ROOT_BRIDGE *Private;
+
+ if ( Buffer == NULL ) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Private = INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
+
+ if (!PciRootBridgeMemAddressValid (Private, Address)) {
+ DEBUG ((DEBUG_ERROR, "READ ADDRESS is not valid: %llx\n", Address));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return PciRootBridgeIoMemRW (FALSE, Width, Address, Count, Buffer);
+
+}
+
+/**
+ Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
+
+ @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param Width Signifies the width of the memory operations.
+ @param Address The base address of the memory operations.
+ @param Count The number of memory operations to perform.
+ @param Buffer For read operations, the destination buffer to store the results. For write
+ operations, the source buffer to write data from.
+
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+
+**/
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoMemWrite (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ PCI_ROOT_BRIDGE *Private;
+
+ if ( Buffer == NULL ) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Private = INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
+
+ if (!PciRootBridgeMemAddressValid (Private, Address)) {
+ DEBUG ((DEBUG_ERROR, "WRITE ADDRESS is not valid: %llx\n", Address));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return PciRootBridgeIoMemRW (TRUE, Width, Address, Count, Buffer);
+}
+
+/**
+ Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
+
+ @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param Width Signifies the width of the memory operations.
+ @param Address The base address of the memory operations.
+ @param Count The number of memory operations to perform.
+ @param Buffer For read operations, the destination buffer to store the results. For write
+ operations, the source buffer to write data from.
+
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+
+**/
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoPciRead (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ if (Buffer == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
+
+ @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param Width Signifies the width of the memory operations.
+ @param Address The base address of the memory operations.
+ @param Count The number of memory operations to perform.
+ @param Buffer For read operations, the destination buffer to store the results. For write
+ operations, the source buffer to write data from.
+
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+
+**/
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoPciWrite (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ if (Buffer == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/NXP/NxpQoriqLs.dec b/Platform/NXP/NxpQoriqLs.dec
index fd07eee..f43ccf0 100644
--- a/Platform/NXP/NxpQoriqLs.dec
+++ b/Platform/NXP/NxpQoriqLs.dec
@@ -51,8 +51,8 @@
gNxpQoriqLsTokenSpaceGuid.PcdI2c1BaseAddr|0|UINT64|0x0000010E
gNxpQoriqLsTokenSpaceGuid.PcdI2c2BaseAddr|0|UINT64|0x0000010F
gNxpQoriqLsTokenSpaceGuid.PcdI2c3BaseAddr|0|UINT64|0x00000110
- gNxpQoriqLsTokenSpaceGuid.PcdSataController1BaseAddress|0x0|UINT32|0x00000111
- gNxpQoriqLsTokenSpaceGuid.PcdSataController2BaseAddress|0x0|UINT32|0x00000112
+ gNxpQoriqLsTokenSpaceGuid.PcdSataBaseAddr|0x0|UINT32|0x00000111
+ gNxpQoriqLsTokenSpaceGuid.PcdSataSize|0x0|UINT32|0x00000112
gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000|UINT64|0x00000113
gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000|UINT64|0x00000114
gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000|UINT64|0x00000115
@@ -246,3 +246,8 @@
#
gNxpQoriqLsTokenSpaceGuid.PcdSysEepromI2cBus|0|UINT32|0x0000330
gNxpQoriqLsTokenSpaceGuid.PcdSysEepromI2cAddress|0|UINT32|0x0000331
+
+ #
+ # SATA Pcds
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdNumSataController|0x0|UINT32|0x00000340
--
1.9.1
next prev parent reply other threads:[~2017-12-22 6:24 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-22 12:16 [PATCH edk2-platforms 0/3] Cover letter:Pci Emulation and SATA support Meenakshi Aggarwal
2017-12-22 12:16 ` [PATCH edk2-platforms 1/3] USB: Added Support of DWC3 USB controller Meenakshi Aggarwal
2017-12-22 12:16 ` Meenakshi Aggarwal [this message]
2017-12-22 12:16 ` [PATCH edk2-platforms 3/3] SATA : Added SATA controller initialization driver Meenakshi Aggarwal
2017-12-22 15:31 ` [PATCH edk2-platforms 0/3] Cover letter:Pci Emulation and SATA support Ard Biesheuvel
2018-01-04 11:27 ` Meenakshi Aggarwal
2018-01-04 11:33 ` Ard Biesheuvel
2018-01-04 12:56 ` Meenakshi Aggarwal
2018-01-05 6:47 ` Meenakshi Aggarwal
2018-01-05 7:40 ` Ard Biesheuvel
2018-01-05 8:53 ` Meenakshi Aggarwal
2018-01-05 9:16 ` Ard Biesheuvel
2018-01-08 15:55 ` [PATCH edk2-platforms v2 0/2] Cover letter:SATA controller support Meenakshi Aggarwal
2018-01-08 15:55 ` [PATCH edk2-platforms v2 1/2] SATA : Added SATA controller driver Meenakshi Aggarwal
2018-01-08 15:05 ` Ard Biesheuvel
2018-01-09 4:50 ` Meenakshi Aggarwal
2018-01-09 8:26 ` Ard Biesheuvel
2018-01-08 15:55 ` [PATCH edk2-platforms v2 2/2] LS1046 : Enable support of SATA controller Meenakshi Aggarwal
2018-01-08 15:11 ` Ard Biesheuvel
2018-01-09 4:37 ` Meenakshi Aggarwal
2018-01-09 8:27 ` Ard Biesheuvel
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