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From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
To: <ard.biesheuvel@linaro.org>, <liming.gao@intel.com>,
	<michael.d.kinney@intel.com>, <edk2-devel@lists.01.org>
Subject: [PATCH] PCI : define macro for AHCI base address.
Date: Mon, 8 Jan 2018 16:50:46 +0530	[thread overview]
Message-ID: <1515410446-14750-1-git-send-email-meenakshi.aggarwal@nxp.com> (raw)

Define PCI BAR 5 macro of AHCI Base address.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
 MdePkg/Include/IndustryStandard/Pci22.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MdePkg/Include/IndustryStandard/Pci22.h b/MdePkg/Include/IndustryStandard/Pci22.h
index 96a7680..a63bb7c 100644
--- a/MdePkg/Include/IndustryStandard/Pci22.h
+++ b/MdePkg/Include/IndustryStandard/Pci22.h
@@ -533,6 +533,7 @@ typedef struct {
 #define PCI_HEADER_TYPE_OFFSET                      0x0E
 #define PCI_BIST_OFFSET                             0x0F
 #define PCI_BASE_ADDRESSREG_OFFSET                  0x10
+#define PCI_AHCI_BASE_ADDRESS                       0x24
 #define PCI_CARDBUS_CIS_OFFSET                      0x28
 #define PCI_SVID_OFFSET                             0x2C ///< SubSystem Vendor id
 #define PCI_SUBSYSTEM_VENDOR_ID_OFFSET              0x2C
-- 
1.9.1



             reply	other threads:[~2018-01-08  5:27 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-01-08 11:20 Meenakshi Aggarwal [this message]
2018-01-08  6:01 ` [PATCH] PCI : define macro for AHCI base address Ni, Ruiyu
2018-01-08  6:07   ` Meenakshi Aggarwal

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