From: Star Zeng <star.zeng@intel.com>
To: edk2-devel@lists.01.org
Cc: Star Zeng <star.zeng@intel.com>, Jiewen Yao <jiewen.yao@intel.com>
Subject: [PATCH] IntelSiliconPkg IntelVTdPmrPei: Use HostAddressWidth in DMAR correctly
Date: Tue, 16 Jan 2018 18:52:11 +0800 [thread overview]
Message-ID: <1516099931-17796-1-git-send-email-star.zeng@intel.com> (raw)
According to VTd spec, HostAddressWidth + 1 should be used as the real
host address width value.
Host Address Width:
This field indicates the maximum DMA physical
addressability supported by this platform. The
system address map reported by the BIOS
indicates what portions of this addresses are
populated.
The Host Address Width (HAW) of the platform is
computed as (N+1), where N is the value
reported in this field. For example, for a platform
supporting 40 bits of physical addressability, the
value of 100111b is reported in this field.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
---
IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c b/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c
index 7147a19f538a..aae482a0385b 100644
--- a/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c
+++ b/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c
@@ -677,7 +677,7 @@ InitVTdPmrForAll (
LowBottom = 0;
LowTop = 0;
HighBottom = 0;
- HighTop = LShiftU64 (1, VTdInfo->HostAddressWidth);
+ HighTop = LShiftU64 (1, VTdInfo->HostAddressWidth + 1);
Status = SetDmaProtectedRange (
VTdInfo,
--
2.7.0.windows.1
next reply other threads:[~2018-01-16 10:46 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-16 10:52 Star Zeng [this message]
2018-01-17 1:09 ` [PATCH] IntelSiliconPkg IntelVTdPmrPei: Use HostAddressWidth in DMAR correctly Yao, Jiewen
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