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From: Star Zeng <star.zeng@intel.com>
To: edk2-devel@lists.01.org
Cc: Star Zeng <star.zeng@intel.com>, Jiewen Yao <jiewen.yao@intel.com>
Subject: [PATCH] IntelSiliconPkg IntelVTdDxe: Fix flush cache issue
Date: Wed, 24 Jan 2018 13:20:54 +0800	[thread overview]
Message-ID: <1516771254-11588-1-git-send-email-star.zeng@intel.com> (raw)

The patch fixes flush cache issue in
CreateSecondLevelPagingEntryTable().

We found some video cards still not work even they have
been added to the exception list.

In CreateSecondLevelPagingEntryTable(), the check
"(BaseAddress >= MemoryLimit)" may be TRUE and "goto Done"
will be executed, then the FlushPageTableMemory operations
at the end of the function will be skipped.

Instead of "goto Done", this patch uses "break" to break
the for loops, then the FlushPageTableMemory operations
at the end of the function could have opportunity to be
executed.

The patch also fixed a miscalculation for Lvl3End.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
---
 IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
index 7bdc4a5146bd..bce5a45105d2 100644
--- a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
+++ b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
@@ -1,6 +1,6 @@
 /** @file
 
-  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -226,7 +226,7 @@ CreateSecondLevelPagingEntryTable (
 
     Lvl3Start = RShiftU64 (BaseAddress, 30) & 0x1FF;
     if (ALIGN_VALUE_LOW(BaseAddress + SIZE_1GB, SIZE_1GB) <= EndAddress) {
-      Lvl3End = SIZE_4KB/sizeof(VTD_SECOND_LEVEL_PAGING_ENTRY);
+      Lvl3End = SIZE_4KB/sizeof(VTD_SECOND_LEVEL_PAGING_ENTRY) - 1;
     } else {
       Lvl3End = RShiftU64 (EndAddress - 1, 30) & 0x1FF;
     }
@@ -252,16 +252,21 @@ CreateSecondLevelPagingEntryTable (
         Lvl2PtEntry[Index2].Bits.PageSize = 1;
         BaseAddress += SIZE_2MB;
         if (BaseAddress >= MemoryLimit) {
-          goto Done;
+          break;
         }
       }
       FlushPageTableMemory (VtdIndex, (UINTN)Lvl2PtEntry, SIZE_4KB);
+      if (BaseAddress >= MemoryLimit) {
+        break;
+      }
     }
     FlushPageTableMemory (VtdIndex, (UINTN)&Lvl3PtEntry[Lvl3Start], (UINTN)&Lvl3PtEntry[Lvl3End + 1] - (UINTN)&Lvl3PtEntry[Lvl3Start]);
+    if (BaseAddress >= MemoryLimit) {
+      break;
+    }
   }
   FlushPageTableMemory (VtdIndex, (UINTN)&Lvl4PtEntry[Lvl4Start], (UINTN)&Lvl4PtEntry[Lvl4End + 1] - (UINTN)&Lvl4PtEntry[Lvl4Start]);
 
-Done:
   return SecondLevelPagingEntry;
 }
 
-- 
2.7.0.windows.1



             reply	other threads:[~2018-01-24  5:15 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-01-24  5:20 Star Zeng [this message]
2018-01-24  6:10 ` [PATCH] IntelSiliconPkg IntelVTdDxe: Fix flush cache issue Yao, Jiewen

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