From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=star.zeng@intel.com; receiver=edk2-devel@lists.01.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9F2D92238B5A8 for ; Tue, 23 Jan 2018 21:15:31 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Jan 2018 21:20:59 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,405,1511856000"; d="scan'208";a="12596984" Received: from shwdeopenpsi068.ccr.corp.intel.com ([10.239.158.46]) by orsmga008.jf.intel.com with ESMTP; 23 Jan 2018 21:20:57 -0800 From: Star Zeng To: edk2-devel@lists.01.org Cc: Star Zeng , Jiewen Yao Date: Wed, 24 Jan 2018 13:20:54 +0800 Message-Id: <1516771254-11588-1-git-send-email-star.zeng@intel.com> X-Mailer: git-send-email 2.7.0.windows.1 Subject: [PATCH] IntelSiliconPkg IntelVTdDxe: Fix flush cache issue X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 24 Jan 2018 05:15:32 -0000 The patch fixes flush cache issue in CreateSecondLevelPagingEntryTable(). We found some video cards still not work even they have been added to the exception list. In CreateSecondLevelPagingEntryTable(), the check "(BaseAddress >= MemoryLimit)" may be TRUE and "goto Done" will be executed, then the FlushPageTableMemory operations at the end of the function will be skipped. Instead of "goto Done", this patch uses "break" to break the for loops, then the FlushPageTableMemory operations at the end of the function could have opportunity to be executed. The patch also fixed a miscalculation for Lvl3End. Cc: Jiewen Yao Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng --- IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c index 7bdc4a5146bd..bce5a45105d2 100644 --- a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c +++ b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c @@ -1,6 +1,6 @@ /** @file - Copyright (c) 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -226,7 +226,7 @@ CreateSecondLevelPagingEntryTable ( Lvl3Start = RShiftU64 (BaseAddress, 30) & 0x1FF; if (ALIGN_VALUE_LOW(BaseAddress + SIZE_1GB, SIZE_1GB) <= EndAddress) { - Lvl3End = SIZE_4KB/sizeof(VTD_SECOND_LEVEL_PAGING_ENTRY); + Lvl3End = SIZE_4KB/sizeof(VTD_SECOND_LEVEL_PAGING_ENTRY) - 1; } else { Lvl3End = RShiftU64 (EndAddress - 1, 30) & 0x1FF; } @@ -252,16 +252,21 @@ CreateSecondLevelPagingEntryTable ( Lvl2PtEntry[Index2].Bits.PageSize = 1; BaseAddress += SIZE_2MB; if (BaseAddress >= MemoryLimit) { - goto Done; + break; } } FlushPageTableMemory (VtdIndex, (UINTN)Lvl2PtEntry, SIZE_4KB); + if (BaseAddress >= MemoryLimit) { + break; + } } FlushPageTableMemory (VtdIndex, (UINTN)&Lvl3PtEntry[Lvl3Start], (UINTN)&Lvl3PtEntry[Lvl3End + 1] - (UINTN)&Lvl3PtEntry[Lvl3Start]); + if (BaseAddress >= MemoryLimit) { + break; + } } FlushPageTableMemory (VtdIndex, (UINTN)&Lvl4PtEntry[Lvl4Start], (UINTN)&Lvl4PtEntry[Lvl4End + 1] - (UINTN)&Lvl4PtEntry[Lvl4Start]); -Done: return SecondLevelPagingEntry; } -- 2.7.0.windows.1