* [PATCH edk2-platforms v2 00/15] Improve D0x platforms and bug fix
@ 2018-01-26 8:00 Ming Huang
2018-01-26 8:00 ` [PATCH edk2-platforms v2 01/15] Hisilicon/D05: Move Madt definition to head file Ming Huang
` (15 more replies)
0 siblings, 16 replies; 30+ messages in thread
From: Ming Huang @ 2018-01-26 8:00 UTC (permalink / raw)
To: leif.lindholm, linaro-uefi, edk2-devel, graeme.gregory
Cc: ard.biesheuvel, guoheyi, wanghuiqiang, huangming23, zhangjinsong2,
mengfanrong, huangdaode, waip23
The major features of this patchset include
adding PPTT support,
switching to Generic BDS driver,
adding capsule upgrade support,
open-source version for SnpPlatform and SasPlatform
changing DmaLib to CoherentDmaLib(this one is omissive in v1).
Code can also be found in github: https://github.com/hisilicon/OpenPlatformPkg.git
branch: rp-1802-platforms-v2
Jason Zhang (3):
Hisilicon D03/D05: Add capsule upgrade support
Hisilicon D03/D05: Open SasPlatform source code
Hisilicon D03/D05: Open SnpPlatform source code
Ming Huang (11):
Hisilicon/D05: Move Madt definition to head file
Hisilicon/D05: Add PPTT support
Hisilicon/D0x/BDS: Switch to Generic BDS driver
Hisilicon/D0x: Break BMC SetBoot option out into separate library
Hilisicon: Change DmaLib to CoherentDmaLib
Hisilicon/Smbios: Indicate use of ProcessorFamily2 in type 4 table
Hisilicon/D05: Replace SP805Watchdog by WatchdogTimer driver.
Hisilicon/D03: Replace SP805Watchdog by WatchdogTimer driver.
Hisilicon/D05/ACPI: Add ITS PXM
Hisilicon/D05/ACPI: Add Pcie, HNS and SAS PXM
Hisilicon D03/D05: Update firmware version to 18.02
Yan Zhang (1):
Hisilicon/PCIe: Disable PCIe ASPM
Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini | 45 ++
Platform/Hisilicon/D03/D03.dsc | 42 +-
Platform/Hisilicon/D03/D03.fdf | 79 ++-
Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc | 81 +++
Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 50 ++
Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c | 70 +++
Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini | 45 ++
Platform/Hisilicon/D05/D05.dsc | 47 +-
Platform/Hisilicon/D05/D05.fdf | 80 ++-
Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc | 81 +++
Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 50 ++
Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c | 70 +++
Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.c | 106 ++++
Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf | 45 ++
Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c | 4 +-
Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.c | 115 ++++
Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf | 46 ++
Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.c | 2 +-
Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.c | 3 +-
Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 103 ++++
Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 2 +
Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc | 10 +
Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl | 9 +
Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 34 +-
Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl | 19 +-
Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h | 30 +-
Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc | 23 +-
Silicon/Hisilicon/Hi1616/Pptt/Pptt.c | 540 ++++++++++++++++
Silicon/Hisilicon/Hi1616/Pptt/Pptt.h | 88 +++
Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf | 48 ++
Silicon/Hisilicon/HisiPkg.dec | 6 +
Silicon/Hisilicon/Hisilicon.dsc.inc | 12 +-
Silicon/Hisilicon/Hisilicon.fdf.inc | 9 +
Silicon/Hisilicon/Include/Library/AcpiNextLib.h | 10 +-
Silicon/Hisilicon/Include/Library/BmcConfigBootLib.h | 31 +
Silicon/Hisilicon/Include/Library/OemDevicePath.h | 52 ++
Silicon/Hisilicon/Include/Protocol/HisiPlatformSasProtocol.h | 30 +
Silicon/Hisilicon/Include/Protocol/SnpPlatformProtocol.h | 32 +
Silicon/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h | 2 +
Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.c | 466 ++++++++++++++
Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf | 51 ++
Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c | 643 ++++++++++++++++++++
Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.h | 31 +
Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf | 74 +++
Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c | 123 ++++
Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf | 51 ++
46 files changed, 3536 insertions(+), 54 deletions(-)
create mode 100644 Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
create mode 100644 Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
create mode 100644 Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
create mode 100644 Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c
create mode 100644 Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
create mode 100644 Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
create mode 100644 Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
create mode 100644 Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c
create mode 100644 Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.c
create mode 100644 Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf
create mode 100644 Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.c
create mode 100644 Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf
create mode 100644 Silicon/Hisilicon/Hi1616/Pptt/Pptt.c
create mode 100644 Silicon/Hisilicon/Hi1616/Pptt/Pptt.h
create mode 100644 Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf
create mode 100644 Silicon/Hisilicon/Include/Library/BmcConfigBootLib.h
create mode 100644 Silicon/Hisilicon/Include/Library/OemDevicePath.h
create mode 100644 Silicon/Hisilicon/Include/Protocol/HisiPlatformSasProtocol.h
create mode 100644 Silicon/Hisilicon/Include/Protocol/SnpPlatformProtocol.h
create mode 100644 Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.c
create mode 100644 Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf
create mode 100644 Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c
create mode 100644 Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.h
create mode 100644 Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
create mode 100644 Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c
create mode 100644 Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf
--
1.9.1
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH edk2-platforms v2 01/15] Hisilicon/D05: Move Madt definition to head file
2018-01-26 8:00 [PATCH edk2-platforms v2 00/15] Improve D0x platforms and bug fix Ming Huang
@ 2018-01-26 8:00 ` Ming Huang
2018-01-30 14:27 ` graeme.gregory
2018-01-26 8:00 ` [PATCH edk2-platforms v2 02/15] Hisilicon/D05: Add PPTT support Ming Huang
` (14 subsequent siblings)
15 siblings, 1 reply; 30+ messages in thread
From: Ming Huang @ 2018-01-26 8:00 UTC (permalink / raw)
To: leif.lindholm, linaro-uefi, edk2-devel, graeme.gregory
Cc: ard.biesheuvel, guoheyi, wanghuiqiang, huangming23, zhangjinsong2,
mengfanrong, huangdaode, waip23, Heyi Guo
Move definition of Madt struct to head file, so PPTT driver
can include it.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
---
Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h | 30 +++++++++++++++++++-
Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc | 23 +--------------
2 files changed, 30 insertions(+), 23 deletions(-)
diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h
index 808219a..ad73aa2 100644
--- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h
+++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h
@@ -1,7 +1,7 @@
/** @file
*
* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
-* Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015-2018, Hisilicon Limited. All rights reserved.
* Copyright (c) 2015-2016, Linaro Limited. All rights reserved.
*
* This program and the accompanying materials
@@ -20,6 +20,8 @@
#ifndef _HI1610_PLATFORM_H_
#define _HI1610_PLATFORM_H_
+#include <IndustryStandard/Acpi.h>
+
//
// ACPI table information used to initialize tables.
//
@@ -44,5 +46,31 @@
}
#define HI1616_WATCHDOG_COUNT 2
+#define HI1616_GIC_STRUCTURE_COUNT 64
+
+#define HI1616_MPID_TA_BASE 0x10000
+#define HI1616_MPID_TB_BASE 0x30000
+#define HI1616_MPID_TA_2_BASE 0x50000
+#define HI1616_MPID_TB_2_BASE 0x70000
+
+// Differs from Juno, we have another affinity level beyond cluster and core
+#define PLATFORM_GET_MPID_TA(ClusterId, CoreId) (HI1616_MPID_TA_BASE | ((ClusterId) << 8) | (CoreId))
+#define PLATFORM_GET_MPID_TB(ClusterId, CoreId) (HI1616_MPID_TB_BASE | ((ClusterId) << 8) | (CoreId))
+#define PLATFORM_GET_MPID_TA_2(ClusterId, CoreId) (HI1616_MPID_TA_2_BASE | ((ClusterId) << 8) | (CoreId))
+#define PLATFORM_GET_MPID_TB_2(ClusterId, CoreId) (HI1616_MPID_TB_2_BASE | ((ClusterId) << 8) | (CoreId))
+
+//
+// Multiple APIC Description Table
+//
+#pragma pack (1)
+
+typedef struct {
+ EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_1_GIC_STRUCTURE GicInterfaces[HI1616_GIC_STRUCTURE_COUNT];
+ EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
+ EFI_ACPI_6_1_GIC_ITS_STRUCTURE GicITS[8];
+} EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE;
+
+#pragma pack ()
#endif
diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc b/Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc
index 169ee72..54605a6 100644
--- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc
+++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc
@@ -2,7 +2,7 @@
* Multiple APIC Description Table (MADT)
*
* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
-* Copyright (c) 2015 - 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015 - 2018, Hisilicon Limited. All rights reserved.
* Copyright (c) 2015 - 2016, Linaro Limited. All rights reserved.
*
* This program and the accompanying materials
@@ -27,27 +27,6 @@
#include <Library/PcdLib.h>
#include "Hi1616Platform.h"
-// Differs from Juno, we have another affinity level beyond cluster and core
-// 0x20000 is only for socket 0
-#define PLATFORM_GET_MPID_TA(ClusterId, CoreId) (0x10000 | ((ClusterId) << 8) | (CoreId))
-#define PLATFORM_GET_MPID_TB(ClusterId, CoreId) (0x30000 | ((ClusterId) << 8) | (CoreId))
-#define PLATFORM_GET_MPID_TA_2(ClusterId, CoreId) (0x50000 | ((ClusterId) << 8) | (CoreId))
-#define PLATFORM_GET_MPID_TB_2(ClusterId, CoreId) (0x70000 | ((ClusterId) << 8) | (CoreId))
-
-//
-// Multiple APIC Description Table
-//
-#pragma pack (1)
-
-typedef struct {
- EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_1_GIC_STRUCTURE GicInterfaces[64];
- EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
- EFI_ACPI_6_1_GIC_ITS_STRUCTURE GicITS[8];
-} EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE;
-
-#pragma pack ()
-
EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
{
ARM_ACPI_HEADER (
--
1.9.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH edk2-platforms v2 02/15] Hisilicon/D05: Add PPTT support
2018-01-26 8:00 [PATCH edk2-platforms v2 00/15] Improve D0x platforms and bug fix Ming Huang
2018-01-26 8:00 ` [PATCH edk2-platforms v2 01/15] Hisilicon/D05: Move Madt definition to head file Ming Huang
@ 2018-01-26 8:00 ` Ming Huang
2018-01-30 14:28 ` graeme.gregory
2018-02-01 1:11 ` Jeremy Linton
2018-01-26 8:00 ` [PATCH edk2-platforms v2 03/15] Hisilicon/D0x/BDS: Switch to Generic BDS driver Ming Huang
` (13 subsequent siblings)
15 siblings, 2 replies; 30+ messages in thread
From: Ming Huang @ 2018-01-26 8:00 UTC (permalink / raw)
To: leif.lindholm, linaro-uefi, edk2-devel, graeme.gregory
Cc: ard.biesheuvel, guoheyi, wanghuiqiang, huangming23, zhangjinsong2,
mengfanrong, huangdaode, waip23, Heyi Guo
Add Processor Properties Topology Table, PPTT include
Processor hierarchy node, Cache Type Structure and ID structure.
PPTT is needed for lscpu command to show socket information correctly.
https://bugs.linaro.org/show_bug.cgi?id=3206
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
---
Platform/Hisilicon/D05/D05.dsc | 1 +
Platform/Hisilicon/D05/D05.fdf | 1 +
Silicon/Hisilicon/Hi1616/Pptt/Pptt.c | 540 ++++++++++++++++++++
Silicon/Hisilicon/Hi1616/Pptt/Pptt.h | 88 ++++
Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf | 48 ++
5 files changed, 678 insertions(+)
diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
index 77a89fd..710339c 100644
--- a/Platform/Hisilicon/D05/D05.dsc
+++ b/Platform/Hisilicon/D05/D05.dsc
@@ -506,6 +506,7 @@
MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
Silicon/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
+ Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf
Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
#
diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf
index 78ab0c8..97de4d2 100644
--- a/Platform/Hisilicon/D05/D05.fdf
+++ b/Platform/Hisilicon/D05/D05.fdf
@@ -241,6 +241,7 @@ READ_LOCK_STATUS = TRUE
INF Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
INF RuleOverride=ACPITABLE Silicon/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
+ INF Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf
INF Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
#
diff --git a/Silicon/Hisilicon/Hi1616/Pptt/Pptt.c b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.c
new file mode 100644
index 0000000..71c456c
--- /dev/null
+++ b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.c
@@ -0,0 +1,540 @@
+/** @file
+*
+* Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2018, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+* Based on the files under Platform/ARM/JunoPkg/AcpiTables/
+*
+**/
+
+#include "Pptt.h"
+
+EFI_ACPI_TABLE_PROTOCOL *mAcpiTableProtocol = NULL;
+EFI_ACPI_SDT_PROTOCOL *mAcpiSdtProtocol = NULL;
+
+EFI_ACPI_DESCRIPTION_HEADER mPpttHeader =
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_DESCRIPTION_HEADER,
+ EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ );
+
+EFI_ACPI_6_2_PPTT_STRUCTURE_ID mPpttSocketType2[PPTT_SOCKET_COMPONENT_NO] =
+{
+ {2, sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID), {0, 0}, 0, 0, 0, 0, 0, 0}
+};
+
+EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE mPpttCacheType1[PPTT_CACHE_NO];
+
+
+STATIC
+VOID
+InitCacheInfo (
+ VOID
+ )
+{
+ UINT8 Index;
+ EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES Type1Attributes;
+ CSSELR_DATA CsselrData;
+ CCSIDR_DATA CcsidrData;
+
+ for (Index = 0; Index < PPTT_CACHE_NO; Index++) {
+ CsselrData.Data = 0;
+ CcsidrData.Data = 0;
+ SetMem (
+ &Type1Attributes,
+ sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES),
+ 0
+ );
+
+ if (Index == 0) { //L1I
+ CsselrData.Bits.InD = 1;
+ CsselrData.Bits.Level = 0;
+ Type1Attributes.CacheType = 1;
+ } else if (Index == 1) {
+ Type1Attributes.CacheType = 0;
+ CsselrData.Bits.Level = Index - 1;
+ } else {
+ Type1Attributes.CacheType = 2;
+ CsselrData.Bits.Level = Index - 1;
+ }
+
+ CcsidrData.Data = ReadCCSIDR (CsselrData.Data);
+
+ if (CcsidrData.Bits.Wa == 1) {
+ Type1Attributes.AllocationType = PPTT_TYPE1_ALLOCATION_WRITE;
+ if (CcsidrData.Bits.Ra == 1) {
+ Type1Attributes.AllocationType = PPTT_TYPE1_ALLOCATION_READ_WRITE;
+ }
+ }
+
+ if (CcsidrData.Bits.Wt == 1) {
+ Type1Attributes.WritePolicy = 1;
+ }
+ DEBUG ((DEBUG_INFO,
+ "[Acpi PPTT] Level = %x!CcsidrData = %x!\n",
+ CsselrData.Bits.Level,
+ CcsidrData.Data));
+
+ mPpttCacheType1[Index].Type = EFI_ACPI_6_2_PPTT_TYPE_CACHE;
+ mPpttCacheType1[Index].Length = sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE);
+ mPpttCacheType1[Index].Reserved[0] = 0;
+ mPpttCacheType1[Index].Reserved[1] = 0;
+ mPpttCacheType1[Index].Flags.SizePropertyValid = 1;
+ mPpttCacheType1[Index].Flags.NumberOfSetsValid = 1;
+ mPpttCacheType1[Index].Flags.AssociativityValid = 1;
+ mPpttCacheType1[Index].Flags.AllocationTypeValid = 1;
+ mPpttCacheType1[Index].Flags.CacheTypeValid = 1;
+ mPpttCacheType1[Index].Flags.WritePolicyValid = 1;
+ mPpttCacheType1[Index].Flags.LineSizeValid = 1;
+ mPpttCacheType1[Index].Flags.Reserved = 0;
+ mPpttCacheType1[Index].NextLevelOfCache = 0;
+
+ if (Index != PPTT_CACHE_NO - 1) {
+ mPpttCacheType1[Index].NumberOfSets = (UINT16)CcsidrData.Bits.NumSets + 1;
+ mPpttCacheType1[Index].Associativity = (UINT16)CcsidrData.Bits.Associativity + 1;
+ mPpttCacheType1[Index].LineSize = (UINT16)( 1 << (CcsidrData.Bits.LineSize + 4));
+ mPpttCacheType1[Index].Size = mPpttCacheType1[Index].LineSize * \
+ mPpttCacheType1[Index].Associativity * \
+ mPpttCacheType1[Index].NumberOfSets;
+ CopyMem (
+ &mPpttCacheType1[Index].Attributes,
+ &Type1Attributes,
+ sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES)
+ );
+ } else {
+ // L3 cache
+ mPpttCacheType1[Index].Size = 0x1000000; // 16m
+ mPpttCacheType1[Index].NumberOfSets = 0x2000;
+ mPpttCacheType1[Index].Associativity = 0x10; // CacheAssociativity16Way
+ SetMem (
+ &mPpttCacheType1[Index].Attributes,
+ sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES),
+ 0x0A
+ );
+ mPpttCacheType1[Index].LineSize = 0x80; // 128byte
+ }
+ }
+}
+
+STATIC
+EFI_STATUS
+AddCoreTable (
+ IN EFI_ACPI_DESCRIPTION_HEADER *PpttTable,
+ IN OUT UINT32 *PpttTableLengthRemain,
+ IN UINT32 Flags,
+ IN UINT32 Parent,
+ IN UINT32 ResourceNo,
+ IN UINT32 ProcessorId
+ )
+{
+ EFI_ACPI_6_2_PPTT_TYPE0 *PpttType0;
+ EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *PpttType1;
+ UINT32 *PrivateResource;
+ UINT8 Index;
+
+ if (*PpttTableLengthRemain <
+ (sizeof (EFI_ACPI_6_2_PPTT_TYPE0) + ResourceNo * 4)) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ PpttType0 = (EFI_ACPI_6_2_PPTT_TYPE0 *)((UINT8 *)PpttTable +
+ PpttTable->Length);
+ PpttType0->Type = 0;
+ CopyMem (&PpttType0->Flags, &Flags, sizeof(PpttType0->Flags));;
+ PpttType0->Parent= Parent;
+ PpttType0->AcpiProcessorId = ProcessorId;
+ PpttType0->NumberOfPrivateResources = ResourceNo;
+ PpttType0->Length = sizeof (EFI_ACPI_6_2_PPTT_TYPE0) +
+ ResourceNo * 4;
+
+ *PpttTableLengthRemain -= (UINTN)PpttType0->Length;
+ PpttTable->Length += PpttType0->Length;
+ PrivateResource = (UINT32 *)((UINT8 *)PpttType0 +
+ sizeof (EFI_ACPI_6_2_PPTT_TYPE0));
+
+ // Add cache type structure
+ for (Index = 0; Index < ResourceNo; Index++, PrivateResource++) {
+ if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE)) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ *PrivateResource = PpttTable->Length;
+ PpttType1 = (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *)((UINT8 *)PpttTable +
+ PpttTable->Length);
+ gBS->CopyMem (
+ PpttType1,
+ &mPpttCacheType1[Index],
+ sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE)
+ );
+ *PpttTableLengthRemain -= PpttType1->Length;
+ PpttTable->Length += PpttType1->Length;
+ }
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+AddClusterTable (
+ IN EFI_ACPI_DESCRIPTION_HEADER *PpttTable,
+ IN OUT UINT32 *PpttTableLengthRemain,
+ IN UINT32 Flags,
+ IN UINT32 Parent,
+ IN UINT32 ResourceNo
+ )
+{
+ EFI_ACPI_6_2_PPTT_TYPE0 *PpttType0;
+ EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *PpttType1;
+ UINT32 *PrivateResource;
+
+ if ((*PpttTableLengthRemain) <
+ (sizeof (EFI_ACPI_6_2_PPTT_TYPE0) + ResourceNo * 4)) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ PpttType0 = (EFI_ACPI_6_2_PPTT_TYPE0 *)((UINT8 *)PpttTable +
+ PpttTable->Length);
+ PpttType0->Type = 0;
+ CopyMem (&PpttType0->Flags, &Flags, sizeof(PpttType0->Flags));;
+ PpttType0->Parent= Parent;
+ PpttType0->NumberOfPrivateResources = ResourceNo;
+ PpttType0->Length = sizeof (EFI_ACPI_6_2_PPTT_TYPE0) +
+ ResourceNo * 4;
+
+ *PpttTableLengthRemain -= PpttType0->Length;
+ PpttTable->Length += PpttType0->Length;
+ PrivateResource = (UINT32 *)((UINT8 *)PpttType0 +
+ sizeof (EFI_ACPI_6_2_PPTT_TYPE0));
+
+ // Add cache type structure
+ if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE)) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ *PrivateResource = PpttTable->Length;
+ PpttType1 = (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *)((UINT8 *)PpttTable +
+ PpttTable->Length);
+ gBS->CopyMem (
+ PpttType1,
+ &mPpttCacheType1[2],
+ sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE)
+ );
+ *PpttTableLengthRemain -= PpttType1->Length;
+ PpttTable->Length += PpttType1->Length;
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+AddScclTable (
+ IN EFI_ACPI_DESCRIPTION_HEADER *PpttTable,
+ IN OUT UINT32 *PpttTableLengthRemain,
+ IN UINT32 Flags,
+ IN UINT32 Parent,
+ IN UINT32 ResourceNo
+ )
+{
+ EFI_ACPI_6_2_PPTT_TYPE0 *PpttType0;
+ EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *PpttType1;
+ UINT32 *PrivateResource;
+
+ if (*PpttTableLengthRemain <
+ (sizeof (EFI_ACPI_6_2_PPTT_TYPE0) + ResourceNo * 4)) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ PpttType0 = (EFI_ACPI_6_2_PPTT_TYPE0 *)((UINT8 *)PpttTable +
+ PpttTable->Length);
+ PpttType0->Type = 0;
+ CopyMem (&PpttType0->Flags, &Flags, sizeof(PpttType0->Flags));;
+ PpttType0->Parent= Parent;
+ PpttType0->NumberOfPrivateResources = ResourceNo;
+ PpttType0->Length = sizeof (EFI_ACPI_6_2_PPTT_TYPE0) +
+ ResourceNo * 4;
+
+ *PpttTableLengthRemain -= PpttType0->Length;
+ PpttTable->Length += PpttType0->Length;
+ PrivateResource = (UINT32 *)((UINT8 *)PpttType0 +
+ sizeof (EFI_ACPI_6_2_PPTT_TYPE0));
+
+ // Add cache type structure
+ if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE)) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ *PrivateResource = PpttTable->Length;
+ PpttType1 = (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *)((UINT8 *)PpttTable +
+ PpttTable->Length);
+ gBS->CopyMem (
+ PpttType1,
+ &mPpttCacheType1[3],
+ sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE)
+ );
+ *PpttTableLengthRemain -= PpttType1->Length;
+ PpttTable->Length += PpttType1->Length;
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+AddSocketTable (
+ IN EFI_ACPI_DESCRIPTION_HEADER *PpttTable,
+ IN OUT UINT32 *PpttTableLengthRemain,
+ IN UINT32 Flags,
+ IN UINT32 Parent,
+ IN UINT32 ResourceNo
+ )
+{
+ EFI_ACPI_6_2_PPTT_TYPE0 *PpttType0;
+ EFI_ACPI_6_2_PPTT_STRUCTURE_ID *PpttType2;
+ UINT32 *PrivateResource;
+ UINT8 Index;
+
+ if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_TYPE0)) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ PpttType0 = (EFI_ACPI_6_2_PPTT_TYPE0 *)((UINT8 *)PpttTable +
+ PpttTable->Length);
+ PpttType0->Type = 0;
+ CopyMem (&PpttType0->Flags, &Flags, sizeof(PpttType0->Flags));;
+ PpttType0->Parent= Parent;
+ PpttType0->NumberOfPrivateResources = ResourceNo;
+ PpttType0->Length = sizeof (EFI_ACPI_6_2_PPTT_TYPE0) +
+ ResourceNo * 4;
+ PpttTable->Length += PpttType0->Length;
+
+ *PpttTableLengthRemain -= PpttType0->Length;
+ if (*PpttTableLengthRemain < ResourceNo * 4) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ PrivateResource = (UINT32 *)((UINT8 *)PpttType0 +
+ sizeof (EFI_ACPI_6_2_PPTT_TYPE0));
+ DEBUG ((DEBUG_INFO,
+ "[Acpi PPTT] sizeof(EFI_ACPI_6_2_PPTT_STRUCTURE_ID) = %x!\n",
+ sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID)));
+
+ for (Index = 0; Index < ResourceNo; Index++, PrivateResource++) {
+ if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID)) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ *PrivateResource = PpttTable->Length;
+ PpttType2 = (EFI_ACPI_6_2_PPTT_STRUCTURE_ID *)((UINT8 *)PpttTable +
+ PpttTable->Length);
+ gBS->CopyMem (
+ PpttType2,
+ &mPpttSocketType2[Index],
+ sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID)
+ );
+ *PpttTableLengthRemain -= PpttType2->Length;
+ PpttTable->Length += PpttType2->Length;
+ }
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+VOID
+GetApic (
+ IN EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE *ApicTable,
+ IN OUT EFI_ACPI_DESCRIPTION_HEADER *PpttTable,
+ IN UINT32 PpttTableLengthRemain,
+ IN UINT32 Index1
+)
+{
+ UINT32 IndexSocket, IndexSccl, IndexCluster, IndexCore;
+ UINT32 SocketOffset, ScclOffset, ClusterOffset;
+ UINT32 Parent = 0;
+ UINT32 Flags = 0;
+ UINT32 ResourceNo = 0;
+
+ // Get APIC data
+ for (IndexSocket = 0; IndexSocket < PPTT_SOCKET_NO; IndexSocket++) {
+ SocketOffset = 0;
+ for (IndexSccl = 0; IndexSccl < PPTT_SCCL_NO; IndexSccl++) {
+ ScclOffset = 0;
+ for (IndexCluster = 0; IndexCluster < PPTT_CLUSTER_NO; IndexCluster++) {
+ ClusterOffset = 0;
+ for (IndexCore = 0; IndexCore < PPTT_CORE_NO; IndexCore++) {
+ if (ApicTable->GicInterfaces[Index1].AcpiProcessorUid != Index1) {
+ // This processor is unusable
+ DEBUG ((DEBUG_ERROR, "[Acpi PPTT] Please check MADT table for UID!\n"));
+ return;
+ }
+ if ((ApicTable->GicInterfaces[Index1].Flags & BIT0) == 0) {
+ // This processor is unusable
+ Index1++;
+ continue;
+ }
+
+ if (SocketOffset == 0) {
+ // Add socket0 for type0 table
+ ResourceNo = PPTT_SOCKET_COMPONENT_NO;
+ SocketOffset = PpttTable->Length;
+ Parent = 0;
+ Flags = PPTT_TYPE0_SOCKET_FLAG;
+ AddSocketTable (
+ PpttTable,
+ &PpttTableLengthRemain,
+ Flags,
+ Parent,
+ ResourceNo
+ );
+ }
+ if (ScclOffset == 0) {
+ // Add socket0sccl0 for type0 table
+ ResourceNo = 1;
+ ScclOffset = PpttTable->Length;
+ Parent = SocketOffset;
+ Flags = PPTT_TYPE0_SCCL_FLAG;
+ AddScclTable (
+ PpttTable,
+ &PpttTableLengthRemain,
+ Flags,
+ Parent,
+ ResourceNo
+ );
+ }
+ if (ClusterOffset == 0) {
+ // Add socket0sccl0ClusterId for type0 table
+ ResourceNo = 1;
+ ClusterOffset = PpttTable->Length ;
+ Parent = ScclOffset;
+ Flags = PPTT_TYPE0_CLUSTER_FLAG;
+ AddClusterTable (
+ PpttTable,
+ &PpttTableLengthRemain,
+ Flags,
+ Parent,
+ ResourceNo
+ );
+ }
+
+ // Add socket0sccl0ClusterIdCoreId for type0 table
+ ResourceNo = 2;
+ Parent = ClusterOffset;
+ Flags = PPTT_TYPE0_CORE_FLAG;
+ AddCoreTable (
+ PpttTable,
+ &PpttTableLengthRemain,
+ Flags,
+ Parent,
+ ResourceNo,
+ Index1
+ );
+
+ Index1++;
+ }
+ }
+ }
+ }
+ return ;
+}
+
+STATIC
+VOID
+PpttSetAcpiTable (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ UINTN AcpiTableHandle;
+ EFI_STATUS Status;
+ UINT8 Checksum;
+ EFI_ACPI_SDT_HEADER *Table;
+ EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE *ApicTable;
+ EFI_ACPI_TABLE_VERSION TableVersion;
+ EFI_ACPI_DESCRIPTION_HEADER *PpttTable;
+ UINTN TableKey;
+ UINT32 Index0, Index1;
+ UINT32 PpttTableLengthRemain = 0;
+
+ gBS->CloseEvent (Event);
+
+ InitCacheInfo ();
+
+ PpttTable = (EFI_ACPI_DESCRIPTION_HEADER *)AllocateZeroPool (PPTT_TABLE_MAX_LEN);
+ gBS->CopyMem (
+ (VOID *)PpttTable,
+ &mPpttHeader,
+ sizeof (EFI_ACPI_DESCRIPTION_HEADER)
+ );
+ PpttTableLengthRemain = PPTT_TABLE_MAX_LEN - sizeof (EFI_ACPI_DESCRIPTION_HEADER);
+
+ for (Index0 = 0; Index0 < EFI_ACPI_MAX_NUM_TABLES; Index0++) {
+ Status = mAcpiSdtProtocol->GetAcpiTable (
+ Index0,
+ &Table,
+ &TableVersion,
+ &TableKey
+ );
+ if (EFI_ERROR (Status)) {
+ break;
+ }
+
+ // Find APIC table
+ if (Table->Signature == EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE) {
+ break;
+ }
+
+ }
+
+ if (!EFI_ERROR (Status) && (Index0 != EFI_ACPI_MAX_NUM_TABLES)) {
+ ApicTable = (EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE *)Table;
+ Index1 = 0;
+
+ GetApic (ApicTable, PpttTable, PpttTableLengthRemain, Index1);
+
+ Checksum = CalculateCheckSum8 ((UINT8 *)(PpttTable), PpttTable->Length);
+ PpttTable->Checksum = Checksum;
+
+ AcpiTableHandle = 0;
+ Status = mAcpiTableProtocol->InstallAcpiTable (
+ mAcpiTableProtocol,
+ PpttTable,
+ PpttTable->Length,
+ &AcpiTableHandle);
+ }
+
+ FreePool (PpttTable);
+ return ;
+}
+
+EFI_STATUS
+EFIAPI
+PpttEntryPoint(
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_EVENT ReadyToBootEvent;
+
+ Status = gBS->LocateProtocol (
+ &gEfiAcpiTableProtocolGuid,
+ NULL,
+ (VOID **)&mAcpiTableProtocol);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = gBS->LocateProtocol (
+ &gEfiAcpiSdtProtocolGuid,
+ NULL,
+ (VOID **)&mAcpiSdtProtocol);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = EfiCreateEventReadyToBootEx (
+ TPL_NOTIFY,
+ PpttSetAcpiTable,
+ NULL,
+ &ReadyToBootEvent
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ DEBUG ((DEBUG_INFO, "Acpi Pptt init done.\n"));
+
+ return Status;
+}
diff --git a/Silicon/Hisilicon/Hi1616/Pptt/Pptt.h b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.h
new file mode 100644
index 0000000..57f8386
--- /dev/null
+++ b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.h
@@ -0,0 +1,88 @@
+/** @file
+*
+* Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2018, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+* Based on the files under Platform/ARM/JunoPkg/AcpiTables/
+*
+**/
+
+#ifndef _PPTT_H_
+#define _PPTT_H_
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/ArmLib/ArmLibPrivate.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Protocol/AcpiSystemDescriptionTable.h>
+#include <Protocol/AcpiTable.h>
+#include "../D05AcpiTables/Hi1616Platform.h"
+
+#define EFI_ACPI_MAX_NUM_TABLES 20
+
+#define PPTT_TABLE_MAX_LEN 0x6000
+#define PPTT_SOCKET_NO 0x2
+#define PPTT_SCCL_NO 0x2
+#define PPTT_CLUSTER_NO 0x4
+#define PPTT_CORE_NO 0x4
+#define PPTT_SOCKET_COMPONENT_NO 0x1
+#define PPTT_CACHE_NO 0x4
+
+#define PPTT_TYPE0_PHYSICAL_PKG BIT0
+#define PPTT_TYPE0_PROCESSORID_VALID BIT1
+#define PPTT_TYPE0_SOCKET_FLAG PPTT_TYPE0_PHYSICAL_PKG
+#define PPTT_TYPE0_SCCL_FLAG 0
+#define PPTT_TYPE0_CLUSTER_FLAG 0
+#define PPTT_TYPE0_CORE_FLAG PPTT_TYPE0_PROCESSORID_VALID
+
+#define PPTT_TYPE1_ALLOCATION_WRITE 0x1
+#define PPTT_TYPE1_ALLOCATION_READ_WRITE 0x2
+
+typedef union {
+ struct {
+ UINT32 InD :1;
+ UINT32 Level :3;
+ UINT32 Reserved :28;
+ } Bits;
+ UINT32 Data;
+} CSSELR_DATA;
+
+typedef union {
+ struct {
+ UINT32 LineSize :3;
+ UINT32 Associativity :10;
+ UINT32 NumSets :15;
+ UINT32 Wa :1;
+ UINT32 Ra :1;
+ UINT32 Wb :1;
+ UINT32 Wt :1;
+ } Bits;
+ UINT32 Data;
+} CCSIDR_DATA;
+
+//
+// Processor Hierarchy Node Structure
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ UINT32 Flags;
+ UINT32 Parent;
+ UINT32 AcpiProcessorId;
+ UINT32 NumberOfPrivateResources;
+} EFI_ACPI_6_2_PPTT_TYPE0;
+
+#endif // _PPTT_H_
+
diff --git a/Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf
new file mode 100644
index 0000000..ff6f772
--- /dev/null
+++ b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf
@@ -0,0 +1,48 @@
+/** @file
+*
+* Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2018, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+* Based on the files under Platform/ARM/JunoPkg/AcpiTables/
+*
+**/
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = AcpiPptt
+ FILE_GUID = AAB14F90-DC2E-4f33-A594-C7894A5B412D
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = PpttEntryPoint
+
+[Sources.common]
+ Pptt.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+ ArmLib
+ BaseMemoryLib
+ DebugLib
+ HobLib
+ UefiDriverEntryPoint
+ UefiRuntimeServicesTableLib
+
+[Protocols]
+ gEfiAcpiSdtProtocolGuid ## PROTOCOL ALWAYS_CONSUMED
+ gEfiAcpiTableProtocolGuid ## PROTOCOL ALWAYS_CONSUMED
+
+[Depex]
+ gEfiAcpiTableProtocolGuid AND gEfiAcpiSdtProtocolGuid
+
--
1.9.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH edk2-platforms v2 03/15] Hisilicon/D0x/BDS: Switch to Generic BDS driver
2018-01-26 8:00 [PATCH edk2-platforms v2 00/15] Improve D0x platforms and bug fix Ming Huang
2018-01-26 8:00 ` [PATCH edk2-platforms v2 01/15] Hisilicon/D05: Move Madt definition to head file Ming Huang
2018-01-26 8:00 ` [PATCH edk2-platforms v2 02/15] Hisilicon/D05: Add PPTT support Ming Huang
@ 2018-01-26 8:00 ` Ming Huang
2018-01-26 8:00 ` [PATCH edk2-platforms v2 04/15] Hisilicon/D0x: Break BMC SetBoot option out into separate library Ming Huang
` (12 subsequent siblings)
15 siblings, 0 replies; 30+ messages in thread
From: Ming Huang @ 2018-01-26 8:00 UTC (permalink / raw)
To: leif.lindholm, linaro-uefi, edk2-devel, graeme.gregory
Cc: ard.biesheuvel, guoheyi, wanghuiqiang, huangming23, zhangjinsong2,
mengfanrong, huangdaode, waip23, Heyi Guo
Hisilicon-specific PlatformBootManagerLib added. It is convenient
to add specific feature, like BMC control boot option.
Remove Intel BDS from dsc file because it is out of use.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Signed-off-by: Jason Zhang <zhangjinsong2@huawei.com>
---
Platform/Hisilicon/D03/D03.dsc | 17 +-
Platform/Hisilicon/D03/D03.fdf | 3 +-
Platform/Hisilicon/D05/D05.dsc | 17 +-
Platform/Hisilicon/D05/D05.fdf | 3 +-
Silicon/Hisilicon/HisiPkg.dec | 2 +
Silicon/Hisilicon/Hisilicon.dsc.inc | 1 +
Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c | 636 ++++++++++++++++++++
Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.h | 31 +
Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf | 73 +++
9 files changed, 777 insertions(+), 6 deletions(-)
diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc
index b434f68..5fbe1f9 100644
--- a/Platform/Hisilicon/D03/D03.dsc
+++ b/Platform/Hisilicon/D03/D03.dsc
@@ -68,6 +68,13 @@
CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
PlatformBdsLib|Silicon/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf
+ UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+ BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
+ SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ PlatformBootManagerLib|Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+ FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
# USB Requirements
@@ -187,7 +194,7 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
- gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }
+ gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }|VOID*|0x0001006b
gHisiTokenSpaceGuid.PcdSysControlBaseAddress|0x40010000
gHisiTokenSpaceGuid.PcdMailBoxAddress|0x0000FFF8
@@ -405,6 +412,12 @@
MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+ MdeModulePkg/Application/UiApp/UiApp.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
+ NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
+ NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
+ }
MdeModulePkg/Application/HelloWorld/HelloWorld.inf
#
# Bds
@@ -457,7 +470,7 @@
MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
- IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
+ MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
#
# UEFI application (Shell Embedded Boot Loader)
diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf
index 0b38eb4..474f37f 100644
--- a/Platform/Hisilicon/D03/D03.fdf
+++ b/Platform/Hisilicon/D03/D03.fdf
@@ -283,6 +283,7 @@ READ_LOCK_STATUS = TRUE
INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
!endif #$(INCLUDE_TFTP_COMMAND)
+ INF MdeModulePkg/Application/UiApp/UiApp.inf
#
# Bds
#
@@ -291,7 +292,7 @@ READ_LOCK_STATUS = TRUE
INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
- INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
+ INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
[FV.FVMAIN_COMPACT]
FvAlignment = 16
diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
index 710339c..4d630da 100644
--- a/Platform/Hisilicon/D05/D05.dsc
+++ b/Platform/Hisilicon/D05/D05.dsc
@@ -84,6 +84,12 @@
CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
PlatformBdsLib|Silicon/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf
+ UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+ SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ PlatformBootManagerLib|Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+ FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
# USB Requirements
@@ -119,6 +125,7 @@
# It could be set FALSE to save size.
gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
gHisiTokenSpaceGuid.PcdIsItsSupported|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE
[PcdsFixedAtBuild.common]
gArmPlatformTokenSpaceGuid.PcdCoreCount|8
@@ -202,8 +209,8 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
- gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }
+ gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }|VOID*|0x0001006b
gHisiTokenSpaceGuid.PcdSysControlBaseAddress|0x40010000
gHisiTokenSpaceGuid.PcdMailBoxAddress|0x0000FFF8
@@ -560,6 +567,12 @@
MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+ MdeModulePkg/Application/UiApp/UiApp.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
+ NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
+ NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
+ }
#
# Bds
#
@@ -610,7 +623,7 @@
MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
- IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
+ MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
#
# UEFI application (Shell Embedded Boot Loader)
#
diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf
index 97de4d2..9f8dc2a 100644
--- a/Platform/Hisilicon/D05/D05.fdf
+++ b/Platform/Hisilicon/D05/D05.fdf
@@ -305,6 +305,7 @@ READ_LOCK_STATUS = TRUE
INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
!endif #$(INCLUDE_TFTP_COMMAND)
+ INF MdeModulePkg/Application/UiApp/UiApp.inf
#
# Bds
#
@@ -313,7 +314,7 @@ READ_LOCK_STATUS = TRUE
INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
- INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
+ INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
[FV.FVMAIN_COMPACT]
FvAlignment = 16
diff --git a/Silicon/Hisilicon/HisiPkg.dec b/Silicon/Hisilicon/HisiPkg.dec
index 81ba3be..398d0a7 100644
--- a/Silicon/Hisilicon/HisiPkg.dec
+++ b/Silicon/Hisilicon/HisiPkg.dec
@@ -94,6 +94,8 @@
gHisiTokenSpaceGuid.PcdSlotPerChannelNum|0x0|UINT32|0x40000004
+ gHisiTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }|VOID*|0x30006554
+
#FDT File Address
gHisiTokenSpaceGuid.FdtFileAddress|0x0|UINT64|0x40000005
diff --git a/Silicon/Hisilicon/Hisilicon.dsc.inc b/Silicon/Hisilicon/Hisilicon.dsc.inc
index cc23673..308064b 100644
--- a/Silicon/Hisilicon/Hisilicon.dsc.inc
+++ b/Silicon/Hisilicon/Hisilicon.dsc.inc
@@ -263,6 +263,7 @@
gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1
gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
+ gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
# DEBUG_ASSERT_ENABLED 0x01
# DEBUG_PRINT_ENABLED 0x02
diff --git a/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c b/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c
new file mode 100644
index 0000000..15df3ba
--- /dev/null
+++ b/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c
@@ -0,0 +1,636 @@
+/** @file
+ Implementation for PlatformBootManagerLib library class interfaces.
+
+ Copyright (c) 2018, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available
+ under the terms and conditions of the BSD License which accompanies this
+ distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+ WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <IndustryStandard/Pci22.h>
+#include <Library/BootLogoLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootManagerLib.h>
+#include <Library/UefiLib.h>
+#include <Protocol/DevicePath.h>
+#include <Protocol/EsrtManagement.h>
+#include <Protocol/GenericMemoryTest.h>
+#include <Protocol/GraphicsOutput.h>
+#include <Protocol/LoadedImage.h>
+#include <Protocol/PciIo.h>
+#include <Protocol/PciRootBridgeIo.h>
+#include <Guid/EventGroup.h>
+#include <Guid/TtyTerm.h>
+
+#include "PlatformBm.h"
+
+#define DP_NODE_LEN(Type) { (UINT8)sizeof (Type), (UINT8)(sizeof (Type) >> 8) }
+
+
+#pragma pack (1)
+typedef struct {
+ VENDOR_DEVICE_PATH SerialDxe;
+ UART_DEVICE_PATH Uart;
+ VENDOR_DEFINED_DEVICE_PATH TermType;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} PLATFORM_SERIAL_CONSOLE;
+#pragma pack ()
+
+#define SERIAL_DXE_FILE_GUID { \
+ 0xD3987D4B, 0x971A, 0x435F, \
+ { 0x8C, 0xAF, 0x49, 0x67, 0xEB, 0x62, 0x72, 0x41 } \
+ }
+
+EFI_GUID EblAppGuid2 = {0x3CEF354A,0x3B7A,0x4519,{0xAD,0x70,0x72,0xA1,0x34,0x69,0x83,0x11}};
+
+STATIC PLATFORM_SERIAL_CONSOLE mSerialConsole = {
+ //
+ // VENDOR_DEVICE_PATH SerialDxe
+ //
+ {
+ { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, DP_NODE_LEN (VENDOR_DEVICE_PATH) },
+ SERIAL_DXE_FILE_GUID
+ },
+
+ //
+ // UART_DEVICE_PATH Uart
+ //
+ {
+ { MESSAGING_DEVICE_PATH, MSG_UART_DP, DP_NODE_LEN (UART_DEVICE_PATH) },
+ 0, // Reserved
+ FixedPcdGet64 (PcdUartDefaultBaudRate), // BaudRate
+ FixedPcdGet8 (PcdUartDefaultDataBits), // DataBits
+ FixedPcdGet8 (PcdUartDefaultParity), // Parity
+ FixedPcdGet8 (PcdUartDefaultStopBits) // StopBits
+ },
+
+ //
+ // VENDOR_DEFINED_DEVICE_PATH TermType
+ //
+ {
+ {
+ MESSAGING_DEVICE_PATH, MSG_VENDOR_DP,
+ DP_NODE_LEN (VENDOR_DEFINED_DEVICE_PATH)
+ }
+ //
+ // Guid to be filled in dynamically
+ //
+ },
+
+ //
+ // EFI_DEVICE_PATH_PROTOCOL End
+ //
+ {
+ END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ DP_NODE_LEN (EFI_DEVICE_PATH_PROTOCOL)
+ }
+};
+
+
+#pragma pack (1)
+typedef struct {
+ USB_CLASS_DEVICE_PATH Keyboard;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} PLATFORM_USB_KEYBOARD;
+#pragma pack ()
+
+STATIC PLATFORM_USB_KEYBOARD mUsbKeyboard = {
+ //
+ // USB_CLASS_DEVICE_PATH Keyboard
+ //
+ {
+ {
+ MESSAGING_DEVICE_PATH, MSG_USB_CLASS_DP,
+ DP_NODE_LEN (USB_CLASS_DEVICE_PATH)
+ },
+ 0xFFFF, // VendorId: any
+ 0xFFFF, // ProductId: any
+ 3, // DeviceClass: HID
+ 1, // DeviceSubClass: boot
+ 1 // DeviceProtocol: keyboard
+ },
+
+ //
+ // EFI_DEVICE_PATH_PROTOCOL End
+ //
+ {
+ END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ DP_NODE_LEN (EFI_DEVICE_PATH_PROTOCOL)
+ }
+};
+
+
+/**
+ Check if the handle satisfies a particular condition.
+
+ @param[in] Handle The handle to check.
+ @param[in] ReportText A caller-allocated string passed in for reporting
+ purposes. It must never be NULL.
+
+ @retval TRUE The condition is satisfied.
+ @retval FALSE Otherwise. This includes the case when the condition could not
+ be fully evaluated due to an error.
+**/
+typedef
+BOOLEAN
+(EFIAPI *FILTER_FUNCTION) (
+ IN EFI_HANDLE Handle,
+ IN CONST CHAR16 *ReportText
+ );
+
+
+/**
+ Process a handle.
+
+ @param[in] Handle The handle to process.
+ @param[in] ReportText A caller-allocated string passed in for reporting
+ purposes. It must never be NULL.
+**/
+typedef
+VOID
+(EFIAPI *CALLBACK_FUNCTION) (
+ IN EFI_HANDLE Handle,
+ IN CONST CHAR16 *ReportText
+ );
+
+/**
+ Locate all handles that carry the specified protocol, filter them with a
+ callback function, and pass each handle that passes the filter to another
+ callback.
+
+ @param[in] ProtocolGuid The protocol to look for.
+
+ @param[in] Filter The filter function to pass each handle to. If this
+ parameter is NULL, then all handles are processed.
+
+ @param[in] Process The callback function to pass each handle to that
+ clears the filter.
+**/
+STATIC
+VOID
+FilterAndProcess (
+ IN EFI_GUID *ProtocolGuid,
+ IN FILTER_FUNCTION Filter OPTIONAL,
+ IN CALLBACK_FUNCTION Process
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE *Handles;
+ UINTN NoHandles;
+ UINTN Idx;
+
+ Status = gBS->LocateHandleBuffer (ByProtocol, ProtocolGuid,
+ NULL /* SearchKey */, &NoHandles, &Handles);
+ if (EFI_ERROR (Status)) {
+ //
+ // This is not an error, just an informative condition.
+ //
+ DEBUG ((DEBUG_VERBOSE, "%a: %g: %r\n", __FUNCTION__, ProtocolGuid,
+ Status));
+ return;
+ }
+
+ ASSERT (NoHandles > 0);
+ for (Idx = 0; Idx < NoHandles; ++Idx) {
+ CHAR16 *DevicePathText;
+ STATIC CHAR16 Fallback[] = L"<device path unavailable>";
+
+ //
+ // The ConvertDevicePathToText() function handles NULL input transparently.
+ //
+ DevicePathText = ConvertDevicePathToText (
+ DevicePathFromHandle (Handles[Idx]),
+ FALSE, // DisplayOnly
+ FALSE // AllowShortcuts
+ );
+ if (DevicePathText == NULL) {
+ DevicePathText = Fallback;
+ }
+
+ if (Filter == NULL || Filter (Handles[Idx], DevicePathText)) {
+ Process (Handles[Idx], DevicePathText);
+ }
+
+ if (DevicePathText != Fallback) {
+ FreePool (DevicePathText);
+ }
+ }
+ gBS->FreePool (Handles);
+}
+
+
+/**
+ This FILTER_FUNCTION checks if a handle corresponds to a PCI display device.
+**/
+STATIC
+BOOLEAN
+EFIAPI
+IsPciDisplay (
+ IN EFI_HANDLE Handle,
+ IN CONST CHAR16 *ReportText
+ )
+{
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ PCI_TYPE00 Pci;
+
+ Status = gBS->HandleProtocol (Handle, &gEfiPciIoProtocolGuid,
+ (VOID**)&PciIo);
+ if (EFI_ERROR (Status)) {
+ //
+ // This is not an error worth reporting.
+ //
+ return FALSE;
+ }
+
+ Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, 0 /* Offset */,
+ sizeof Pci / sizeof (UINT32), &Pci);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: %s: %r\n", __FUNCTION__, ReportText, Status));
+ return FALSE;
+ }
+
+ return IS_PCI_DISPLAY (&Pci);
+}
+
+
+/**
+ This CALLBACK_FUNCTION attempts to connect a handle non-recursively, asking
+ the matching driver to produce all first-level child handles.
+**/
+STATIC
+VOID
+EFIAPI
+Connect (
+ IN EFI_HANDLE Handle,
+ IN CONST CHAR16 *ReportText
+ )
+{
+ EFI_STATUS Status;
+
+ Status = gBS->ConnectController (
+ Handle, // ControllerHandle
+ NULL, // DriverImageHandle
+ NULL, // RemainingDevicePath -- produce all children
+ FALSE // Recursive
+ );
+ DEBUG ((EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE, "%a: %s: %r\n",
+ __FUNCTION__, ReportText, Status));
+}
+
+
+/**
+ This CALLBACK_FUNCTION retrieves the EFI_DEVICE_PATH_PROTOCOL from the
+ handle, and adds it to ConOut and ErrOut.
+**/
+STATIC
+VOID
+EFIAPI
+AddOutput (
+ IN EFI_HANDLE Handle,
+ IN CONST CHAR16 *ReportText
+ )
+{
+ EFI_STATUS Status;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+
+ DevicePath = DevicePathFromHandle (Handle);
+ if (DevicePath == NULL) {
+ DEBUG ((DEBUG_ERROR, "%a: %s: handle %p: device path not found\n",
+ __FUNCTION__, ReportText, Handle));
+ return;
+ }
+
+ Status = EfiBootManagerUpdateConsoleVariable (ConOut, DevicePath, NULL);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: %s: adding to ConOut: %r\n", __FUNCTION__,
+ ReportText, Status));
+ return;
+ }
+
+ Status = EfiBootManagerUpdateConsoleVariable (ErrOut, DevicePath, NULL);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: %s: adding to ErrOut: %r\n", __FUNCTION__,
+ ReportText, Status));
+ return;
+ }
+
+ DEBUG ((DEBUG_VERBOSE, "%a: %s: added to ConOut and ErrOut\n", __FUNCTION__,
+ ReportText));
+}
+
+STATIC
+VOID
+PlatformRegisterFvBootOption (
+ EFI_GUID *FileGuid,
+ CHAR16 *Description,
+ UINT32 Attributes
+ )
+{
+ EFI_STATUS Status;
+ INTN OptionIndex;
+ EFI_BOOT_MANAGER_LOAD_OPTION NewOption;
+ EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions;
+ UINTN BootOptionCount;
+ MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode;
+ EFI_LOADED_IMAGE_PROTOCOL *LoadedImage;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+
+ Status = gBS->HandleProtocol (
+ gImageHandle,
+ &gEfiLoadedImageProtocolGuid,
+ (VOID **) &LoadedImage
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ EfiInitializeFwVolDevicepathNode (&FileNode, FileGuid);
+ DevicePath = DevicePathFromHandle (LoadedImage->DeviceHandle);
+ ASSERT (DevicePath != NULL);
+ DevicePath = AppendDevicePathNode (
+ DevicePath,
+ (EFI_DEVICE_PATH_PROTOCOL *) &FileNode
+ );
+ ASSERT (DevicePath != NULL);
+
+ Status = EfiBootManagerInitializeLoadOption (
+ &NewOption,
+ LoadOptionNumberUnassigned,
+ LoadOptionTypeBoot,
+ Attributes,
+ Description,
+ DevicePath,
+ NULL,
+ 0
+ );
+ ASSERT_EFI_ERROR (Status);
+ FreePool (DevicePath);
+
+ BootOptions = EfiBootManagerGetLoadOptions (
+ &BootOptionCount, LoadOptionTypeBoot
+ );
+
+ OptionIndex = EfiBootManagerFindLoadOption (
+ &NewOption, BootOptions, BootOptionCount
+ );
+
+ if (OptionIndex == -1) {
+ Status = EfiBootManagerAddLoadOptionVariable (&NewOption, MAX_UINTN);
+ ASSERT_EFI_ERROR (Status);
+ }
+ EfiBootManagerFreeLoadOption (&NewOption);
+ EfiBootManagerFreeLoadOptions (BootOptions, BootOptionCount);
+}
+
+
+STATIC
+VOID
+PlatformRegisterOptionsAndKeys (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_INPUT_KEY Enter;
+ EFI_INPUT_KEY F2;
+ EFI_INPUT_KEY Esc;
+ EFI_BOOT_MANAGER_LOAD_OPTION BootOption;
+
+ //
+ // Register ENTER as CONTINUE key
+ //
+ Enter.ScanCode = SCAN_NULL;
+ Enter.UnicodeChar = CHAR_CARRIAGE_RETURN;
+ Status = EfiBootManagerRegisterContinueKeyOption (0, &Enter, NULL);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Map F2 and ESC to Boot Manager Menu
+ //
+ F2.ScanCode = SCAN_F2;
+ F2.UnicodeChar = CHAR_NULL;
+ Esc.ScanCode = SCAN_ESC;
+ Esc.UnicodeChar = CHAR_NULL;
+
+ Status = EfiBootManagerGetBootManagerMenu (&BootOption);
+ ASSERT_EFI_ERROR (Status);
+ Status = EfiBootManagerAddKeyOptionVariable (
+ NULL, (UINT16) BootOption.OptionNumber, 0, &F2, NULL
+ );
+ ASSERT (Status == EFI_SUCCESS || Status == EFI_ALREADY_STARTED);
+ Status = EfiBootManagerAddKeyOptionVariable (
+ NULL, (UINT16) BootOption.OptionNumber, 0, &Esc, NULL
+ );
+ ASSERT (Status == EFI_SUCCESS || Status == EFI_ALREADY_STARTED);
+}
+
+STATIC
+VOID
+UpdateMemory (
+ )
+{
+ EFI_STATUS Status;
+ EFI_GENERIC_MEMORY_TEST_PROTOCOL* MemoryTest;
+ BOOLEAN RequireSoftECCInit;
+
+ RequireSoftECCInit = FALSE;
+
+ // Add MemoryTest for memmap add above 4G memory.
+ Status = gBS->LocateProtocol (
+ &gEfiGenericMemTestProtocolGuid,
+ NULL,
+ (VOID **)&MemoryTest);
+ if (!EFI_ERROR (Status)) {
+ Status = MemoryTest->MemoryTestInit (
+ MemoryTest,
+ IGNORE,
+ &RequireSoftECCInit);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "MemoryTestInit fail(%r)\n", Status));
+ }
+ } else {
+ DEBUG ((DEBUG_ERROR, "Get GenericMemTestProtocol fail(%r)\n", Status));
+ }
+
+ return;
+}
+
+//
+// BDS Platform Functions
+//
+/**
+ Do the platform init, can be customized by OEM/IBV
+ Possible things that can be done in PlatformBootManagerBeforeConsole:
+ Update console variable: 1. include hot-plug devices;
+ 2. Clear ConIn and add SOL for AMT
+ Register new Driver#### or Boot####
+ Register new Key####: e.g.: F12
+ Signal ReadyToLock event
+ Authentication action: 1. connect Auth devices;
+ 2. Identify auto logon user.
+**/
+VOID
+EFIAPI
+PlatformBootManagerBeforeConsole (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ ESRT_MANAGEMENT_PROTOCOL *EsrtManagement;
+
+ //
+ // Signal EndOfDxe PI Event
+ //
+ EfiEventGroupSignal (&gEfiEndOfDxeEventGroupGuid);
+
+ //
+ //Sync Esrt Table
+ //
+ EsrtManagement = NULL;
+ Status = gBS->LocateProtocol (
+ &gEsrtManagementProtocolGuid,
+ NULL,
+ (VOID **)&EsrtManagement);
+ if (!EFI_ERROR (Status)) {
+ Status = EsrtManagement->SyncEsrtFmp ();
+ }
+
+ UpdateMemory ();
+
+ //
+ // Locate the PCI root bridges and make the PCI bus driver connect each,
+ // non-recursively. This will produce a number of child handles with PciIo on
+ // them.
+ //
+ FilterAndProcess (&gEfiPciRootBridgeIoProtocolGuid, NULL, Connect);
+
+ //
+ // Find all display class PCI devices (using the handles from the previous
+ // step), and connect them non-recursively. This should produce a number of
+ // child handles with GOPs on them.
+ //
+ FilterAndProcess (&gEfiPciIoProtocolGuid, IsPciDisplay, Connect);
+
+ //
+ // Now add the device path of all handles with GOP on them to ConOut and
+ // ErrOut.
+ //
+ FilterAndProcess (&gEfiGraphicsOutputProtocolGuid, NULL, AddOutput);
+
+ //
+ // Add the hardcoded short-form USB keyboard device path to ConIn.
+ //
+ EfiBootManagerUpdateConsoleVariable (ConIn,
+ (EFI_DEVICE_PATH_PROTOCOL *)&mUsbKeyboard, NULL);
+
+ //
+ // Add the hardcoded serial console device path to ConIn, ConOut, ErrOut.
+ //
+ ASSERT (FixedPcdGet8 (PcdDefaultTerminalType) == 4);
+ CopyGuid (&mSerialConsole.TermType.Guid, &gEfiTtyTermGuid);
+
+ EfiBootManagerUpdateConsoleVariable (ConIn,
+ (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL);
+ EfiBootManagerUpdateConsoleVariable (ConOut,
+ (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL);
+ EfiBootManagerUpdateConsoleVariable (ErrOut,
+ (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL);
+
+ //
+ // Register platform-specific boot options and keyboard shortcuts.
+ //
+ PlatformRegisterOptionsAndKeys ();
+}
+
+/**
+ Do the platform specific action after the console is ready
+ Possible things that can be done in PlatformBootManagerAfterConsole:
+ Console post action:
+ Dynamically switch output mode from 100x31 to 80x25 for certain senarino
+ Signal console ready platform customized event
+ Run diagnostics like memory testing
+ Connect certain devices
+ Dispatch aditional option roms
+ Special boot: e.g.: USB boot, enter UI
+**/
+VOID
+EFIAPI
+PlatformBootManagerAfterConsole (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ ESRT_MANAGEMENT_PROTOCOL *EsrtManagement = NULL;
+
+ //
+ // Show the splash screen.
+ //
+ BootLogoEnableLogo ();
+
+ //
+ // Connect the rest of the devices.
+ //
+ EfiBootManagerConnectAll ();
+
+ //
+ // Enumerate all possible boot options.
+ //
+ EfiBootManagerRefreshAllBootOption ();
+
+ //
+ // Sync Esrt Table
+ //
+ Status = gBS->LocateProtocol (
+ &gEsrtManagementProtocolGuid,
+ NULL,
+ (VOID **)&EsrtManagement);
+ if (!EFI_ERROR (Status)) {
+ Status = EsrtManagement->SyncEsrtFmp ();
+ }
+
+ //
+ // Register UEFI Shell
+ //
+ PlatformRegisterFvBootOption (
+ PcdGetPtr (PcdShellFile), L"UEFI Shell", LOAD_OPTION_ACTIVE
+ );
+}
+
+/**
+ This function is called each second during the boot manager waits the
+ timeout.
+
+ @param TimeoutRemain The remaining timeout.
+**/
+VOID
+EFIAPI
+PlatformBootManagerWaitCallback (
+ UINT16 TimeoutRemain
+ )
+{
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL_UNION Black;
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL_UNION White;
+ UINT16 Timeout;
+
+ Print(L"\r%-2d seconds left, Press Esc or F2 to enter Setup.", TimeoutRemain);
+ Timeout = PcdGet16 (PcdPlatformBootTimeOut);
+
+ Black.Raw = 0x00000000;
+ White.Raw = 0x00FFFFFF;
+
+ BootLogoUpdateProgress (
+ White.Pixel,
+ Black.Pixel,
+ L"Start boot option",
+ White.Pixel,
+ (Timeout - TimeoutRemain) * 100 / Timeout,
+ 0
+ );
+}
diff --git a/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.h b/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.h
new file mode 100644
index 0000000..4067e93
--- /dev/null
+++ b/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.h
@@ -0,0 +1,31 @@
+/** @file
+ Head file for BDS Platform specific code
+
+ Copyright (c) 2018, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available
+ under the terms and conditions of the BSD License which accompanies this
+ distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+ WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PLATFORM_BM_H_
+#define _PLATFORM_BM_H_
+
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+
+
+#endif // _PLATFORM_BM_H_
diff --git a/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf b/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
new file mode 100644
index 0000000..27ef64b
--- /dev/null
+++ b/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
@@ -0,0 +1,73 @@
+## @file
+# Implementation for PlatformBootManagerLib library class interfaces.
+#
+# Copyright (c) 2018, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available
+# under the terms and conditions of the BSD License which accompanies this
+# distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+# IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = PlatformBootManagerLib
+ FILE_GUID = f2a6b1de-479e-4212-859e-f014ddd27b66
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PlatformBootManagerLib|DXE_DRIVER
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = ARM AARCH64
+#
+
+[Sources]
+ PlatformBm.c
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ BootLogoLib
+ DebugLib
+ DevicePathLib
+ DxeServicesLib
+ MemoryAllocationLib
+ PcdLib
+ PrintLib
+ UefiBootManagerLib
+ UefiBootServicesTableLib
+ UefiLib
+
+[FixedPcd]
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
+ gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType
+ gHisiTokenSpaceGuid.PcdShellFile
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut
+
+[Guids]
+ gEfiEndOfDxeEventGroupGuid
+ gEfiTtyTermGuid
+
+[Protocols]
+ gEfiGenericMemTestProtocolGuid
+ gEfiLoadedImageProtocolGuid
+ gEsrtManagementProtocolGuid
--
1.9.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH edk2-platforms v2 04/15] Hisilicon/D0x: Break BMC SetBoot option out into separate library
2018-01-26 8:00 [PATCH edk2-platforms v2 00/15] Improve D0x platforms and bug fix Ming Huang
` (2 preceding siblings ...)
2018-01-26 8:00 ` [PATCH edk2-platforms v2 03/15] Hisilicon/D0x/BDS: Switch to Generic BDS driver Ming Huang
@ 2018-01-26 8:00 ` Ming Huang
2018-01-26 8:00 ` [PATCH edk2-platforms v2 05/15] Hisilicon D03/D05: Add capsule upgrade support Ming Huang
` (11 subsequent siblings)
15 siblings, 0 replies; 30+ messages in thread
From: Ming Huang @ 2018-01-26 8:00 UTC (permalink / raw)
To: leif.lindholm, linaro-uefi, edk2-devel, graeme.gregory
Cc: ard.biesheuvel, guoheyi, wanghuiqiang, huangming23, zhangjinsong2,
mengfanrong, huangdaode, waip23, Heyi Guo
Modify the feature of BMC set boot option as switching generic
BDS. Break BMC SetBoot option out into BmcConfigBootLib.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
---
Platform/Hisilicon/D03/D03.dsc | 1 +
Platform/Hisilicon/D05/D05.dsc | 1 +
Silicon/Hisilicon/HisiPkg.dec | 1 +
Silicon/Hisilicon/Include/Library/BmcConfigBootLib.h | 31 ++
Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.c | 466 ++++++++++++++++++++
Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf | 51 +++
Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c | 7 +
Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf | 1 +
8 files changed, 559 insertions(+)
diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc
index 5fbe1f9..e1e3b14 100644
--- a/Platform/Hisilicon/D03/D03.dsc
+++ b/Platform/Hisilicon/D03/D03.dsc
@@ -68,6 +68,7 @@
CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
PlatformBdsLib|Silicon/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf
+ BmcConfigBootLib|Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf
UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
index 4d630da..ac7da04 100644
--- a/Platform/Hisilicon/D05/D05.dsc
+++ b/Platform/Hisilicon/D05/D05.dsc
@@ -84,6 +84,7 @@
CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
PlatformBdsLib|Silicon/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf
+ BmcConfigBootLib|Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf
UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
diff --git a/Silicon/Hisilicon/HisiPkg.dec b/Silicon/Hisilicon/HisiPkg.dec
index 398d0a7..889a181 100644
--- a/Silicon/Hisilicon/HisiPkg.dec
+++ b/Silicon/Hisilicon/HisiPkg.dec
@@ -43,6 +43,7 @@
gHisiEfiMemoryMapGuid = {0xf8870015, 0x6994, 0x4b98, {0x95, 0xa2, 0xbd, 0x56, 0xda, 0x91, 0xc0, 0x7f}}
gVersionInfoHobGuid = {0xe13a14c, 0x859c, 0x4f22, {0x82, 0xbd, 0x18, 0xe, 0xe1, 0x42, 0x12, 0xbf}}
+ gOemBootVariableGuid = {0xb7784577, 0x5aaf, 0x4557, {0xa1, 0x99, 0xd4, 0xa4, 0x2f, 0x45, 0x06, 0xf8}}
[LibraryClasses]
PlatformSysCtrlLib|Include/Library/PlatformSysCtrlLib.h
diff --git a/Silicon/Hisilicon/Include/Library/BmcConfigBootLib.h b/Silicon/Hisilicon/Include/Library/BmcConfigBootLib.h
new file mode 100644
index 0000000..d937234
--- /dev/null
+++ b/Silicon/Hisilicon/Include/Library/BmcConfigBootLib.h
@@ -0,0 +1,31 @@
+/** @file
+*
+* Copyright (c) 2017, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2017, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _BMC_CONFIG_BOOT_LIB_H_
+#define _BMC_CONFIG_BOOT_LIB_H_
+
+VOID
+EFIAPI
+RestoreBootOrder (
+ VOID
+ );
+
+VOID
+EFIAPI
+HandleBmcBootType (
+ VOID
+ );
+
+#endif
diff --git a/Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.c b/Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.c
new file mode 100644
index 0000000..08a9c9c
--- /dev/null
+++ b/Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.c
@@ -0,0 +1,466 @@
+/** @file
+*
+* Copyright (c) 2017, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2017, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/IpmiCmdLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PrintLib.h>
+#include <Library/UefiBootManagerLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Guid/GlobalVariable.h>
+#include <Protocol/DevicePathToText.h>
+
+
+STATIC
+UINT16
+EFIAPI
+GetBBSTypeFromFileSysPath (
+ IN CHAR16 *UsbPathTxt,
+ IN CHAR16 *FileSysPathTxt,
+ IN EFI_DEVICE_PATH_PROTOCOL *FileSysPath
+ )
+{
+ EFI_DEVICE_PATH_PROTOCOL *Node;
+
+ if (StrnCmp (UsbPathTxt, FileSysPathTxt, StrLen (UsbPathTxt)) == 0) {
+ Node = FileSysPath;
+ while (!IsDevicePathEnd (Node)) {
+ if ((DevicePathType (Node) == MEDIA_DEVICE_PATH) &&
+ (DevicePathSubType (Node) == MEDIA_CDROM_DP)) {
+ return BBS_TYPE_CDROM;
+ }
+ Node = NextDevicePathNode (Node);
+ }
+ }
+
+ return BBS_TYPE_UNKNOWN;
+}
+
+STATIC
+UINT16
+EFIAPI
+GetBBSTypeFromUsbPath (
+ IN CONST EFI_DEVICE_PATH_PROTOCOL *UsbPath
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE *FileSystemHandles;
+ UINTN NumberFileSystemHandles;
+ UINTN Index;
+ EFI_DEVICE_PATH_PROTOCOL *FileSysPath;
+ EFI_DEVICE_PATH_TO_TEXT_PROTOCOL *DevPathToText;
+ CHAR16 *UsbPathTxt;
+ CHAR16 *FileSysPathTxt;
+ UINT16 Result;
+
+ Status = gBS->LocateProtocol (
+ &gEfiDevicePathToTextProtocolGuid,
+ NULL,
+ (VOID **) &DevPathToText);
+ ASSERT_EFI_ERROR(Status);
+
+ Result = BBS_TYPE_UNKNOWN;
+ UsbPathTxt = DevPathToText->ConvertDevicePathToText (UsbPath, TRUE, TRUE);
+ if (UsbPathTxt == NULL) {
+ return Result;
+ }
+
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiSimpleFileSystemProtocolGuid,
+ NULL,
+ &NumberFileSystemHandles,
+ &FileSystemHandles
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Locate SimpleFileSystemProtocol error(%r)\n", Status));
+ FreePool (UsbPathTxt);
+ return BBS_TYPE_UNKNOWN;
+ }
+
+ for (Index = 0; Index < NumberFileSystemHandles; Index++) {
+ FileSysPath = DevicePathFromHandle (FileSystemHandles[Index]);
+ FileSysPathTxt = DevPathToText->ConvertDevicePathToText (FileSysPath, TRUE, TRUE);
+
+ if (FileSysPathTxt == NULL) {
+ continue;
+ }
+
+ Result = GetBBSTypeFromFileSysPath (UsbPathTxt, FileSysPathTxt, FileSysPath);
+ FreePool (FileSysPathTxt);
+
+ if (Result != BBS_TYPE_UNKNOWN) {
+ break;
+ }
+ }
+
+ if (NumberFileSystemHandles != 0) {
+ FreePool (FileSystemHandles);
+ }
+
+ FreePool (UsbPathTxt);
+
+ return Result;
+}
+
+STATIC
+UINT16
+EFIAPI
+GetBBSTypeFromMessagingDevicePath (
+ IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
+ IN EFI_DEVICE_PATH_PROTOCOL *Node
+ )
+{
+ VENDOR_DEVICE_PATH *Vendor;
+ UINT16 Result;
+
+ Result = BBS_TYPE_UNKNOWN;
+
+ switch (DevicePathSubType (Node)) {
+ case MSG_MAC_ADDR_DP:
+ Result = BBS_TYPE_EMBEDDED_NETWORK;
+ break;
+
+ case MSG_USB_DP:
+ Result = GetBBSTypeFromUsbPath (DevicePath);
+ if (Result == BBS_TYPE_UNKNOWN) {
+ Result = BBS_TYPE_USB;
+ }
+ break;
+
+ case MSG_SATA_DP:
+ Result = BBS_TYPE_HARDDRIVE;
+ break;
+
+ case MSG_VENDOR_DP:
+ Vendor = (VENDOR_DEVICE_PATH *) (Node);
+ if (&Vendor->Guid != NULL) {
+ if (CompareGuid (&Vendor->Guid, &((EFI_GUID) DEVICE_PATH_MESSAGING_SAS))) {
+ Result = BBS_TYPE_HARDDRIVE;
+ }
+ }
+ break;
+
+ default:
+ Result = BBS_TYPE_UNKNOWN;
+ break;
+ }
+
+ return Result;
+}
+
+STATIC
+UINT16
+EFIAPI
+GetBBSTypeByDevicePath (
+ IN EFI_DEVICE_PATH_PROTOCOL *DevicePath
+ )
+{
+ EFI_DEVICE_PATH_PROTOCOL *Node;
+ UINT16 Result;
+
+ Result = BBS_TYPE_UNKNOWN;
+ if (DevicePath == NULL) {
+ return Result;
+ }
+
+ Node = DevicePath;
+ while (!IsDevicePathEnd (Node)) {
+ switch (DevicePathType (Node)) {
+ case MEDIA_DEVICE_PATH:
+ if (DevicePathSubType (Node) == MEDIA_CDROM_DP) {
+ Result = BBS_TYPE_CDROM;
+ }
+ break;
+
+ case MESSAGING_DEVICE_PATH:
+ Result = GetBBSTypeFromMessagingDevicePath (DevicePath, Node);
+ break;
+
+ default:
+ Result = BBS_TYPE_UNKNOWN;
+ break;
+ }
+
+ if (Result != BBS_TYPE_UNKNOWN) {
+ break;
+ }
+
+ Node = NextDevicePathNode (Node);
+ }
+
+ return Result;
+}
+
+STATIC
+EFI_STATUS
+EFIAPI
+GetBmcBootOptionsSetting (
+ OUT IPMI_GET_BOOT_OPTION *BmcBootOpt
+ )
+{
+ EFI_STATUS Status;
+
+ Status = IpmiCmdGetSysBootOptions (BmcBootOpt);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Get iBMC BootOpts %r!\n", Status));
+ return Status;
+ }
+
+ if (BmcBootOpt->BootFlagsValid != BOOT_OPTION_BOOT_FLAG_VALID) {
+ return EFI_NOT_FOUND;
+ }
+
+ if (BmcBootOpt->Persistent) {
+ BmcBootOpt->BootFlagsValid = BOOT_OPTION_BOOT_FLAG_VALID;
+ } else {
+ BmcBootOpt->BootFlagsValid = BOOT_OPTION_BOOT_FLAG_INVALID;
+ }
+
+ Status = IpmiCmdSetSysBootOptions (BmcBootOpt);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Set iBMC BootOpts %r!\n", Status));
+ }
+
+ return Status;
+}
+
+VOID
+EFIAPI
+RestoreBootOrder (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UINT16 *BootOrder;
+ UINTN BootOrderSize;
+
+ GetVariable2 (
+ L"BootOrderBackup",
+ &gOemBootVariableGuid,
+ (VOID **) &BootOrder,
+ &BootOrderSize
+ );
+ if (BootOrder == NULL) {
+ return ;
+ }
+
+ Print (L"\nRestore BootOrder(%d).\n", BootOrderSize / sizeof (UINT16));
+
+ Status = gRT->SetVariable (
+ L"BootOrder",
+ &gEfiGlobalVariableGuid,
+ EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS
+ | EFI_VARIABLE_NON_VOLATILE,
+ BootOrderSize,
+ BootOrder
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "SetVariable BootOrder %r!\n", Status));
+ }
+
+ Status = gRT->SetVariable (
+ L"BootOrderBackup",
+ &gOemBootVariableGuid,
+ EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_NON_VOLATILE,
+ 0,
+ NULL
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "SetVariable BootOrderBackup %r!\n", Status));
+ }
+
+ FreePool (BootOrder);
+}
+
+
+STATIC
+VOID
+EFIAPI
+RestoreBootOrderOnReadyToBoot (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ // restore BootOrder variable in normal condition.
+ RestoreBootOrder ();
+}
+
+STATIC
+VOID
+EFIAPI
+UpdateBootOrder (
+ IN UINT16 *NewOrder,
+ IN UINT16 *BootOrder,
+ IN UINTN BootOrderSize
+ )
+{
+ EFI_STATUS Status;
+ EFI_EVENT Event;
+
+ Status = gRT->SetVariable (
+ L"BootOrderBackup",
+ &gOemBootVariableGuid,
+ EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_NON_VOLATILE,
+ BootOrderSize,
+ BootOrder
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Set BootOrderBackup Variable:%r!\n", Status));
+ return;
+ }
+
+ Status = gRT->SetVariable (
+ L"BootOrder",
+ &gEfiGlobalVariableGuid,
+ EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS
+ | EFI_VARIABLE_NON_VOLATILE,
+ BootOrderSize,
+ NewOrder
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Set BootOrder Variable:%r!\n", Status));
+ return;
+ }
+
+ // Register notify function to restore BootOrder variable on ReadyToBoot Event.
+ Status = gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_CALLBACK,
+ RestoreBootOrderOnReadyToBoot,
+ NULL,
+ &gEfiEventReadyToBootGuid,
+ &Event
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Create ready to boot event %r!\n", Status));
+ }
+}
+
+STATIC
+VOID
+EFIAPI
+SetBootOrder (
+ IN UINT16 BootType
+ )
+{
+ EFI_STATUS Status;
+ UINT16 *NewOrder;
+ UINT16 *RemainBoots;
+ UINT16 *BootOrder;
+ UINTN BootOrderSize;
+ EFI_BOOT_MANAGER_LOAD_OPTION Option;
+ CHAR16 OptionName[sizeof ("Boot####")];
+ UINTN Index;
+ UINTN SelectCnt;
+ UINTN RemainCnt;
+
+ GetEfiGlobalVariable2 (L"BootOrder", (VOID **) &BootOrder, &BootOrderSize);
+ if (BootOrder == NULL) {
+ return ;
+ }
+
+ NewOrder = AllocatePool (BootOrderSize);
+ RemainBoots = AllocatePool (BootOrderSize);
+ if ((NewOrder == NULL) || (RemainBoots == NULL)) {
+ DEBUG ((DEBUG_ERROR, "Out of resources."));
+ goto Exit;
+ }
+
+ SelectCnt = 0;
+ RemainCnt = 0;
+
+ for (Index = 0; Index < BootOrderSize / sizeof (UINT16); Index++) {
+ UnicodeSPrint (OptionName, sizeof (OptionName), L"Boot%04x", BootOrder[Index]);
+ Status = EfiBootManagerVariableToLoadOption (OptionName, &Option);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Boot%04x is invalid option!\n", BootOrder[Index]));
+ continue;
+ }
+
+ if (GetBBSTypeByDevicePath (Option.FilePath) == BootType) {
+ NewOrder[SelectCnt++] = BootOrder[Index];
+ } else {
+ RemainBoots[RemainCnt++] = BootOrder[Index];
+ }
+ }
+
+ if (SelectCnt != 0) {
+ // append RemainBoots to NewOrder
+ for (Index = 0; Index < RemainCnt; Index++) {
+ NewOrder[SelectCnt + Index] = RemainBoots[Index];
+ }
+
+ if (CompareMem (NewOrder, BootOrder, BootOrderSize) != 0) {
+ UpdateBootOrder (NewOrder, BootOrder, BootOrderSize);
+ }
+ }
+
+Exit:
+ FreePool (BootOrder);
+ if (NewOrder != NULL) {
+ FreePool (NewOrder);
+ }
+ if (RemainBoots != NULL) {
+ FreePool (RemainBoots);
+ }
+}
+
+VOID
+EFIAPI
+HandleBmcBootType (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ IPMI_GET_BOOT_OPTION BmcBootOpt;
+ UINT16 BootType;
+
+ Status = GetBmcBootOptionsSetting (&BmcBootOpt);
+ if (EFI_ERROR (Status)) {
+ return;
+ }
+
+ Print (L"Boot Type from BMC is %x\n", BmcBootOpt.BootDeviceSelector);
+
+ switch (BmcBootOpt.BootDeviceSelector) {
+ case ForcePxe:
+ BootType = BBS_TYPE_EMBEDDED_NETWORK;
+ break;
+
+ case ForcePrimaryRemovableMedia:
+ BootType = BBS_TYPE_USB;
+ break;
+
+ case ForceDefaultHardDisk:
+ BootType = BBS_TYPE_HARDDRIVE;
+ break;
+
+ case ForceDefaultCD:
+ BootType = BBS_TYPE_CDROM;
+ break;
+
+ default:
+ return;
+ }
+
+ SetBootOrder (BootType);
+}
+
diff --git a/Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf b/Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf
new file mode 100644
index 0000000..b603523
--- /dev/null
+++ b/Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf
@@ -0,0 +1,51 @@
+#/** @file
+#
+# Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = BmcConfigBootLib
+ FILE_GUID = f174d192-7208-46c1-b9d1-65b2db06ad3b
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = BmcConfigBootLib
+
+[Sources.common]
+ BmcConfigBootLib.c
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ DevicePathLib
+ IpmiCmdLib
+ PcdLib
+ PrintLib
+ UefiBootManagerLib
+
+[Guids]
+ gEfiEventReadyToBootGuid
+ gOemBootVariableGuid
+
+[Protocols]
+ gEfiDevicePathToTextProtocolGuid ## CONSUMES
+ gEfiSimpleFileSystemProtocolGuid ## CONSUMES
+
+[Depex]
+ gEfiDevicePathToTextProtocolGuid
diff --git a/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c b/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c
index 15df3ba..7dd5ba6 100644
--- a/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c
+++ b/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c
@@ -17,6 +17,7 @@
#include <IndustryStandard/Pci22.h>
#include <Library/BootLogoLib.h>
+#include <Library/BmcConfigBootLib.h>
#include <Library/DevicePathLib.h>
#include <Library/PcdLib.h>
#include <Library/UefiBootManagerLib.h>
@@ -502,6 +503,10 @@ PlatformBootManagerBeforeConsole (
Status = EsrtManagement->SyncEsrtFmp ();
}
+ // restore BootOrder variable if previous BMC boot override attempt
+ // left it in a modified state
+ RestoreBootOrder ();
+
UpdateMemory ();
//
@@ -601,6 +606,8 @@ PlatformBootManagerAfterConsole (
PlatformRegisterFvBootOption (
PcdGetPtr (PcdShellFile), L"UEFI Shell", LOAD_OPTION_ACTIVE
);
+
+ HandleBmcBootType ();
}
/**
diff --git a/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf b/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
index 27ef64b..7a53bef 100644
--- a/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+++ b/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
@@ -42,6 +42,7 @@
BaseLib
BaseMemoryLib
BootLogoLib
+ BmcConfigBootLib
DebugLib
DevicePathLib
DxeServicesLib
--
1.9.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH edk2-platforms v2 05/15] Hisilicon D03/D05: Add capsule upgrade support
2018-01-26 8:00 [PATCH edk2-platforms v2 00/15] Improve D0x platforms and bug fix Ming Huang
` (3 preceding siblings ...)
2018-01-26 8:00 ` [PATCH edk2-platforms v2 04/15] Hisilicon/D0x: Break BMC SetBoot option out into separate library Ming Huang
@ 2018-01-26 8:00 ` Ming Huang
2018-01-29 19:58 ` Leif Lindholm
2018-01-30 12:47 ` Ard Biesheuvel
2018-01-26 8:00 ` [PATCH edk2-platforms v2 06/15] Hisilicon D03/D05: Open SasPlatform source code Ming Huang
` (10 subsequent siblings)
15 siblings, 2 replies; 30+ messages in thread
From: Ming Huang @ 2018-01-26 8:00 UTC (permalink / raw)
To: leif.lindholm, linaro-uefi, edk2-devel, graeme.gregory
Cc: ard.biesheuvel, guoheyi, wanghuiqiang, huangming23, zhangjinsong2,
mengfanrong, huangdaode, waip23, Heyi Guo
From: Jason Zhang <zhangjinsong2@huawei.com>
This module support updating the boot CPU firmware only.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jason Zhang <zhangjinsong2@huawei.com>
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
---
Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini | 45 +++++++
Platform/Hisilicon/D03/D03.dsc | 17 ++-
Platform/Hisilicon/D03/D03.fdf | 70 +++++++++++
Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc | 81 +++++++++++++
Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 50 ++++++++
Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c | 70 +++++++++++
Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini | 45 +++++++
Platform/Hisilicon/D05/D05.dsc | 19 ++-
Platform/Hisilicon/D05/D05.fdf | 70 +++++++++++
Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc | 81 +++++++++++++
Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 50 ++++++++
Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c | 70 +++++++++++
Silicon/Hisilicon/Hisilicon.dsc.inc | 11 +-
Silicon/Hisilicon/Hisilicon.fdf.inc | 9 ++
Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c | 123 ++++++++++++++++++++
Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf | 51 ++++++++
16 files changed, 859 insertions(+), 3 deletions(-)
diff --git a/Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini b/Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
new file mode 100644
index 0000000..fc834d9
--- /dev/null
+++ b/Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
@@ -0,0 +1,45 @@
+#
+# Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2018, Linaro Limited. All rights reserved.
+# Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Head]
+NumOfUpdate = 3
+NumOfRecovery = 0
+Update0 = SysFvMain
+Update1 = SysCustom
+Update2 = SysNvRam
+
+[SysFvMain]
+FirmwareType = 0 # 0 - SystemFirmware, 1 - NvRam
+AddressType = 0 # 0 - relative address, 1 - absolute address.
+BaseAddress = 0x00000000 # Base address offset on flash
+Length = 0x002D0000 # Length
+ImageOffset = 0x00000000 # Image offset of this SystemFirmware image
+FileGuid = 642e4fcf-2df7-4415-8b70-a03909c57b55 # PcdEdkiiSystemFirmwareFileGuid
+
+[SysCustom]
+FirmwareType = 0 # 0 - SystemFirmware, 1 - NvRam
+AddressType = 0 # 0 - relative address, 1 - absolute address.
+BaseAddress = 0x002F0000 # Base address offset on flash
+Length = 0x00010000 # Length
+ImageOffset = 0x002F0000 # Image offset of this SystemFirmware image
+FileGuid = 642e4fcf-2df7-4415-8b70-a03909c57b55 # PcdEdkiiSystemFirmwareFileGuid
+
+[SysNvRam]
+FirmwareType = 1 # 0 - SystemFirmware, 1 - NvRam
+AddressType = 0 # 0 - relative address, 1 - absolute address.
+BaseAddress = 0x002D0000 # Base address offset on flash
+Length = 0x00020000 # Length
+ImageOffset = 0x002D0000 # Image offset of this SystemFirmware image
+FileGuid = 642e4fcf-2df7-4415-8b70-a03909c57b55 # PcdEdkiiSystemFirmwareFileGuid
diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc
index e1e3b14..82c8bb4 100644
--- a/Platform/Hisilicon/D03/D03.dsc
+++ b/Platform/Hisilicon/D03/D03.dsc
@@ -65,7 +65,6 @@
OemAddressMapLib|Platform/Hisilicon/D03/Library/OemAddressMap2P/OemAddressMap2PHi1610.inf
PlatformSysCtrlLib|Silicon/Hisilicon/Hi1610/Library/PlatformSysCtrlLibHi1610/PlatformSysCtrlLibHi1610.inf
- CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
PlatformBdsLib|Silicon/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf
BmcConfigBootLib|Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf
@@ -115,6 +114,11 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
gHisiTokenSpaceGuid.PcdIsItsSupported|TRUE
+[PcdsDynamicExDefault.common.DEFAULT]
+ gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor|{0x0}|VOID*|0x100
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSystemFmpCapsuleImageTypeIdGuid|{0x29, 0x3d, 0x4b, 0xd3, 0x85, 0x00, 0xb3, 0x4a, 0x8b, 0xe8, 0x84, 0x18, 0x8c, 0xc5, 0x04, 0x89}
+ gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareFileGuid|{0xcf, 0x4f, 0x2e, 0x64, 0xf7, 0x2d, 0x15, 0x44, 0x8b, 0x70, 0xa0, 0x39, 0x09, 0xc5, 0x7b, 0x55}
+
[PcdsFixedAtBuild.common]
gArmPlatformTokenSpaceGuid.PcdCoreCount|8
@@ -305,6 +309,8 @@
Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf
Silicon/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
+ Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
+
MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
<LibraryClasses>
NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
@@ -405,6 +411,9 @@
Platform/Hisilicon/D03/Drivers/Sas/SasDxeDriver.inf
+ SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf
+ MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf
+
#
# FAT filesystem + GPT/MBR partitioning
#
@@ -472,6 +481,12 @@
MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf {
+ <LibraryClasses>
+ FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibPkcs7/FmpAuthenticationLibPkcs7.inf
+ }
+
+ MdeModulePkg/Application/CapsuleApp/CapsuleApp.inf
#
# UEFI application (Shell Embedded Boot Loader)
diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf
index 474f37f..6462a53 100644
--- a/Platform/Hisilicon/D03/D03.fdf
+++ b/Platform/Hisilicon/D03/D03.fdf
@@ -275,6 +275,8 @@ READ_LOCK_STATUS = TRUE
INF Platform/Hisilicon/D03/Drivers/SasPlatform/SasPlatform.inf
INF Platform/Hisilicon/D03/Drivers/Sas/SasDxeDriver.inf
+ INF SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf
+ INF MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf
#
# Build Shell from latest source code instead of prebuilt binary
#
@@ -330,12 +332,80 @@ READ_LOCK_STATUS = TRUE
INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+ INF RuleOverride = FMP_IMAGE_DESC Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
+
FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
SECTION FV_IMAGE = FVMAIN
}
}
+[FV.CapsuleDispatchFv]
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf
+
+[FV.SystemFirmwareUpdateCargo]
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ FILE RAW = 642e4fcf-2df7-4415-8b70-a03909c57b55 { # PcdEdkiiSystemFirmwareFileGuid
+ FD = D03
+ }
+
+ FILE RAW = ce57b167-b0e4-41e8-a897-5f4feb781d40 { # gEdkiiSystemFmpCapsuleDriverFvFileGuid
+ FV = CapsuleDispatchFv
+ }
+
+ FILE RAW = 812136D3-4D3A-433A-9418-29BB9BF78F6E { # gEdkiiSystemFmpCapsuleConfigFileGuid
+ Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
+ }
+
+[FmpPayload.FmpPayloadSystemFirmwarePkcs7]
+IMAGE_HEADER_INIT_VERSION = 0x02
+IMAGE_TYPE_ID = 44c850f2-85ff-4be5-bf34-a59528df22d3 # PcdSystemFmpCapsuleImageTypeIdGuid
+IMAGE_INDEX = 0x1
+HARDWARE_INSTANCE = 0x0
+MONOTONIC_COUNT = 0x1
+CERTIFICATE_GUID = 4AAFD29D-68DF-49EE-8AA9-347D375665A7 # PKCS7
+
+ FV = SystemFirmwareUpdateCargo
+
+[Capsule.StyxFirmwareUpdateCapsuleFmpPkcs7]
+CAPSULE_GUID = 6dcbd5ed-e82d-4c44-bda1-7194199ad92a # gEfiFmpCapsuleGuid
+CAPSULE_HEADER_SIZE = 0x20
+CAPSULE_HEADER_INIT_VERSION = 0x1
+
+ FMP_PAYLOAD = FmpPayloadSystemFirmwarePkcs7
!include Silicon/Hisilicon/Hisilicon.fdf.inc
diff --git a/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc b/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
new file mode 100644
index 0000000..d9f4a00
--- /dev/null
+++ b/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
@@ -0,0 +1,81 @@
+/** @file
+ System Firmware descriptor.
+
+ Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2018, Linaro Limited. All rights reserved.
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiPei.h>
+#include <Guid/EdkiiSystemFmpCapsule.h>
+#include <Protocol/FirmwareManagement.h>
+
+#define PACKAGE_VERSION 0xFFFFFFFF
+#define PACKAGE_VERSION_STRING L"Unknown"
+
+#define CURRENT_FIRMWARE_VERSION 0x00000002
+#define CURRENT_FIRMWARE_VERSION_STRING L"0x00000002"
+#define LOWEST_SUPPORTED_FIRMWARE_VERSION 0x00000001
+
+#define IMAGE_ID SIGNATURE_64('H','W','A', 'R', 'M', '_', 'F', 'd')
+#define IMAGE_ID_STRING L"ARMPlatformFd"
+
+// PcdSystemFmpCapsuleImageTypeIdGuid
+#define IMAGE_TYPE_ID_GUID { 0x44c850f2, 0x85ff, 0x4be5, { 0xbf, 0x34, 0xa5, 0x95, 0x28, 0xdf, 0x22, 0xd3 } }
+
+typedef struct {
+ EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR Descriptor;
+ // real string data
+ CHAR16 ImageIdNameStr[sizeof(IMAGE_ID_STRING) / sizeof(CHAR16)];
+ CHAR16 VersionNameStr[sizeof(CURRENT_FIRMWARE_VERSION_STRING) / sizeof(CHAR16)];
+ CHAR16 PackageVersionNameStr[sizeof(PACKAGE_VERSION_STRING) / sizeof(CHAR16)];
+} IMAGE_DESCRIPTOR;
+
+IMAGE_DESCRIPTOR mImageDescriptor =
+{
+ {
+ EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR_SIGNATURE,
+ sizeof (EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR),
+ sizeof (IMAGE_DESCRIPTOR),
+ PACKAGE_VERSION, // PackageVersion
+ OFFSET_OF (IMAGE_DESCRIPTOR, PackageVersionNameStr), // PackageVersionName
+ 1, // ImageIndex;
+ {0x0}, // Reserved
+ IMAGE_TYPE_ID_GUID, // ImageTypeId;
+ IMAGE_ID, // ImageId;
+ OFFSET_OF (IMAGE_DESCRIPTOR, ImageIdNameStr), // ImageIdName;
+ CURRENT_FIRMWARE_VERSION, // Version;
+ OFFSET_OF (IMAGE_DESCRIPTOR, VersionNameStr), // VersionName;
+ {0x0}, // Reserved2
+ FixedPcdGet32 (PcdFdSize), // Size;
+ IMAGE_ATTRIBUTE_IMAGE_UPDATABLE |
+ IMAGE_ATTRIBUTE_RESET_REQUIRED |
+ IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED |
+ IMAGE_ATTRIBUTE_IN_USE, // AttributesSupported;
+ IMAGE_ATTRIBUTE_IMAGE_UPDATABLE |
+ IMAGE_ATTRIBUTE_RESET_REQUIRED |
+ IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED |
+ IMAGE_ATTRIBUTE_IN_USE, // AttributesSetting;
+ 0x0, // Compatibilities;
+ LOWEST_SUPPORTED_FIRMWARE_VERSION, // LowestSupportedImageVersion;
+ 0x00000000, // LastAttemptVersion;
+ 0, // LastAttemptStatus;
+ {0x0}, // Reserved3
+ 0, // HardwareInstance;
+ },
+ // real string data
+ {IMAGE_ID_STRING},
+ {CURRENT_FIRMWARE_VERSION_STRING},
+ {PACKAGE_VERSION_STRING},
+};
+
+VOID* CONST ReferenceAcpiTable = &mImageDescriptor;
diff --git a/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf b/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
new file mode 100644
index 0000000..c38a809
--- /dev/null
+++ b/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
@@ -0,0 +1,50 @@
+## @file
+# System Firmware descriptor.
+#
+# Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2018, Linaro Limited. All rights reserved.
+# Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SystemFirmwareDescriptor
+ FILE_GUID = 90B2B846-CA6D-4D6E-A8D3-C140A8E110AC
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ ENTRY_POINT = SystemFirmwareDescriptorPeimEntry
+
+[Sources]
+ SystemFirmwareDescriptorPei.c
+ SystemFirmwareDescriptor.aslc
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ SignedCapsulePkg/SignedCapsulePkg.dec
+
+[LibraryClasses]
+ DebugLib
+ PcdLib
+ PeimEntryPoint
+ PeiServicesLib
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdFdSize
+
+[Pcd]
+ gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor
+
+[Depex]
+ TRUE
diff --git a/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c b/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c
new file mode 100644
index 0000000..27c0a71
--- /dev/null
+++ b/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c
@@ -0,0 +1,70 @@
+/** @file
+ System Firmware descriptor producer.
+
+ Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2018, Linaro Limited. All rights reserved.
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiPei.h>
+#include <Guid/EdkiiSystemFmpCapsule.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Protocol/FirmwareManagement.h>
+
+/**
+ Entrypoint for SystemFirmwareDescriptor PEIM.
+
+ @param[in] FileHandle Handle of the file being invoked.
+ @param[in] PeiServices Describes the list of possible PEI Services.
+
+ @retval EFI_SUCCESS PPI successfully installed.
+**/
+EFI_STATUS
+EFIAPI
+SystemFirmwareDescriptorPeimEntry (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+ EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR *Descriptor;
+ UINTN Size;
+ UINTN Index;
+ UINT32 AuthenticationStatus;
+
+ //
+ // Search RAW section.
+ //
+
+ Index = 0;
+ while (TRUE) {
+ Status = PeiServicesFfsFindSectionData3 (EFI_SECTION_RAW, Index, FileHandle, (VOID **)&Descriptor, &AuthenticationStatus);
+ if (EFI_ERROR (Status)) {
+ // Should not happen, must something wrong in FDF.
+ DEBUG ((DEBUG_ERROR, "Not found SystemFirmwareDescriptor in fdf !\n"));
+ return EFI_NOT_FOUND;
+ }
+ if (Descriptor->Signature == EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR_SIGNATURE) {
+ break;
+ }
+ Index++;
+ }
+
+ DEBUG ((DEBUG_INFO, "EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR size - 0x%x\n", Descriptor->Length));
+
+ Size = Descriptor->Length;
+ PcdSetPtrS (PcdEdkiiSystemFirmwareImageDescriptor, &Size, Descriptor);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini b/Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
new file mode 100644
index 0000000..fc834d9
--- /dev/null
+++ b/Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
@@ -0,0 +1,45 @@
+#
+# Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2018, Linaro Limited. All rights reserved.
+# Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Head]
+NumOfUpdate = 3
+NumOfRecovery = 0
+Update0 = SysFvMain
+Update1 = SysCustom
+Update2 = SysNvRam
+
+[SysFvMain]
+FirmwareType = 0 # 0 - SystemFirmware, 1 - NvRam
+AddressType = 0 # 0 - relative address, 1 - absolute address.
+BaseAddress = 0x00000000 # Base address offset on flash
+Length = 0x002D0000 # Length
+ImageOffset = 0x00000000 # Image offset of this SystemFirmware image
+FileGuid = 642e4fcf-2df7-4415-8b70-a03909c57b55 # PcdEdkiiSystemFirmwareFileGuid
+
+[SysCustom]
+FirmwareType = 0 # 0 - SystemFirmware, 1 - NvRam
+AddressType = 0 # 0 - relative address, 1 - absolute address.
+BaseAddress = 0x002F0000 # Base address offset on flash
+Length = 0x00010000 # Length
+ImageOffset = 0x002F0000 # Image offset of this SystemFirmware image
+FileGuid = 642e4fcf-2df7-4415-8b70-a03909c57b55 # PcdEdkiiSystemFirmwareFileGuid
+
+[SysNvRam]
+FirmwareType = 1 # 0 - SystemFirmware, 1 - NvRam
+AddressType = 0 # 0 - relative address, 1 - absolute address.
+BaseAddress = 0x002D0000 # Base address offset on flash
+Length = 0x00020000 # Length
+ImageOffset = 0x002D0000 # Image offset of this SystemFirmware image
+FileGuid = 642e4fcf-2df7-4415-8b70-a03909c57b55 # PcdEdkiiSystemFirmwareFileGuid
diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
index ac7da04..e39acb1 100644
--- a/Platform/Hisilicon/D05/D05.dsc
+++ b/Platform/Hisilicon/D05/D05.dsc
@@ -81,7 +81,6 @@
OemAddressMapLib|Platform/Hisilicon/D05/Library/OemAddressMapD05/OemAddressMapD05.inf
PlatformSysCtrlLib|Silicon/Hisilicon/Hi1616/Library/PlatformSysCtrlLibHi1616/PlatformSysCtrlLibHi1616.inf
- CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
PlatformBdsLib|Silicon/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf
BmcConfigBootLib|Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf
@@ -128,6 +127,11 @@
gHisiTokenSpaceGuid.PcdIsItsSupported|TRUE
gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE
+[PcdsDynamicExDefault.common.DEFAULT]
+ gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor|{0x0}|VOID*|0x100
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSystemFmpCapsuleImageTypeIdGuid|{0x29, 0x3d, 0x4b, 0xd3, 0x85, 0x00, 0xb3, 0x4a, 0x8b, 0xe8, 0x84, 0x18, 0x8c, 0xc5, 0x04, 0x89}
+ gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareFileGuid|{0xcf, 0x4f, 0x2e, 0x64, 0xf7, 0x2d, 0x15, 0x44, 0x8b, 0x70, 0xa0, 0x39, 0x09, 0xc5, 0x7b, 0x55}
+
[PcdsFixedAtBuild.common]
gArmPlatformTokenSpaceGuid.PcdCoreCount|8
@@ -444,6 +448,8 @@
Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf
Silicon/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
+ Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
+
MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
<LibraryClasses>
NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
@@ -560,6 +566,9 @@
Platform/Hisilicon/D05/Drivers/Sas/SasDxeDriver.inf
+ SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf
+ MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf
+
#
# FAT filesystem + GPT/MBR partitioning
#
@@ -625,6 +634,14 @@
MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+
+ SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf {
+ <LibraryClasses>
+ FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibPkcs7/FmpAuthenticationLibPkcs7.inf
+ }
+
+ MdeModulePkg/Application/CapsuleApp/CapsuleApp.inf
+
#
# UEFI application (Shell Embedded Boot Loader)
#
diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf
index 9f8dc2a..b0296e1 100644
--- a/Platform/Hisilicon/D05/D05.fdf
+++ b/Platform/Hisilicon/D05/D05.fdf
@@ -297,6 +297,8 @@ READ_LOCK_STATUS = TRUE
INF Platform/Hisilicon/D05/Drivers/SasPlatform/SasPlatform.inf
INF Platform/Hisilicon/D05/Drivers/Sas/SasDxeDriver.inf
+ INF SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf
+ INF MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf
#
# Build Shell from latest source code instead of prebuilt binary
#
@@ -355,12 +357,80 @@ READ_LOCK_STATUS = TRUE
INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+ INF RuleOverride = FMP_IMAGE_DESC Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
+
FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
SECTION FV_IMAGE = FVMAIN
}
}
+[FV.CapsuleDispatchFv]
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf
+
+[FV.SystemFirmwareUpdateCargo]
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ FILE RAW = 642e4fcf-2df7-4415-8b70-a03909c57b55 { # PcdEdkiiSystemFirmwareFileGuid
+ FD = D05
+ }
+
+ FILE RAW = ce57b167-b0e4-41e8-a897-5f4feb781d40 { # gEdkiiSystemFmpCapsuleDriverFvFileGuid
+ FV = CapsuleDispatchFv
+ }
+
+ FILE RAW = 812136D3-4D3A-433A-9418-29BB9BF78F6E { # gEdkiiSystemFmpCapsuleConfigFileGuid
+ Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
+ }
+
+[FmpPayload.FmpPayloadSystemFirmwarePkcs7]
+IMAGE_HEADER_INIT_VERSION = 0x02
+IMAGE_TYPE_ID = 7978365d-7978-45fd-ad77-b27693cfe85b # PcdSystemFmpCapsuleImageTypeIdGuid
+IMAGE_INDEX = 0x1
+HARDWARE_INSTANCE = 0x0
+MONOTONIC_COUNT = 0x1
+CERTIFICATE_GUID = 4AAFD29D-68DF-49EE-8AA9-347D375665A7 # PKCS7
+
+ FV = SystemFirmwareUpdateCargo
+
+[Capsule.StyxFirmwareUpdateCapsuleFmpPkcs7]
+CAPSULE_GUID = 6dcbd5ed-e82d-4c44-bda1-7194199ad92a # gEfiFmpCapsuleGuid
+CAPSULE_HEADER_SIZE = 0x20
+CAPSULE_HEADER_INIT_VERSION = 0x1
+
+ FMP_PAYLOAD = FmpPayloadSystemFirmwarePkcs7
!include Silicon/Hisilicon/Hisilicon.fdf.inc
diff --git a/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc b/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
new file mode 100644
index 0000000..9f65bb9
--- /dev/null
+++ b/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
@@ -0,0 +1,81 @@
+/** @file
+ System Firmware descriptor.
+
+ Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2018, Linaro Limited. All rights reserved.
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiPei.h>
+#include <Guid/EdkiiSystemFmpCapsule.h>
+#include <Protocol/FirmwareManagement.h>
+
+#define PACKAGE_VERSION 0xFFFFFFFF
+#define PACKAGE_VERSION_STRING L"Unknown"
+
+#define CURRENT_FIRMWARE_VERSION 0x00000002
+#define CURRENT_FIRMWARE_VERSION_STRING L"0x00000002"
+#define LOWEST_SUPPORTED_FIRMWARE_VERSION 0x00000001
+
+#define IMAGE_ID SIGNATURE_64('H','W','A', 'R', 'M', '_', 'F', 'd')
+#define IMAGE_ID_STRING L"ARMPlatformFd"
+
+// PcdSystemFmpCapsuleImageTypeIdGuid
+#define IMAGE_TYPE_ID_GUID { 0x7978365d, 0x7978, 0x45fd, { 0xad, 0x77, 0xb2, 0x76, 0x93, 0xcf, 0xe8, 0x5b } }
+
+typedef struct {
+ EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR Descriptor;
+ // real string data
+ CHAR16 ImageIdNameStr[sizeof(IMAGE_ID_STRING) / sizeof(CHAR16)];
+ CHAR16 VersionNameStr[sizeof(CURRENT_FIRMWARE_VERSION_STRING) / sizeof(CHAR16)];
+ CHAR16 PackageVersionNameStr[sizeof(PACKAGE_VERSION_STRING) / sizeof(CHAR16)];
+} IMAGE_DESCRIPTOR;
+
+IMAGE_DESCRIPTOR mImageDescriptor =
+{
+ {
+ EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR_SIGNATURE,
+ sizeof (EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR),
+ sizeof (IMAGE_DESCRIPTOR),
+ PACKAGE_VERSION, // PackageVersion
+ OFFSET_OF (IMAGE_DESCRIPTOR, PackageVersionNameStr), // PackageVersionName
+ 1, // ImageIndex;
+ {0x0}, // Reserved
+ IMAGE_TYPE_ID_GUID, // ImageTypeId;
+ IMAGE_ID, // ImageId;
+ OFFSET_OF (IMAGE_DESCRIPTOR, ImageIdNameStr), // ImageIdName;
+ CURRENT_FIRMWARE_VERSION, // Version;
+ OFFSET_OF (IMAGE_DESCRIPTOR, VersionNameStr), // VersionName;
+ {0x0}, // Reserved2
+ FixedPcdGet32 (PcdFdSize), // Size;
+ IMAGE_ATTRIBUTE_IMAGE_UPDATABLE |
+ IMAGE_ATTRIBUTE_RESET_REQUIRED |
+ IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED |
+ IMAGE_ATTRIBUTE_IN_USE, // AttributesSupported;
+ IMAGE_ATTRIBUTE_IMAGE_UPDATABLE |
+ IMAGE_ATTRIBUTE_RESET_REQUIRED |
+ IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED |
+ IMAGE_ATTRIBUTE_IN_USE, // AttributesSetting;
+ 0x0, // Compatibilities;
+ LOWEST_SUPPORTED_FIRMWARE_VERSION, // LowestSupportedImageVersion;
+ 0x00000000, // LastAttemptVersion;
+ 0, // LastAttemptStatus;
+ {0x0}, // Reserved3
+ 0, // HardwareInstance;
+ },
+ // real string data
+ {IMAGE_ID_STRING},
+ {CURRENT_FIRMWARE_VERSION_STRING},
+ {PACKAGE_VERSION_STRING},
+};
+
+VOID* CONST ReferenceAcpiTable = &mImageDescriptor;
diff --git a/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf b/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
new file mode 100644
index 0000000..c38a809
--- /dev/null
+++ b/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
@@ -0,0 +1,50 @@
+## @file
+# System Firmware descriptor.
+#
+# Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2018, Linaro Limited. All rights reserved.
+# Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SystemFirmwareDescriptor
+ FILE_GUID = 90B2B846-CA6D-4D6E-A8D3-C140A8E110AC
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ ENTRY_POINT = SystemFirmwareDescriptorPeimEntry
+
+[Sources]
+ SystemFirmwareDescriptorPei.c
+ SystemFirmwareDescriptor.aslc
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ SignedCapsulePkg/SignedCapsulePkg.dec
+
+[LibraryClasses]
+ DebugLib
+ PcdLib
+ PeimEntryPoint
+ PeiServicesLib
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdFdSize
+
+[Pcd]
+ gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor
+
+[Depex]
+ TRUE
diff --git a/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c b/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c
new file mode 100644
index 0000000..27c0a71
--- /dev/null
+++ b/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c
@@ -0,0 +1,70 @@
+/** @file
+ System Firmware descriptor producer.
+
+ Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2018, Linaro Limited. All rights reserved.
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiPei.h>
+#include <Guid/EdkiiSystemFmpCapsule.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Protocol/FirmwareManagement.h>
+
+/**
+ Entrypoint for SystemFirmwareDescriptor PEIM.
+
+ @param[in] FileHandle Handle of the file being invoked.
+ @param[in] PeiServices Describes the list of possible PEI Services.
+
+ @retval EFI_SUCCESS PPI successfully installed.
+**/
+EFI_STATUS
+EFIAPI
+SystemFirmwareDescriptorPeimEntry (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+ EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR *Descriptor;
+ UINTN Size;
+ UINTN Index;
+ UINT32 AuthenticationStatus;
+
+ //
+ // Search RAW section.
+ //
+
+ Index = 0;
+ while (TRUE) {
+ Status = PeiServicesFfsFindSectionData3 (EFI_SECTION_RAW, Index, FileHandle, (VOID **)&Descriptor, &AuthenticationStatus);
+ if (EFI_ERROR (Status)) {
+ // Should not happen, must something wrong in FDF.
+ DEBUG ((DEBUG_ERROR, "Not found SystemFirmwareDescriptor in fdf !\n"));
+ return EFI_NOT_FOUND;
+ }
+ if (Descriptor->Signature == EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR_SIGNATURE) {
+ break;
+ }
+ Index++;
+ }
+
+ DEBUG ((DEBUG_INFO, "EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR size - 0x%x\n", Descriptor->Length));
+
+ Size = Descriptor->Length;
+ PcdSetPtrS (PcdEdkiiSystemFirmwareImageDescriptor, &Size, Descriptor);
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Hisilicon/Hisilicon.dsc.inc b/Silicon/Hisilicon/Hisilicon.dsc.inc
index 308064b..dfa11d1 100644
--- a/Silicon/Hisilicon/Hisilicon.dsc.inc
+++ b/Silicon/Hisilicon/Hisilicon.dsc.inc
@@ -104,6 +104,15 @@
ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibFmp/DxeCapsuleLib.inf
+ OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
+ IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
+ BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
+ FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibPkcs7/FmpAuthenticationLibPkcs7.inf
+ EdkiiSystemCapsuleLib|SignedCapsulePkg/Library/EdkiiSystemCapsuleLib/EdkiiSystemCapsuleLib.inf
+ IniParsingLib|SignedCapsulePkg/Library/IniParsingLib/IniParsingLib.inf
+ PlatformFlashAccessLib|Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf
+
#
# It is not possible to prevent the ARM compiler for generic intrinsic functions.
# This library provides the instrinsic functions generate by a given compiler.
@@ -198,7 +207,7 @@
HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf
- CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibFmp/DxeRuntimeCapsuleLib.inf
SerialPortLib|Silicon/Hisilicon/Library/Dw8250SerialPortRuntimeLib/Dw8250SerialPortRuntimeLib.inf
DebugLib|IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
diff --git a/Silicon/Hisilicon/Hisilicon.fdf.inc b/Silicon/Hisilicon/Hisilicon.fdf.inc
index ee87cd1..986dd75 100644
--- a/Silicon/Hisilicon/Hisilicon.fdf.inc
+++ b/Silicon/Hisilicon/Hisilicon.fdf.inc
@@ -76,6 +76,15 @@
}
}
+[Rule.Common.PEIM.FMP_IMAGE_DESC]
+ FILE PEIM = $(NAMED_GUID) {
+ RAW BIN |.acpi
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 Align=4K $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
[Rule.Common.DXE_CORE]
FILE DXE_CORE = $(NAMED_GUID) {
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
diff --git a/Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c b/Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c
new file mode 100644
index 0000000..62da61c
--- /dev/null
+++ b/Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c
@@ -0,0 +1,123 @@
+/** @file
+ Platform Flash Access library.
+
+ Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2018, Linaro Limited. All rights reserved.
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PlatformFlashAccessLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/HisiSpiFlashProtocol.h>
+
+STATIC EFI_PHYSICAL_ADDRESS mInternalFdAddress;
+STATIC EFI_PHYSICAL_ADDRESS mSFCMEM0BaseAddress;
+
+STATIC HISI_SPI_FLASH_PROTOCOL *mSpiProtocol;
+
+/**
+ Perform flash write opreation.
+
+ @param[in] FirmwareType The type of firmware.
+ @param[in] FlashAddress The address of flash device to be accessed.
+ @param[in] FlashAddressType The type of flash device address.
+ @param[in] Buffer The pointer to the data buffer.
+ @param[in] Length The length of data buffer in bytes.
+
+ @retval EFI_SUCCESS The operation returns successfully.
+ @retval EFI_WRITE_PROTECTED The flash device is read only.
+ @retval EFI_UNSUPPORTED The flash device access is unsupported.
+ @retval EFI_INVALID_PARAMETER The input parameter is not valid.
+**/
+EFI_STATUS
+EFIAPI
+PerformFlashWrite (
+ IN PLATFORM_FIRMWARE_TYPE FirmwareType,
+ IN EFI_PHYSICAL_ADDRESS FlashAddress,
+ IN FLASH_ADDRESS_TYPE FlashAddressType,
+ IN VOID *Buffer,
+ IN UINTN Length
+ )
+{
+ UINT32 RomAddress;
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO,
+ "PerformFlashWrite - 0x%x(%x) - 0x%x\n",
+ (UINTN)FlashAddress,
+ (UINTN)FlashAddressType,
+ Length));
+
+ if (FlashAddressType == FlashAddressTypeAbsoluteAddress) {
+ FlashAddress = FlashAddress - mInternalFdAddress;
+ }
+
+ RomAddress = (UINT32)FlashAddress + (mInternalFdAddress - mSFCMEM0BaseAddress);
+
+ DEBUG ((DEBUG_INFO, "Erase and Write Flash Start\n"));
+
+ Status = mSpiProtocol->EraseWrite (
+ mSpiProtocol,
+ (UINT32) RomAddress,
+ (UINT8 *)Buffer,
+ (UINT32) Length
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Erase and Write Status = %r \n", Status));
+ }
+
+ return Status;
+}
+
+/**
+ Platform Flash Access Lib Constructor.
+
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.
+ @param[in] SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS Constructor returns successfully.
+**/
+EFI_STATUS
+EFIAPI
+PerformFlashAccessLibConstructor (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ mInternalFdAddress = (EFI_PHYSICAL_ADDRESS) PcdGet64 (PcdFdBaseAddress);
+
+ mSFCMEM0BaseAddress = (EFI_PHYSICAL_ADDRESS) PcdGet64 (PcdSFCMEM0BaseAddress);
+
+ DEBUG ((DEBUG_INFO,
+ "PcdFlashAreaBaseAddress - 0x%x, PcdSFCMEM0BaseAddress - 0x%x \n",
+ mInternalFdAddress,
+ mSFCMEM0BaseAddress));
+
+ Status = gBS->LocateProtocol (
+ &gHisiSpiFlashProtocolGuid,
+ NULL,
+ (VOID **)&mSpiProtocol);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR,
+ "LocateProtocol gHisiSpiFlashProtocolGuid Status = %r \n",
+ Status));
+ }
+
+ return Status;
+}
diff --git a/Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf b/Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf
new file mode 100644
index 0000000..ba209c9
--- /dev/null
+++ b/Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf
@@ -0,0 +1,51 @@
+## @file
+# Platform Flash Access library.
+#
+# Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2018, Linaro Limited. All rights reserved.
+# Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = PlatformFlashAccessLibDxe
+ FILE_GUID = c230e06c-c0d8-4935-8c23-9b8f7d33d1c4
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PlatformFlashAccessLib|DXE_DRIVER
+ CONSTRUCTOR = PerformFlashAccessLibConstructor
+
+[Sources]
+ PlatformFlashAccessLibDxe.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ SignedCapsulePkg/SignedCapsulePkg.dec
+ Silicon/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+ BaseMemoryLib
+ DebugLib
+ PcdLib
+ UefiBootServicesTableLib
+
+[Protocols]
+ gHisiSpiFlashProtocolGuid
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdFdBaseAddress
+ gHisiTokenSpaceGuid.PcdSFCMEM0BaseAddress
+
+[Depex]
+ gHisiSpiFlashProtocolGuid
--
1.9.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH edk2-platforms v2 06/15] Hisilicon D03/D05: Open SasPlatform source code
2018-01-26 8:00 [PATCH edk2-platforms v2 00/15] Improve D0x platforms and bug fix Ming Huang
` (4 preceding siblings ...)
2018-01-26 8:00 ` [PATCH edk2-platforms v2 05/15] Hisilicon D03/D05: Add capsule upgrade support Ming Huang
@ 2018-01-26 8:00 ` Ming Huang
2018-01-26 8:00 ` [PATCH edk2-platforms v2 07/15] Hisilicon D03/D05: Open SnpPlatform " Ming Huang
` (9 subsequent siblings)
15 siblings, 0 replies; 30+ messages in thread
From: Ming Huang @ 2018-01-26 8:00 UTC (permalink / raw)
To: leif.lindholm, linaro-uefi, edk2-devel, graeme.gregory
Cc: ard.biesheuvel, guoheyi, wanghuiqiang, huangming23, zhangjinsong2,
mengfanrong, huangdaode, waip23, Heyi Guo
From: Jason Zhang <zhangjinsong2@huawei.com>
This module install a protocol for SasDriverDxe. the protocol
include main information of sas controller, like controller ID,
enable or disable,base address of registers.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jason Zhang <zhangjinsong2@huawei.com>
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
---
Platform/Hisilicon/D03/D03.dsc | 1 +
Platform/Hisilicon/D03/D03.fdf | 2 +-
Platform/Hisilicon/D05/D05.dsc | 1 +
Platform/Hisilicon/D05/D05.fdf | 2 +-
Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.c | 106 ++++++++++++++++++++
Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf | 45 +++++++++
Silicon/Hisilicon/HisiPkg.dec | 2 +
Silicon/Hisilicon/Include/Library/OemDevicePath.h | 52 ++++++++++
Silicon/Hisilicon/Include/Protocol/HisiPlatformSasProtocol.h | 30 ++++++
9 files changed, 239 insertions(+), 2 deletions(-)
diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc
index 82c8bb4..07da597 100644
--- a/Platform/Hisilicon/D03/D03.dsc
+++ b/Platform/Hisilicon/D03/D03.dsc
@@ -468,6 +468,7 @@
Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf
Platform/Hisilicon/D03/Drivers/Sm750Dxe/UefiSmi.inf
+ Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf
Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf
diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf
index 6462a53..919f9d7 100644
--- a/Platform/Hisilicon/D03/D03.fdf
+++ b/Platform/Hisilicon/D03/D03.fdf
@@ -272,7 +272,7 @@ READ_LOCK_STATUS = TRUE
#
INF Platform/Hisilicon/D03/Drivers/Sm750Dxe/UefiSmi.inf
- INF Platform/Hisilicon/D03/Drivers/SasPlatform/SasPlatform.inf
+ INF Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf
INF Platform/Hisilicon/D03/Drivers/Sas/SasDxeDriver.inf
INF SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf
diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
index e39acb1..b279c9e 100644
--- a/Platform/Hisilicon/D05/D05.dsc
+++ b/Platform/Hisilicon/D05/D05.dsc
@@ -621,6 +621,7 @@
Platform/Hisilicon/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf
Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf
Platform/Hisilicon/D05/Drivers/Sm750Dxe/UefiSmi.inf
+ Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf
MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf
diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf
index b0296e1..b105ee2 100644
--- a/Platform/Hisilicon/D05/D05.fdf
+++ b/Platform/Hisilicon/D05/D05.fdf
@@ -294,7 +294,7 @@ READ_LOCK_STATUS = TRUE
#
INF Platform/Hisilicon/D05/Drivers/Sm750Dxe/UefiSmi.inf
INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
- INF Platform/Hisilicon/D05/Drivers/SasPlatform/SasPlatform.inf
+ INF Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf
INF Platform/Hisilicon/D05/Drivers/Sas/SasDxeDriver.inf
INF SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf
diff --git a/Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.c b/Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.c
new file mode 100644
index 0000000..7ae1f5d
--- /dev/null
+++ b/Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.c
@@ -0,0 +1,106 @@
+/** @file
+*
+* Copyright (c) 2017, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2017, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <PiDxe.h>
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiLib.h>
+
+#include <Protocol/HisiPlatformSasProtocol.h>
+
+#define SAS0BusAddr 0xc3000000
+#define SAS1BusAddr 0xa2000000
+#define SAS2BusAddr 0xa3000000
+
+#define SAS0ResetAddr 0xc0000000
+#define SAS1ResetAddr 0xa0000000
+#define SAS2ResetAddr 0xa0000000
+
+typedef struct {
+ UINTN Signature;
+ EFI_HANDLE Handle;
+ HISI_PLATFORM_SAS_PROTOCOL SasPlatformProtocol;
+} SAS_PLATFORM_INSTANCE;
+
+
+STATIC HISI_PLATFORM_SAS_PROTOCOL mSasPlatformProtocol[] = {
+ {
+ 0,
+ FALSE,
+ SAS0BusAddr,
+ SAS0ResetAddr
+ },
+ {
+ 1,
+ TRUE,
+ SAS1BusAddr,
+ SAS1ResetAddr
+ },
+ {
+ 2,
+ FALSE,
+ SAS2BusAddr,
+ SAS2ResetAddr
+ }
+};
+
+EFI_STATUS
+EFIAPI
+SasPlatformInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ UINTN Loop;
+ SAS_PLATFORM_INSTANCE *PrivateData;
+ EFI_STATUS Status;
+
+ for (Loop = 0; Loop < ARRAY_SIZE (mSasPlatformProtocol); Loop++) {
+ if (mSasPlatformProtocol[Loop].Enable != TRUE) {
+ continue;
+ }
+ PrivateData = AllocateZeroPool (sizeof(SAS_PLATFORM_INSTANCE));
+ if (PrivateData == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ PrivateData->SasPlatformProtocol = mSasPlatformProtocol[Loop];
+
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &PrivateData->Handle,
+ &gHisiPlatformSasProtocolGuid,
+ &PrivateData->SasPlatformProtocol,
+ NULL
+ );
+ if (EFI_ERROR (Status)) {
+ FreePool (PrivateData);
+ DEBUG ((DEBUG_ERROR,
+ "[%a]:[%dL] InstallProtocolInterface fail. %r\n",
+ __FUNCTION__,
+ __LINE__,
+ Status));
+ continue;
+ }
+ }
+
+ DEBUG ((DEBUG_INFO, "sas platform init driver Ok!!!\n"));
+ return EFI_SUCCESS;
+}
+
diff --git a/Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf b/Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf
new file mode 100644
index 0000000..fe33623
--- /dev/null
+++ b/Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf
@@ -0,0 +1,45 @@
+#/** @file
+#
+# Copyright (c) 2017, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2017, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010019
+ BASE_NAME = SasPlatform
+ FILE_GUID = 67B9CDE8-257D-44f9-9DE7-39DE866E3539
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = SasPlatformInitialize
+
+[Sources]
+ SasPlatform.c
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ DxeServicesTableLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiLib
+
+[Protocols]
+ gHisiPlatformSasProtocolGuid
+
+[Depex]
+ TRUE
diff --git a/Silicon/Hisilicon/HisiPkg.dec b/Silicon/Hisilicon/HisiPkg.dec
index 889a181..4c9d379 100644
--- a/Silicon/Hisilicon/HisiPkg.dec
+++ b/Silicon/Hisilicon/HisiPkg.dec
@@ -37,6 +37,7 @@
gBmcInfoProtocolGuid = {0x43fa6ffd, 0x35e4, 0x479e, {0xab, 0xec, 0x5, 0x3, 0xf6, 0x48, 0x0, 0xf5}}
gSataEnableFlagProtocolGuid = {0xc2b3c770, 0x8b4a, 0x4796, {0xb2, 0xcf, 0x1d, 0xee, 0x44, 0xd0, 0x32, 0xf3}}
gPlatformSasProtocolGuid = {0x40e9829f, 0x3a2c, 0x479a, {0x9a, 0x93, 0x45, 0x7d, 0x13, 0x50, 0x96, 0x5d}}
+ gHisiPlatformSasProtocolGuid = {0x20e9829f, 0x3a2c, 0x479a, {0x9a, 0x93, 0x45, 0x7d, 0x13, 0x50, 0x96, 0x6d}}
[Guids]
gHisiTokenSpaceGuid = {0xc8bc553e, 0x12bf, 0x11e6, {0x97, 0x4f, 0x87, 0xf7, 0x7c, 0xfd, 0x52, 0x1d}}
@@ -44,6 +45,7 @@
gHisiEfiMemoryMapGuid = {0xf8870015, 0x6994, 0x4b98, {0x95, 0xa2, 0xbd, 0x56, 0xda, 0x91, 0xc0, 0x7f}}
gVersionInfoHobGuid = {0xe13a14c, 0x859c, 0x4f22, {0x82, 0xbd, 0x18, 0xe, 0xe1, 0x42, 0x12, 0xbf}}
gOemBootVariableGuid = {0xb7784577, 0x5aaf, 0x4557, {0xa1, 0x99, 0xd4, 0xa4, 0x2f, 0x45, 0x06, 0xf8}}
+ gEfiHisiSocControllerGuid = {0xee369cc3, 0xa743, 0x5382, {0x75, 0x64, 0x53, 0xe4, 0x31, 0x19, 0x38, 0x35}}
[LibraryClasses]
PlatformSysCtrlLib|Include/Library/PlatformSysCtrlLib.h
diff --git a/Silicon/Hisilicon/Include/Library/OemDevicePath.h b/Silicon/Hisilicon/Include/Library/OemDevicePath.h
new file mode 100644
index 0000000..9d66c21
--- /dev/null
+++ b/Silicon/Hisilicon/Include/Library/OemDevicePath.h
@@ -0,0 +1,52 @@
+/** @file
+*
+* Copyright (c) 2015 - 2017, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015 - 2017, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _OEM_DEVICE_PATH_H_
+#define _OEM_DEVICE_PATH_H_
+#include <Protocol/DevicePath.h>
+
+typedef enum
+{
+ C_NIC = 1,
+ C_SATA = 2,
+ C_SAS = 3,
+ C_USB = 4,
+} CONTROLLER_TYPE;
+
+typedef struct{
+ VENDOR_DEVICE_PATH Vender;
+ UINT8 ControllerType;
+ UINT8 Socket;
+ UINT8 Port;
+} EXT_VENDOR_DEVICE_PATH;
+
+typedef struct{
+ UINT16 BootIndex;
+ UINT16 Port;
+} SATADES;
+
+typedef struct{
+ UINT16 BootIndex;
+ UINT16 ParentPortNumber;
+ UINT16 InterfaceNumber;
+} USBDES;
+
+typedef struct{
+ UINT16 BootIndex;
+ UINT16 Port;
+} PXEDES;
+
+#endif
+
diff --git a/Silicon/Hisilicon/Include/Protocol/HisiPlatformSasProtocol.h b/Silicon/Hisilicon/Include/Protocol/HisiPlatformSasProtocol.h
new file mode 100644
index 0000000..b5edb99
--- /dev/null
+++ b/Silicon/Hisilicon/Include/Protocol/HisiPlatformSasProtocol.h
@@ -0,0 +1,30 @@
+/** @file
+*
+* Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2018, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _HISI_PLATFORM_SAS_PROTOCOL_H_
+#define _HISI_PLATFORM_SAS_PROTOCOL_H_
+
+typedef struct _HISI_PLATFORM_SAS_PROTOCOL HISI_PLATFORM_SAS_PROTOCOL;
+
+struct _HISI_PLATFORM_SAS_PROTOCOL {
+ UINT32 ControllerId;
+ BOOLEAN Enable;
+ UINT64 BaseAddr;
+ UINT64 ResetAddr;
+};
+
+extern EFI_GUID gHisiPlatformSasProtocolGuid;
+
+#endif
--
1.9.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH edk2-platforms v2 07/15] Hisilicon D03/D05: Open SnpPlatform source code
2018-01-26 8:00 [PATCH edk2-platforms v2 00/15] Improve D0x platforms and bug fix Ming Huang
` (5 preceding siblings ...)
2018-01-26 8:00 ` [PATCH edk2-platforms v2 06/15] Hisilicon D03/D05: Open SasPlatform source code Ming Huang
@ 2018-01-26 8:00 ` Ming Huang
2018-01-26 8:00 ` [PATCH edk2-platforms v2 08/15] Hilisicon: Change DmaLib to CoherentDmaLib Ming Huang
` (8 subsequent siblings)
15 siblings, 0 replies; 30+ messages in thread
From: Ming Huang @ 2018-01-26 8:00 UTC (permalink / raw)
To: leif.lindholm, linaro-uefi, edk2-devel, graeme.gregory
Cc: ard.biesheuvel, guoheyi, wanghuiqiang, huangming23, zhangjinsong2,
mengfanrong, huangdaode, waip23, Heyi Guo
From: Jason Zhang <zhangjinsong2@huawei.com>
1. This driver install a protocol for SnpPV600Dxe driver.
The protocol indicate which ethernet port to use and port sequence.
2. Fixed bug:Confusing Ethernet port sequence.
Move the most right Ethernet port (when looking from the front
of the chassis) to the first one in BootManage for PXE boot.
https://bugs.linaro.org/show_bug.cgi?id=2657
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jason Zhang <zhangjinsong2@huawei.com>
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
---
Platform/Hisilicon/D03/D03.dsc | 2 +
Platform/Hisilicon/D03/D03.fdf | 2 +-
Platform/Hisilicon/D05/D05.dsc | 2 +
Platform/Hisilicon/D05/D05.fdf | 2 +-
Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.c | 115 ++++++++++++++++++++
Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf | 46 ++++++++
Silicon/Hisilicon/HisiPkg.dec | 1 +
Silicon/Hisilicon/Include/Protocol/SnpPlatformProtocol.h | 32 ++++++
8 files changed, 200 insertions(+), 2 deletions(-)
diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc
index 07da597..947a8a5 100644
--- a/Platform/Hisilicon/D03/D03.dsc
+++ b/Platform/Hisilicon/D03/D03.dsc
@@ -399,6 +399,8 @@
Platform/Hisilicon/D03/Drivers/Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.inf
+ Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf
+
MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf
index 919f9d7..1c55761 100644
--- a/Platform/Hisilicon/D03/D03.fdf
+++ b/Platform/Hisilicon/D03/D03.fdf
@@ -242,7 +242,7 @@ READ_LOCK_STATUS = TRUE
#Network
#
- INF Platform/Hisilicon/D03/Drivers/Net/SnpPlatform/SnpPlatform.inf
+ INF Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf
INF Platform/Hisilicon/D03/Drivers/Net/SnpPV600Dxe/SnpPV600Dxe.inf
INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
index b279c9e..6e44041 100644
--- a/Platform/Hisilicon/D05/D05.dsc
+++ b/Platform/Hisilicon/D05/D05.dsc
@@ -537,6 +537,8 @@
Platform/Hisilicon/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf
+ Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf
+
MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf
index b105ee2..e829494 100644
--- a/Platform/Hisilicon/D05/D05.fdf
+++ b/Platform/Hisilicon/D05/D05.fdf
@@ -248,7 +248,7 @@ READ_LOCK_STATUS = TRUE
#Network
#
- INF Platform/Hisilicon/D05/Drivers/Net/SnpPlatform/SnpPlatform.inf
+ INF Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf
INF Platform/Hisilicon/D05/Drivers/Net/SnpPV600Dxe/SnpPV600Dxe.inf
INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
diff --git a/Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.c b/Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.c
new file mode 100644
index 0000000..0d6e86e
--- /dev/null
+++ b/Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.c
@@ -0,0 +1,115 @@
+/** @file
+*
+* Copyright (c) 2017, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2017, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <PiDxe.h>
+#include <Uefi.h>
+#include <Guid/EventGroup.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiLib.h>
+
+#include <Protocol/SnpPlatformProtocol.h>
+
+typedef struct {
+ UINTN Signature;
+ EFI_HANDLE Handle;
+ HISI_PLATFORM_SNP_PROTOCOL SnpPlatformProtocol;
+} SNP_PLATFORM_INSTANCE;
+
+STATIC HISI_PLATFORM_SNP_PROTOCOL mSnpPlatformProtocol[] = {
+ {
+ 4,
+ 1
+ },
+ {
+ 5,
+ 1
+ },
+ {
+ 2,
+ 0
+ },
+ {
+ 3,
+ 0
+ },
+ {
+ 0,
+ 1
+ },
+ {
+ 1,
+ 1
+ },
+ {
+ 6,
+ 0
+ },
+ {
+ 7,
+ 0
+ }
+};
+
+
+EFI_STATUS
+EFIAPI
+SnpPlatformInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ UINTN Loop;
+ SNP_PLATFORM_INSTANCE *PrivateData;
+ EFI_STATUS Status;
+
+ for (Loop = 0; Loop < ARRAY_SIZE (mSnpPlatformProtocol); Loop++) {
+ if(mSnpPlatformProtocol[Loop].Enable != 1) {
+ continue;
+ }
+ PrivateData = AllocateZeroPool (sizeof(SNP_PLATFORM_INSTANCE));
+ if (PrivateData == NULL) {
+ DEBUG ((DEBUG_INFO,"SnpPlatformInitialize error 1\n"));
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+
+ PrivateData->SnpPlatformProtocol = mSnpPlatformProtocol[Loop];
+
+ //
+ // Install the snp protocol, device path protocol
+ //
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &PrivateData->Handle,
+ &gHisiSnpPlatformProtocolGuid,
+ &PrivateData->SnpPlatformProtocol,
+ NULL
+ );
+ if (EFI_ERROR (Status)) {
+ FreePool (PrivateData);
+ DEBUG ((DEBUG_ERROR, "InstallProtocolInterface fail. %r\n", Status));
+ continue;
+ }
+ }
+
+ DEBUG ((DEBUG_INFO,"SnpPlatformInitialize succes!\n"));
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf b/Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf
new file mode 100644
index 0000000..3301abf
--- /dev/null
+++ b/Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf
@@ -0,0 +1,46 @@
+#/** @file
+#
+# Copyright (c) 2017, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2017, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010019
+ BASE_NAME = SnpPlatform
+ FILE_GUID = 102D8FC9-20A4-42eb-AC14-1C98BA5B17A8
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = SnpPlatformInitialize
+
+[Sources]
+ SnpPlatform.c
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ DxeServicesTableLib
+ MemoryAllocationLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+
+[Protocols]
+ gHisiSnpPlatformProtocolGuid
+
+[Depex]
+ TRUE
+
diff --git a/Silicon/Hisilicon/HisiPkg.dec b/Silicon/Hisilicon/HisiPkg.dec
index 4c9d379..35bea97 100644
--- a/Silicon/Hisilicon/HisiPkg.dec
+++ b/Silicon/Hisilicon/HisiPkg.dec
@@ -38,6 +38,7 @@
gSataEnableFlagProtocolGuid = {0xc2b3c770, 0x8b4a, 0x4796, {0xb2, 0xcf, 0x1d, 0xee, 0x44, 0xd0, 0x32, 0xf3}}
gPlatformSasProtocolGuid = {0x40e9829f, 0x3a2c, 0x479a, {0x9a, 0x93, 0x45, 0x7d, 0x13, 0x50, 0x96, 0x5d}}
gHisiPlatformSasProtocolGuid = {0x20e9829f, 0x3a2c, 0x479a, {0x9a, 0x93, 0x45, 0x7d, 0x13, 0x50, 0x96, 0x6d}}
+ gHisiSnpPlatformProtocolGuid = {0x81321f27, 0xff58, 0x4a1d, {0x99, 0x97, 0xd, 0xcc, 0xfa, 0x82, 0xf4, 0x6f}}
[Guids]
gHisiTokenSpaceGuid = {0xc8bc553e, 0x12bf, 0x11e6, {0x97, 0x4f, 0x87, 0xf7, 0x7c, 0xfd, 0x52, 0x1d}}
diff --git a/Silicon/Hisilicon/Include/Protocol/SnpPlatformProtocol.h b/Silicon/Hisilicon/Include/Protocol/SnpPlatformProtocol.h
new file mode 100644
index 0000000..0d9f0b4
--- /dev/null
+++ b/Silicon/Hisilicon/Include/Protocol/SnpPlatformProtocol.h
@@ -0,0 +1,32 @@
+/** @file
+*
+* Copyright (c) 2017, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2017, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _SNP_PLATFORM_PROTOCOL_H_
+#define _SNP_PLATFORM_PROTOCOL_H_
+#define HISI_SNP_PLATFORM_PROTOCOL_GUID \
+ { \
+ 0x81321f27, 0xff58, 0x4a1d, 0x99, 0x97, 0xd, 0xcc, 0xfa, 0x82, 0xf4, 0x6f \
+ }
+
+typedef struct _HISI_PLATFORM_SNP_PROTOCOL HISI_PLATFORM_SNP_PROTOCOL;
+
+struct _HISI_PLATFORM_SNP_PROTOCOL {
+ UINT32 ControllerId;
+ UINT32 Enable;
+};
+
+extern EFI_GUID gHisiSnpPlatformProtocolGuid;
+
+#endif
--
1.9.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH edk2-platforms v2 08/15] Hilisicon: Change DmaLib to CoherentDmaLib
2018-01-26 8:00 [PATCH edk2-platforms v2 00/15] Improve D0x platforms and bug fix Ming Huang
` (6 preceding siblings ...)
2018-01-26 8:00 ` [PATCH edk2-platforms v2 07/15] Hisilicon D03/D05: Open SnpPlatform " Ming Huang
@ 2018-01-26 8:00 ` Ming Huang
2018-01-26 8:00 ` [PATCH edk2-platforms v2 09/15] Hisilicon/Smbios: Indicate use of ProcessorFamily2 in type 4 table Ming Huang
` (7 subsequent siblings)
15 siblings, 0 replies; 30+ messages in thread
From: Ming Huang @ 2018-01-26 8:00 UTC (permalink / raw)
To: leif.lindholm, linaro-uefi, edk2-devel, graeme.gregory
Cc: ard.biesheuvel, guoheyi, wanghuiqiang, huangming23, zhangjinsong2,
mengfanrong, huangdaode, waip23, Wang Yue, Heyi Guo
Unify all D0x(include D06 in further) to cache coherent DmaLib.
This can improve boot speed.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wang Yue <wangyue41@huawei.com>
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
---
Platform/Hisilicon/D05/D05.dsc | 2 +-
Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.c | 2 +-
Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.c | 3 +--
3 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
index 6e44041..dfe19b0 100644
--- a/Platform/Hisilicon/D05/D05.dsc
+++ b/Platform/Hisilicon/D05/D05.dsc
@@ -614,7 +614,7 @@
Platform/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf
Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf {
<LibraryClasses>
- DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf
+ DmaLib|EmbeddedPkg/Library/CoherentDmaLib/CoherentDmaLib.inf
NULL|Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf
}
diff --git a/Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.c b/Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.c
index 706eb12..63de50b 100644
--- a/Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.c
+++ b/Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.c
@@ -26,7 +26,7 @@ EhciVirtualPciIoInitialize (
{
return RegisterNonDiscoverableMmioDevice (
NonDiscoverableDeviceTypeEhci,
- NonDiscoverableDeviceDmaTypeNonCoherent,
+ NonDiscoverableDeviceDmaTypeCoherent,
NULL,
NULL,
1,
diff --git a/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.c b/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.c
index 2310ee4..3e272f8 100644
--- a/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.c
+++ b/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.c
@@ -27,7 +27,6 @@ ExitBootServicesEventSmmu (
IN VOID *Context
)
{
- SmmuConfigForOS ();
DEBUG((EFI_D_INFO,"SMMU ExitBootServicesEvent\n"));
}
@@ -43,7 +42,7 @@ IoInitDxeEntry (
(VOID) EfiSerdesInitWrap ();
- SmmuConfigForBios ();
+ SmmuConfigForOS ();
Status = gBS->CreateEvent (
EVT_SIGNAL_EXIT_BOOT_SERVICES,
--
1.9.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH edk2-platforms v2 09/15] Hisilicon/Smbios: Indicate use of ProcessorFamily2 in type 4 table
2018-01-26 8:00 [PATCH edk2-platforms v2 00/15] Improve D0x platforms and bug fix Ming Huang
` (7 preceding siblings ...)
2018-01-26 8:00 ` [PATCH edk2-platforms v2 08/15] Hilisicon: Change DmaLib to CoherentDmaLib Ming Huang
@ 2018-01-26 8:00 ` Ming Huang
2018-01-26 8:00 ` [PATCH edk2-platforms v2 10/15] Hisilicon/PCIe: Disable PCIe ASPM Ming Huang
` (6 subsequent siblings)
15 siblings, 0 replies; 30+ messages in thread
From: Ming Huang @ 2018-01-26 8:00 UTC (permalink / raw)
To: leif.lindholm, linaro-uefi, edk2-devel, graeme.gregory
Cc: ard.biesheuvel, guoheyi, wanghuiqiang, huangming23, zhangjinsong2,
mengfanrong, huangdaode, waip23, Heyi Guo
modify processorFamily of type 4 to ProcessorFamilyIndicatorFamily2,
indicator to obtain the processor family from the Processor Family 2 field.
ProcessorFamily2 is already specified as ProcessorFamilyARM in the existing
table.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
---
Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c b/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c
index 61473e8..c9903ba 100644
--- a/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c
+++ b/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c
@@ -125,7 +125,7 @@ SMBIOS_TABLE_TYPE4 mSmbiosProcessorTable[] = {
},
1, //Socket
CentralProcessor, //ProcessorType
- ProcessorFamilyOther, //ProcessorFamily
+ ProcessorFamilyIndicatorFamily2, //ProcessorFamily
2, //ProcessorManufacture
{ //ProcessorId
{ //Signature
@@ -172,7 +172,7 @@ SMBIOS_TABLE_TYPE4 mSmbiosProcessorTable[] = {
},
1, //Socket
CentralProcessor, //ProcessorType
- ProcessorFamilyOther, //ProcessorFamily
+ ProcessorFamilyIndicatorFamily2, //ProcessorFamily
2, //ProcessorManufacture
{ //ProcessorId
{ //Signature
--
1.9.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH edk2-platforms v2 10/15] Hisilicon/PCIe: Disable PCIe ASPM
2018-01-26 8:00 [PATCH edk2-platforms v2 00/15] Improve D0x platforms and bug fix Ming Huang
` (8 preceding siblings ...)
2018-01-26 8:00 ` [PATCH edk2-platforms v2 09/15] Hisilicon/Smbios: Indicate use of ProcessorFamily2 in type 4 table Ming Huang
@ 2018-01-26 8:00 ` Ming Huang
2018-01-26 8:00 ` [PATCH edk2-platforms v2 11/15] Hisilicon/D05: Replace SP805Watchdog by WatchdogTimer driver Ming Huang
` (5 subsequent siblings)
15 siblings, 0 replies; 30+ messages in thread
From: Ming Huang @ 2018-01-26 8:00 UTC (permalink / raw)
To: leif.lindholm, linaro-uefi, edk2-devel, graeme.gregory
Cc: ard.biesheuvel, guoheyi, wanghuiqiang, huangming23, zhangjinsong2,
mengfanrong, huangdaode, waip23, Yan Zhang, Heyi Guo
From: Yan Zhang <zhangyan81@huawei.com>
In order to replace command line parameter pcie_aspm=off, BIOS needs to
disable Pcie Aspm support during Pcie initilization.
D03 and D05 do not support PCIe ASPM, so we disable it in BIOS.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Signed-off-by: Yan Zhang <zhangyan81@huawei.com>
---
Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 103 ++++++++++++++++++++
Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 2 +
Silicon/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h | 2 +
3 files changed, 107 insertions(+)
diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
index f420c91..c1c3fbb 100644
--- a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
+++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
@@ -1033,6 +1033,106 @@ DisableRcOptionRom (
return;
}
+STATIC
+VOID
+PcieDbiCs2Enable (
+ IN UINT32 HostBridgeNum,
+ IN UINT32 Port,
+ IN BOOLEAN Val
+ )
+{
+ UINT32 RegVal;
+
+ RegRead (
+ PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE_SYS_CTRL21,
+ RegVal
+ );
+ if (Val) {
+ RegVal = RegVal | BIT2;
+ /* BIT2: DBI Chip Select indicator. 0 indicates CS, 1 indicates CS2.*/
+ } else {
+ RegVal = RegVal & (~BIT2);
+ }
+ RegWrite (
+ PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE_SYS_CTRL21,
+ RegVal
+ );
+}
+
+STATIC
+BOOLEAN
+PcieDBIReadOnlyWriteEnable (
+ IN UINT32 HostBridgeNum,
+ IN UINT32 Port
+ )
+{
+ UINT32 Val;
+
+ RegRead (
+ PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_DBI_READ_ONLY_WRITE_ENABLE,
+ Val
+ );
+ if (Val == 0x1) {
+ return TRUE;
+ } else {
+ RegWrite (
+ PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_DBI_READ_ONLY_WRITE_ENABLE,
+ 0x1
+ );
+ /* Delay 10us to make sure the PCIE device have enouph time to response. */
+ MicroSecondDelay(10);
+ RegRead (
+ PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_DBI_READ_ONLY_WRITE_ENABLE,
+ Val
+ );
+ if (Val == 0x1) {
+ return TRUE;
+ }
+ }
+ DEBUG ((DEBUG_ERROR,"PcieDBIReadOnlyWriteEnable Fail!!!\n"));
+ return FALSE;
+}
+
+STATIC
+VOID
+SwitchPcieASPMSupport (
+ IN UINT32 HostBridgeNum,
+ IN UINT32 Port,
+ IN UINT8 Val
+ )
+{
+ PCIE_EP_PCIE_CAP3_U PcieCap3;
+
+ if (Port >= PCIE_MAX_ROOTBRIDGE) {
+ DEBUG ((DEBUG_ERROR, "Port is not valid\n"));
+ return;
+ }
+ if (!PcieDBIReadOnlyWriteEnable (HostBridgeNum, Port)) {
+ DEBUG ((DEBUG_INFO, "PcieDBI ReadOnly Reg do not Enable!!!\n"));
+ return;
+ }
+ PcieDbiCs2Enable (HostBridgeNum, Port, FALSE);
+
+ RegRead (
+ PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_EP_PCIE_CAP3_REG,
+ PcieCap3.UInt32
+ );
+ PcieCap3.Bits.active_state_power_management = Val;
+ RegWrite (
+ PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_EP_PCIE_CAP3_REG,
+ PcieCap3.UInt32
+ );
+ RegRead (
+ PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_EP_PCIE_CAP3_REG,
+ PcieCap3.UInt32
+ );
+ DEBUG ((DEBUG_INFO,
+ "ASPI active state power management: %d\n",
+ PcieCap3.Bits.active_state_power_management));
+
+ PcieDbiCs2Enable (HostBridgeNum, Port, TRUE);
+}
+
EFI_STATUS
EFIAPI
PciePortInit (
@@ -1090,6 +1190,9 @@ PciePortInit (
/* disable link up interrupt */
(VOID)PcieMaskLinkUpInit(soctype, HostBridgeNum, PortIndex);
+ /* disable ASPM */
+ SwitchPcieASPMSupport (HostBridgeNum, PortIndex, PCIE_ASPM_DISABLE);
+
/* Pcie Equalization*/
(VOID)PcieEqualization(soctype ,HostBridgeNum, PortIndex);
diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h
index 9a0f636..e96c53c 100644
--- a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h
+++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h
@@ -77,6 +77,8 @@
#define RegWrite(addr,data) MmioWrite32((addr), (data))
#define RegRead(addr,data) ((data) = MmioRead32 (addr))
+#define PCIE_ASPM_DISABLE 0x0
+#define PCIE_ASPM_ENABLE 0x1
typedef struct tagPcieDebugInfo
{
diff --git a/Silicon/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h b/Silicon/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h
index bf57652..c8b9781 100644
--- a/Silicon/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h
+++ b/Silicon/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h
@@ -135,6 +135,7 @@
#define PCIE_EEP_PORTLOGIC53_REG (0x888)
#define PCIE_EEP_GEN3_CONTRL_REG (0x890)
#define PCIE_EEP_PIPE_LOOPBACK_REG (0x8B8)
+#define PCIE_DBI_READ_ONLY_WRITE_ENABLE (0x8BC)
#define PCIE_EEP_PORTLOGIC54_REG (0x900)
#define PCIE_EEP_PORTLOGIC55_REG (0x904)
#define PCIE_EEP_PORTLOGIC56_REG (0x908)
@@ -12556,6 +12557,7 @@ typedef union tagPortlogic93
#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG (PCIE_SUBCTRL_BASE + 0x1018)
#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG (PCIE_SUBCTRL_BASE + 0x101C)
#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY7_REG (PCIE_SUBCTRL_BASE + 0x1020)
+#define PCIE_SUBCTRL_SC_PCIE_SYS_CTRL21 (PCIE_SUBCTRL_BASE + 0x1024)
#define PCIE_SUBCTRL_SC_DISPATCH_RETRY_CONTROL_REG (PCIE_SUBCTRL_BASE + 0x1030)
#define PCIE_SUBCTRL_SC_DISPATCH_INTMASK_REG (PCIE_SUBCTRL_BASE + 0x1100)
#define PCIE_SUBCTRL_SC_DISPATCH_RAWINT_REG (PCIE_SUBCTRL_BASE + 0x1104)
--
1.9.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH edk2-platforms v2 11/15] Hisilicon/D05: Replace SP805Watchdog by WatchdogTimer driver.
2018-01-26 8:00 [PATCH edk2-platforms v2 00/15] Improve D0x platforms and bug fix Ming Huang
` (9 preceding siblings ...)
2018-01-26 8:00 ` [PATCH edk2-platforms v2 10/15] Hisilicon/PCIe: Disable PCIe ASPM Ming Huang
@ 2018-01-26 8:00 ` Ming Huang
2018-01-26 8:00 ` [PATCH edk2-platforms v2 12/15] Hisilicon/D03: " Ming Huang
` (4 subsequent siblings)
15 siblings, 0 replies; 30+ messages in thread
From: Ming Huang @ 2018-01-26 8:00 UTC (permalink / raw)
To: leif.lindholm, linaro-uefi, edk2-devel, graeme.gregory
Cc: ard.biesheuvel, guoheyi, wanghuiqiang, huangming23, zhangjinsong2,
mengfanrong, huangdaode, waip23, Heyi Guo, GongChengYa
In SCT test,we find SP805 watchdog driver can't reset when timeout
so we use another driver in MdeModulePkg.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Signed-off-by: GongChengYa <gongchengya1@huawei.com>
---
Platform/Hisilicon/D05/D05.dsc | 2 +-
Platform/Hisilicon/D05/D05.fdf | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
index dfe19b0..b2ccd0e 100644
--- a/Platform/Hisilicon/D05/D05.dsc
+++ b/Platform/Hisilicon/D05/D05.dsc
@@ -511,7 +511,7 @@
ArmPkg/Drivers/TimerDxe/TimerDxe.inf
- ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
+ MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf
#
#ACPI
diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf
index e829494..22609bb 100644
--- a/Platform/Hisilicon/D05/D05.fdf
+++ b/Platform/Hisilicon/D05/D05.fdf
@@ -193,7 +193,7 @@ READ_LOCK_STATUS = TRUE
INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
- INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
+ INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
#
# FAT filesystem + GPT/MBR partitioning
--
1.9.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH edk2-platforms v2 12/15] Hisilicon/D03: Replace SP805Watchdog by WatchdogTimer driver.
2018-01-26 8:00 [PATCH edk2-platforms v2 00/15] Improve D0x platforms and bug fix Ming Huang
` (10 preceding siblings ...)
2018-01-26 8:00 ` [PATCH edk2-platforms v2 11/15] Hisilicon/D05: Replace SP805Watchdog by WatchdogTimer driver Ming Huang
@ 2018-01-26 8:00 ` Ming Huang
2018-01-26 8:00 ` [PATCH edk2-platforms v2 13/15] Hisilicon/D05/ACPI: Add ITS PXM Ming Huang
` (3 subsequent siblings)
15 siblings, 0 replies; 30+ messages in thread
From: Ming Huang @ 2018-01-26 8:00 UTC (permalink / raw)
To: leif.lindholm, linaro-uefi, edk2-devel, graeme.gregory
Cc: ard.biesheuvel, guoheyi, wanghuiqiang, huangming23, zhangjinsong2,
mengfanrong, huangdaode, waip23, Heyi Guo, GongChengYa
In SCT test,we find SP805 watchdog driver can't reset when timeout
so we use another driver in MdeModulePkg.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Signed-off-by: GongChengYa <gongchengya1@huawei.com>
---
Platform/Hisilicon/D03/D03.dsc | 2 +-
Platform/Hisilicon/D03/D03.fdf | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc
index 947a8a5..37bec9e 100644
--- a/Platform/Hisilicon/D03/D03.dsc
+++ b/Platform/Hisilicon/D03/D03.dsc
@@ -374,7 +374,7 @@
ArmPkg/Drivers/TimerDxe/TimerDxe.inf
- ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
+ MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf
#
#ACPI
diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf
index 1c55761..e6a4820 100644
--- a/Platform/Hisilicon/D03/D03.fdf
+++ b/Platform/Hisilicon/D03/D03.fdf
@@ -189,7 +189,7 @@ READ_LOCK_STATUS = TRUE
INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
- INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
+ INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
#
# FAT filesystem + GPT/MBR partitioning
--
1.9.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH edk2-platforms v2 13/15] Hisilicon/D05/ACPI: Add ITS PXM
2018-01-26 8:00 [PATCH edk2-platforms v2 00/15] Improve D0x platforms and bug fix Ming Huang
` (11 preceding siblings ...)
2018-01-26 8:00 ` [PATCH edk2-platforms v2 12/15] Hisilicon/D03: " Ming Huang
@ 2018-01-26 8:00 ` Ming Huang
2018-01-30 14:30 ` graeme.gregory
2018-01-26 8:00 ` [PATCH edk2-platforms v2 14/15] Hisilicon/D05/ACPI: Add Pcie, HNS and SAS PXM Ming Huang
` (2 subsequent siblings)
15 siblings, 1 reply; 30+ messages in thread
From: Ming Huang @ 2018-01-26 8:00 UTC (permalink / raw)
To: leif.lindholm, linaro-uefi, edk2-devel, graeme.gregory
Cc: ard.biesheuvel, guoheyi, wanghuiqiang, huangming23, zhangjinsong2,
mengfanrong, huangdaode, waip23, Heyi Guo
Add ITS affinity structure in SRAT.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
---
Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc | 10 ++++++++++
Silicon/Hisilicon/Include/Library/AcpiNextLib.h | 10 +++++++++-
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc
index b448a29..8ea0c4b 100644
--- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc
+++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc
@@ -121,6 +121,16 @@ EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE Srat = {
EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003E,0x00000001,0x00000000), //GICC Affinity Processor 62
EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003F,0x00000001,0x00000000) //GICC Affinity Processor 63
},
+ {
+ EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x00000000, 0x00000000),
+ EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x00000001, 0x00000001),
+ EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x00000000, 0x00000002),
+ EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x00000001, 0x00000003),
+ EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x00000002, 0x00000004),
+ EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x00000003, 0x00000005),
+ EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x00000002, 0x00000006),
+ EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x00000003, 0x00000007)
+ },
};
//
diff --git a/Silicon/Hisilicon/Include/Library/AcpiNextLib.h b/Silicon/Hisilicon/Include/Library/AcpiNextLib.h
index 60f9925..fd05a3b 100644
--- a/Silicon/Hisilicon/Include/Library/AcpiNextLib.h
+++ b/Silicon/Hisilicon/Include/Library/AcpiNextLib.h
@@ -39,6 +39,13 @@
ACPIProcessorUID, Flags, ClockDomain \
}
+#define EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT( \
+ ProximityDomain, ItsId) \
+ { \
+ 4, sizeof (EFI_ACPI_6_2_GIC_ITS_AFFINITY_STRUCTURE), ProximityDomain, \
+ {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, ItsId \
+ }
+
#define EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT( \
ProximityDomain, AddressBaseLow, AddressBaseHigh, LengthLow, LengthHigh, Flags) \
{ \
@@ -70,12 +77,13 @@
//
#define EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT 64
#define EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT 10
-
+#define EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_COUNT 8
typedef struct {
EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER Header;
EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE Memory[EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT];
EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE Gicc[EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT];
+ EFI_ACPI_6_2_GIC_ITS_AFFINITY_STRUCTURE Its[EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_COUNT];
} EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE;
#pragma pack()
--
1.9.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH edk2-platforms v2 14/15] Hisilicon/D05/ACPI: Add Pcie, HNS and SAS PXM
2018-01-26 8:00 [PATCH edk2-platforms v2 00/15] Improve D0x platforms and bug fix Ming Huang
` (12 preceding siblings ...)
2018-01-26 8:00 ` [PATCH edk2-platforms v2 13/15] Hisilicon/D05/ACPI: Add ITS PXM Ming Huang
@ 2018-01-26 8:00 ` Ming Huang
2018-01-30 14:31 ` graeme.gregory
2018-01-26 8:00 ` [PATCH edk2-platforms v2 15/15] Hisilicon D03/D05: Update firmware version to 18.02 Ming Huang
2018-01-29 17:33 ` [PATCH edk2-platforms v2 00/15] Improve D0x platforms and bug fix Leif Lindholm
15 siblings, 1 reply; 30+ messages in thread
From: Ming Huang @ 2018-01-26 8:00 UTC (permalink / raw)
To: leif.lindholm, linaro-uefi, edk2-devel, graeme.gregory
Cc: ard.biesheuvel, guoheyi, wanghuiqiang, huangming23, zhangjinsong2,
mengfanrong, huangdaode, waip23, Heyi Guo
Add PXM method for Pcie device, HNS device and SAS device.
Add STA method for HNS.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: hensonwang <wanghuiqiang@huawei.com>
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
---
Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl | 9 ++++++
Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 34 ++++++++++++++++++--
Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl | 19 +++++++++--
3 files changed, 57 insertions(+), 5 deletions(-)
diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl
index 11c28ba..7aa04af 100644
--- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl
+++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl
@@ -233,6 +233,15 @@ Scope(_SB)
}
})
+ Method (_PXM, 0, NotSerialized)
+ {
+ Return(0x00)
+ }
+ Method (_STA, 0, NotSerialized)
+ {
+ Return(0x0F)
+ }
+
//reset XGE port
//Arg0 : XGE port index in dsaf
//Arg1 : 0 reset, 1 cancle reset
diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl
index 55c7f50..122e4f0 100644
--- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl
+++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl
@@ -141,7 +141,10 @@ Scope(_SB)
{
Return (0xf)
}
-
+ Method (_PXM, 0, NotSerialized)
+ {
+ Return(0x00)
+ }
} // Device(PCI2)
Device (RES2)
@@ -240,7 +243,10 @@ Scope(_SB)
{
Return (RBYV())
}
-
+ Method (_PXM, 0, NotSerialized)
+ {
+ Return(0x01)
+ }
} // Device(PCI4)
Device (RES4)
{
@@ -338,6 +344,10 @@ Scope(_SB)
{
Return (RBYV())
}
+ Method (_PXM, 0, NotSerialized)
+ {
+ Return(0x01)
+ }
} // Device(PCI5)
Device (RES5)
{
@@ -435,6 +445,10 @@ Scope(_SB)
{
Return (RBYV())
}
+ Method (_PXM, 0, NotSerialized)
+ {
+ Return(0x01)
+ }
} // Device(PCI6)
Device (RES6)
{
@@ -531,6 +545,10 @@ Scope(_SB)
{
Return (RBYV())
}
+ Method (_PXM, 0, NotSerialized)
+ {
+ Return(0x01)
+ }
} // Device(PCI7)
Device (RES7)
{
@@ -690,6 +708,10 @@ Scope(_SB)
{
Return (0xf)
}
+ Method (_PXM, 0, NotSerialized)
+ {
+ Return(0x02)
+ }
} // Device(PCIa)
Device (RESa)
{
@@ -810,6 +832,10 @@ Scope(_SB)
{
Return (RBYV())
}
+ Method (_PXM, 0, NotSerialized)
+ {
+ Return(0x03)
+ }
} // Device(PCIc)
Device (RESc)
@@ -907,6 +933,10 @@ Scope(_SB)
{
Return (RBYV())
}
+ Method (_PXM, 0, NotSerialized)
+ {
+ Return(0x03)
+ }
} // Device(PCId)
Device (RESd)
{
diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl
index 6455130..d5b7e2f 100644
--- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl
+++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl
@@ -88,7 +88,10 @@ Scope(_SB)
Store(0x7ffff, CLK)
Sleep(1)
}
-
+ Method (_PXM, 0, NotSerialized)
+ {
+ Return(0x00)
+ }
Method (_STA, 0, NotSerialized)
{
Return (0x0)
@@ -169,8 +172,15 @@ Scope(_SB)
Store(0x7ffff, CLK)
Sleep(1)
}
+ Method (_PXM, 0, NotSerialized)
+ {
+ Return(0x00)
+ }
+ Method (_STA, 0, NotSerialized)
+ {
+ Return(0x0F)
+ }
}
-
Device(SAS2) {
Name(_HID, "HISI0162")
Name(_CCA, 1)
@@ -244,7 +254,10 @@ Scope(_SB)
Store(0x7ffff, CLK)
Sleep(1)
}
-
+ Method (_PXM, 0, NotSerialized)
+ {
+ Return(0x00)
+ }
Method (_STA, 0, NotSerialized)
{
Return (0x0)
--
1.9.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH edk2-platforms v2 15/15] Hisilicon D03/D05: Update firmware version to 18.02
2018-01-26 8:00 [PATCH edk2-platforms v2 00/15] Improve D0x platforms and bug fix Ming Huang
` (13 preceding siblings ...)
2018-01-26 8:00 ` [PATCH edk2-platforms v2 14/15] Hisilicon/D05/ACPI: Add Pcie, HNS and SAS PXM Ming Huang
@ 2018-01-26 8:00 ` Ming Huang
2018-01-29 17:33 ` [PATCH edk2-platforms v2 00/15] Improve D0x platforms and bug fix Leif Lindholm
15 siblings, 0 replies; 30+ messages in thread
From: Ming Huang @ 2018-01-26 8:00 UTC (permalink / raw)
To: leif.lindholm, linaro-uefi, edk2-devel, graeme.gregory
Cc: ard.biesheuvel, guoheyi, wanghuiqiang, huangming23, zhangjinsong2,
mengfanrong, huangdaode, waip23, Heyi Guo
Replace the old string with short one. The old one is
too long that can not be show integrallty in Setup nemu.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
---
Platform/Hisilicon/D03/D03.dsc | 2 +-
Platform/Hisilicon/D05/D05.dsc | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc
index 37bec9e..c496306 100644
--- a/Platform/Hisilicon/D03/D03.dsc
+++ b/Platform/Hisilicon/D03/D03.dsc
@@ -168,7 +168,7 @@
!ifdef $(FIRMWARE_VER)
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)"
!else
- gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Development build base on Hisilicon D03 UEFI 17.10 Release"
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Development build 18.02 for Hisilicon D03"
!endif
gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18"
diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
index b2ccd0e..0792b08 100644
--- a/Platform/Hisilicon/D05/D05.dsc
+++ b/Platform/Hisilicon/D05/D05.dsc
@@ -187,7 +187,7 @@
!ifdef $(FIRMWARE_VER)
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)"
!else
- gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Development build base on Hisilicon D05 UEFI 17.10 Release"
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Development build 18.02 for Hisilicon D05"
!endif
gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18"
--
1.9.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* Re: [PATCH edk2-platforms v2 00/15] Improve D0x platforms and bug fix
2018-01-26 8:00 [PATCH edk2-platforms v2 00/15] Improve D0x platforms and bug fix Ming Huang
` (14 preceding siblings ...)
2018-01-26 8:00 ` [PATCH edk2-platforms v2 15/15] Hisilicon D03/D05: Update firmware version to 18.02 Ming Huang
@ 2018-01-29 17:33 ` Leif Lindholm
2018-02-03 7:50 ` Huangming (Mark)
15 siblings, 1 reply; 30+ messages in thread
From: Leif Lindholm @ 2018-01-29 17:33 UTC (permalink / raw)
To: Ming Huang
Cc: linaro-uefi, edk2-devel, graeme.gregory, ard.biesheuvel, guoheyi,
wanghuiqiang, huangming23, zhangjinsong2, mengfanrong, huangdaode,
waip23, Jeremy Linton
So, I'm mostly happy with this set, but:
Sender (and hence Author for all patches that do not have a second
From: statement after Subject: ) for all patches here is
Ming Huang <heyi.guo@linaro.org>
Can you please address this, either by actually sending from Ming Huang, or
by adding a From:.
You can add my
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
to 3-4, 6-12 and 15.
I have a few comments on 5/15, and then I need some input from others
on the ACPI bits - especially from Jeremy, who should ideally have
been cc:d on at least the PPTT patch given his comments on v1.
/
Leif
On Fri, Jan 26, 2018 at 04:00:35PM +0800, Ming Huang wrote:
> The major features of this patchset include
> adding PPTT support,
> switching to Generic BDS driver,
> adding capsule upgrade support,
> open-source version for SnpPlatform and SasPlatform
> changing DmaLib to CoherentDmaLib(this one is omissive in v1).
>
> Code can also be found in github: https://github.com/hisilicon/OpenPlatformPkg.git
> branch: rp-1802-platforms-v2
>
>
> Jason Zhang (3):
> Hisilicon D03/D05: Add capsule upgrade support
> Hisilicon D03/D05: Open SasPlatform source code
> Hisilicon D03/D05: Open SnpPlatform source code
>
> Ming Huang (11):
> Hisilicon/D05: Move Madt definition to head file
> Hisilicon/D05: Add PPTT support
> Hisilicon/D0x/BDS: Switch to Generic BDS driver
> Hisilicon/D0x: Break BMC SetBoot option out into separate library
> Hilisicon: Change DmaLib to CoherentDmaLib
> Hisilicon/Smbios: Indicate use of ProcessorFamily2 in type 4 table
> Hisilicon/D05: Replace SP805Watchdog by WatchdogTimer driver.
> Hisilicon/D03: Replace SP805Watchdog by WatchdogTimer driver.
> Hisilicon/D05/ACPI: Add ITS PXM
> Hisilicon/D05/ACPI: Add Pcie, HNS and SAS PXM
> Hisilicon D03/D05: Update firmware version to 18.02
>
> Yan Zhang (1):
> Hisilicon/PCIe: Disable PCIe ASPM
>
> Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini | 45 ++
> Platform/Hisilicon/D03/D03.dsc | 42 +-
> Platform/Hisilicon/D03/D03.fdf | 79 ++-
> Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc | 81 +++
> Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 50 ++
> Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c | 70 +++
> Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini | 45 ++
> Platform/Hisilicon/D05/D05.dsc | 47 +-
> Platform/Hisilicon/D05/D05.fdf | 80 ++-
> Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc | 81 +++
> Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 50 ++
> Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c | 70 +++
> Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.c | 106 ++++
> Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf | 45 ++
> Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c | 4 +-
> Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.c | 115 ++++
> Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf | 46 ++
> Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.c | 2 +-
> Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.c | 3 +-
> Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 103 ++++
> Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 2 +
> Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc | 10 +
> Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl | 9 +
> Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 34 +-
> Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl | 19 +-
> Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h | 30 +-
> Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc | 23 +-
> Silicon/Hisilicon/Hi1616/Pptt/Pptt.c | 540 ++++++++++++++++
> Silicon/Hisilicon/Hi1616/Pptt/Pptt.h | 88 +++
> Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf | 48 ++
> Silicon/Hisilicon/HisiPkg.dec | 6 +
> Silicon/Hisilicon/Hisilicon.dsc.inc | 12 +-
> Silicon/Hisilicon/Hisilicon.fdf.inc | 9 +
> Silicon/Hisilicon/Include/Library/AcpiNextLib.h | 10 +-
> Silicon/Hisilicon/Include/Library/BmcConfigBootLib.h | 31 +
> Silicon/Hisilicon/Include/Library/OemDevicePath.h | 52 ++
> Silicon/Hisilicon/Include/Protocol/HisiPlatformSasProtocol.h | 30 +
> Silicon/Hisilicon/Include/Protocol/SnpPlatformProtocol.h | 32 +
> Silicon/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h | 2 +
> Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.c | 466 ++++++++++++++
> Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf | 51 ++
> Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c | 643 ++++++++++++++++++++
> Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.h | 31 +
> Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf | 74 +++
> Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c | 123 ++++
> Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf | 51 ++
> 46 files changed, 3536 insertions(+), 54 deletions(-)
> create mode 100644 Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
> create mode 100644 Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
> create mode 100644 Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
> create mode 100644 Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c
> create mode 100644 Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
> create mode 100644 Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
> create mode 100644 Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
> create mode 100644 Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c
> create mode 100644 Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.c
> create mode 100644 Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf
> create mode 100644 Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.c
> create mode 100644 Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf
> create mode 100644 Silicon/Hisilicon/Hi1616/Pptt/Pptt.c
> create mode 100644 Silicon/Hisilicon/Hi1616/Pptt/Pptt.h
> create mode 100644 Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf
> create mode 100644 Silicon/Hisilicon/Include/Library/BmcConfigBootLib.h
> create mode 100644 Silicon/Hisilicon/Include/Library/OemDevicePath.h
> create mode 100644 Silicon/Hisilicon/Include/Protocol/HisiPlatformSasProtocol.h
> create mode 100644 Silicon/Hisilicon/Include/Protocol/SnpPlatformProtocol.h
> create mode 100644 Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.c
> create mode 100644 Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf
> create mode 100644 Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c
> create mode 100644 Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.h
> create mode 100644 Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
> create mode 100644 Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c
> create mode 100644 Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf
>
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH edk2-platforms v2 05/15] Hisilicon D03/D05: Add capsule upgrade support
2018-01-26 8:00 ` [PATCH edk2-platforms v2 05/15] Hisilicon D03/D05: Add capsule upgrade support Ming Huang
@ 2018-01-29 19:58 ` Leif Lindholm
2018-01-30 12:48 ` Huangming (Mark)
2018-01-30 12:47 ` Ard Biesheuvel
1 sibling, 1 reply; 30+ messages in thread
From: Leif Lindholm @ 2018-01-29 19:58 UTC (permalink / raw)
To: Ming Huang
Cc: linaro-uefi, edk2-devel, graeme.gregory, ard.biesheuvel, guoheyi,
wanghuiqiang, huangming23, zhangjinsong2, mengfanrong, huangdaode,
waip23
A few style comments below.
On Fri, Jan 26, 2018 at 04:00:40PM +0800, Ming Huang wrote:
> From: Jason Zhang <zhangjinsong2@huawei.com>
>
> This module support updating the boot CPU firmware only.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Jason Zhang <zhangjinsong2@huawei.com>
> Signed-off-by: Ming Huang <huangming23@huawei.com>
> Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
> ---
> Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini | 45 +++++++
> Platform/Hisilicon/D03/D03.dsc | 17 ++-
> Platform/Hisilicon/D03/D03.fdf | 70 +++++++++++
> Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc | 81 +++++++++++++
> Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 50 ++++++++
> Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c | 70 +++++++++++
> Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini | 45 +++++++
> Platform/Hisilicon/D05/D05.dsc | 19 ++-
> Platform/Hisilicon/D05/D05.fdf | 70 +++++++++++
> Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc | 81 +++++++++++++
> Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 50 ++++++++
> Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c | 70 +++++++++++
> Silicon/Hisilicon/Hisilicon.dsc.inc | 11 +-
> Silicon/Hisilicon/Hisilicon.fdf.inc | 9 ++
> Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c | 123 ++++++++++++++++++++
> Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf | 51 ++++++++
> 16 files changed, 859 insertions(+), 3 deletions(-)
>
> diff --git a/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc b/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
> new file mode 100644
> index 0000000..d9f4a00
> --- /dev/null
> +++ b/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
> @@ -0,0 +1,81 @@
> +/** @file
> + System Firmware descriptor.
> +
> + Copyright (c) 2018, Hisilicon Limited. All rights reserved.
> + Copyright (c) 2018, Linaro Limited. All rights reserved.
> + Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <PiPei.h>
> +#include <Guid/EdkiiSystemFmpCapsule.h>
> +#include <Protocol/FirmwareManagement.h>
> +
> +#define PACKAGE_VERSION 0xFFFFFFFF
> +#define PACKAGE_VERSION_STRING L"Unknown"
> +
> +#define CURRENT_FIRMWARE_VERSION 0x00000002
> +#define CURRENT_FIRMWARE_VERSION_STRING L"0x00000002"
> +#define LOWEST_SUPPORTED_FIRMWARE_VERSION 0x00000001
> +
> +#define IMAGE_ID SIGNATURE_64('H','W','A', 'R', 'M', '_', 'F', 'd')
> +#define IMAGE_ID_STRING L"ARMPlatformFd"
> +
> +// PcdSystemFmpCapsuleImageTypeIdGuid
> +#define IMAGE_TYPE_ID_GUID { 0x44c850f2, 0x85ff, 0x4be5, { 0xbf, 0x34, 0xa5, 0x95, 0x28, 0xdf, 0x22, 0xd3 } }
> +
> +typedef struct {
> + EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR Descriptor;
> + // real string data
> + CHAR16 ImageIdNameStr[sizeof(IMAGE_ID_STRING) / sizeof(CHAR16)];
> + CHAR16 VersionNameStr[sizeof(CURRENT_FIRMWARE_VERSION_STRING) / sizeof(CHAR16)];
> + CHAR16 PackageVersionNameStr[sizeof(PACKAGE_VERSION_STRING) / sizeof(CHAR16)];
Use ARRAY_SIZE for the 3 above?
> +} IMAGE_DESCRIPTOR;
> +
> +IMAGE_DESCRIPTOR mImageDescriptor =
> +{
> + {
> + EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR_SIGNATURE,
> + sizeof (EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR),
> + sizeof (IMAGE_DESCRIPTOR),
> + PACKAGE_VERSION, // PackageVersion
> + OFFSET_OF (IMAGE_DESCRIPTOR, PackageVersionNameStr), // PackageVersionName
> + 1, // ImageIndex;
> + {0x0}, // Reserved
> + IMAGE_TYPE_ID_GUID, // ImageTypeId;
> + IMAGE_ID, // ImageId;
> + OFFSET_OF (IMAGE_DESCRIPTOR, ImageIdNameStr), // ImageIdName;
> + CURRENT_FIRMWARE_VERSION, // Version;
> + OFFSET_OF (IMAGE_DESCRIPTOR, VersionNameStr), // VersionName;
> + {0x0}, // Reserved2
> + FixedPcdGet32 (PcdFdSize), // Size;
> + IMAGE_ATTRIBUTE_IMAGE_UPDATABLE |
> + IMAGE_ATTRIBUTE_RESET_REQUIRED |
> + IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED |
> + IMAGE_ATTRIBUTE_IN_USE, // AttributesSupported;
> + IMAGE_ATTRIBUTE_IMAGE_UPDATABLE |
> + IMAGE_ATTRIBUTE_RESET_REQUIRED |
> + IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED |
> + IMAGE_ATTRIBUTE_IN_USE, // AttributesSetting;
> + 0x0, // Compatibilities;
> + LOWEST_SUPPORTED_FIRMWARE_VERSION, // LowestSupportedImageVersion;
> + 0x00000000, // LastAttemptVersion;
> + 0, // LastAttemptStatus;
> + {0x0}, // Reserved3
> + 0, // HardwareInstance;
> + },
> + // real string data
> + {IMAGE_ID_STRING},
> + {CURRENT_FIRMWARE_VERSION_STRING},
> + {PACKAGE_VERSION_STRING},
> +};
> +
> +VOID* CONST ReferenceAcpiTable = &mImageDescriptor;
> diff --git a/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf b/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
> new file mode 100644
> index 0000000..c38a809
> --- /dev/null
> +++ b/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
> @@ -0,0 +1,50 @@
> +## @file
> +# System Firmware descriptor.
> +#
> +# Copyright (c) 2018, Hisilicon Limited. All rights reserved.
> +# Copyright (c) 2018, Linaro Limited. All rights reserved.
> +# Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010005
0x0001001A
> + BASE_NAME = SystemFirmwareDescriptor
> + FILE_GUID = 90B2B846-CA6D-4D6E-A8D3-C140A8E110AC
> + MODULE_TYPE = PEIM
> + VERSION_STRING = 1.0
> + ENTRY_POINT = SystemFirmwareDescriptorPeimEntry
> +
> +[Sources]
> + SystemFirmwareDescriptorPei.c
> + SystemFirmwareDescriptor.aslc
> +
> +[Packages]
> + ArmPkg/ArmPkg.dec
> + ArmPlatformPkg/ArmPlatformPkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + MdePkg/MdePkg.dec
> + SignedCapsulePkg/SignedCapsulePkg.dec
> +
> +[LibraryClasses]
> + DebugLib
> + PcdLib
> + PeimEntryPoint
> + PeiServicesLib
> +
> +[FixedPcd]
> + gArmTokenSpaceGuid.PcdFdSize
> +
> +[Pcd]
> + gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor
> +
> +[Depex]
> + TRUE
> diff --git a/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc b/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
> new file mode 100644
> index 0000000..9f65bb9
> --- /dev/null
> +++ b/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
> @@ -0,0 +1,81 @@
> +/** @file
> + System Firmware descriptor.
> +
> + Copyright (c) 2018, Hisilicon Limited. All rights reserved.
> + Copyright (c) 2018, Linaro Limited. All rights reserved.
> + Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <PiPei.h>
> +#include <Guid/EdkiiSystemFmpCapsule.h>
> +#include <Protocol/FirmwareManagement.h>
> +
> +#define PACKAGE_VERSION 0xFFFFFFFF
> +#define PACKAGE_VERSION_STRING L"Unknown"
> +
> +#define CURRENT_FIRMWARE_VERSION 0x00000002
> +#define CURRENT_FIRMWARE_VERSION_STRING L"0x00000002"
> +#define LOWEST_SUPPORTED_FIRMWARE_VERSION 0x00000001
> +
> +#define IMAGE_ID SIGNATURE_64('H','W','A', 'R', 'M', '_', 'F', 'd')
> +#define IMAGE_ID_STRING L"ARMPlatformFd"
> +
> +// PcdSystemFmpCapsuleImageTypeIdGuid
> +#define IMAGE_TYPE_ID_GUID { 0x7978365d, 0x7978, 0x45fd, { 0xad, 0x77, 0xb2, 0x76, 0x93, 0xcf, 0xe8, 0x5b } }
> +
> +typedef struct {
> + EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR Descriptor;
> + // real string data
> + CHAR16 ImageIdNameStr[sizeof(IMAGE_ID_STRING) / sizeof(CHAR16)];
> + CHAR16 VersionNameStr[sizeof(CURRENT_FIRMWARE_VERSION_STRING) / sizeof(CHAR16)];
> + CHAR16 PackageVersionNameStr[sizeof(PACKAGE_VERSION_STRING) / sizeof(CHAR16)];
3x ARRAY_SIZE?
> +} IMAGE_DESCRIPTOR;
> +
> +IMAGE_DESCRIPTOR mImageDescriptor =
> +{
> + {
> + EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR_SIGNATURE,
> + sizeof (EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR),
> + sizeof (IMAGE_DESCRIPTOR),
> + PACKAGE_VERSION, // PackageVersion
> + OFFSET_OF (IMAGE_DESCRIPTOR, PackageVersionNameStr), // PackageVersionName
> + 1, // ImageIndex;
> + {0x0}, // Reserved
> + IMAGE_TYPE_ID_GUID, // ImageTypeId;
> + IMAGE_ID, // ImageId;
> + OFFSET_OF (IMAGE_DESCRIPTOR, ImageIdNameStr), // ImageIdName;
> + CURRENT_FIRMWARE_VERSION, // Version;
> + OFFSET_OF (IMAGE_DESCRIPTOR, VersionNameStr), // VersionName;
> + {0x0}, // Reserved2
> + FixedPcdGet32 (PcdFdSize), // Size;
> + IMAGE_ATTRIBUTE_IMAGE_UPDATABLE |
> + IMAGE_ATTRIBUTE_RESET_REQUIRED |
> + IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED |
> + IMAGE_ATTRIBUTE_IN_USE, // AttributesSupported;
> + IMAGE_ATTRIBUTE_IMAGE_UPDATABLE |
> + IMAGE_ATTRIBUTE_RESET_REQUIRED |
> + IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED |
> + IMAGE_ATTRIBUTE_IN_USE, // AttributesSetting;
> + 0x0, // Compatibilities;
> + LOWEST_SUPPORTED_FIRMWARE_VERSION, // LowestSupportedImageVersion;
> + 0x00000000, // LastAttemptVersion;
> + 0, // LastAttemptStatus;
> + {0x0}, // Reserved3
> + 0, // HardwareInstance;
> + },
> + // real string data
> + {IMAGE_ID_STRING},
> + {CURRENT_FIRMWARE_VERSION_STRING},
> + {PACKAGE_VERSION_STRING},
> +};
> +
> +VOID* CONST ReferenceAcpiTable = &mImageDescriptor;
> diff --git a/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf b/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
> new file mode 100644
> index 0000000..c38a809
> --- /dev/null
> +++ b/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
> @@ -0,0 +1,50 @@
> +## @file
> +# System Firmware descriptor.
> +#
> +# Copyright (c) 2018, Hisilicon Limited. All rights reserved.
> +# Copyright (c) 2018, Linaro Limited. All rights reserved.
> +# Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010005
0x0001001A
> + BASE_NAME = SystemFirmwareDescriptor
> + FILE_GUID = 90B2B846-CA6D-4D6E-A8D3-C140A8E110AC
> + MODULE_TYPE = PEIM
> + VERSION_STRING = 1.0
> + ENTRY_POINT = SystemFirmwareDescriptorPeimEntry
> +
> +[Sources]
> + SystemFirmwareDescriptorPei.c
> + SystemFirmwareDescriptor.aslc
> +
> +[Packages]
> + ArmPkg/ArmPkg.dec
> + ArmPlatformPkg/ArmPlatformPkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + MdePkg/MdePkg.dec
> + SignedCapsulePkg/SignedCapsulePkg.dec
> +
> +[LibraryClasses]
> + DebugLib
> + PcdLib
> + PeimEntryPoint
> + PeiServicesLib
> +
> +[FixedPcd]
> + gArmTokenSpaceGuid.PcdFdSize
> +
> +[Pcd]
> + gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor
> +
> +[Depex]
> + TRUE
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH edk2-platforms v2 05/15] Hisilicon D03/D05: Add capsule upgrade support
2018-01-26 8:00 ` [PATCH edk2-platforms v2 05/15] Hisilicon D03/D05: Add capsule upgrade support Ming Huang
2018-01-29 19:58 ` Leif Lindholm
@ 2018-01-30 12:47 ` Ard Biesheuvel
1 sibling, 0 replies; 30+ messages in thread
From: Ard Biesheuvel @ 2018-01-30 12:47 UTC (permalink / raw)
To: Ming Huang
Cc: Leif Lindholm, linaro-uefi, edk2-devel@lists.01.org,
Graeme Gregory, guoheyi, wanghuiqiang, huangming, Jason Zhang,
Mengfanrong, huangdaode, waip23
On 26 January 2018 at 08:00, Ming Huang <heyi.guo@linaro.org> wrote:
> From: Jason Zhang <zhangjinsong2@huawei.com>
>
> This module support updating the boot CPU firmware only.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Jason Zhang <zhangjinsong2@huawei.com>
> Signed-off-by: Ming Huang <huangming23@huawei.com>
> Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
This looks good to me know.
Provided that you address Leif's additional comments:
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
> Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini | 45 +++++++
> Platform/Hisilicon/D03/D03.dsc | 17 ++-
> Platform/Hisilicon/D03/D03.fdf | 70 +++++++++++
> Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc | 81 +++++++++++++
> Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 50 ++++++++
> Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c | 70 +++++++++++
> Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini | 45 +++++++
> Platform/Hisilicon/D05/D05.dsc | 19 ++-
> Platform/Hisilicon/D05/D05.fdf | 70 +++++++++++
> Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc | 81 +++++++++++++
> Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 50 ++++++++
> Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c | 70 +++++++++++
> Silicon/Hisilicon/Hisilicon.dsc.inc | 11 +-
> Silicon/Hisilicon/Hisilicon.fdf.inc | 9 ++
> Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c | 123 ++++++++++++++++++++
> Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf | 51 ++++++++
> 16 files changed, 859 insertions(+), 3 deletions(-)
>
> diff --git a/Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini b/Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
> new file mode 100644
> index 0000000..fc834d9
> --- /dev/null
> +++ b/Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
> @@ -0,0 +1,45 @@
> +#
> +# Copyright (c) 2018, Hisilicon Limited. All rights reserved.
> +# Copyright (c) 2018, Linaro Limited. All rights reserved.
> +# Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +##
> +
> +[Head]
> +NumOfUpdate = 3
> +NumOfRecovery = 0
> +Update0 = SysFvMain
> +Update1 = SysCustom
> +Update2 = SysNvRam
> +
> +[SysFvMain]
> +FirmwareType = 0 # 0 - SystemFirmware, 1 - NvRam
> +AddressType = 0 # 0 - relative address, 1 - absolute address.
> +BaseAddress = 0x00000000 # Base address offset on flash
> +Length = 0x002D0000 # Length
> +ImageOffset = 0x00000000 # Image offset of this SystemFirmware image
> +FileGuid = 642e4fcf-2df7-4415-8b70-a03909c57b55 # PcdEdkiiSystemFirmwareFileGuid
> +
> +[SysCustom]
> +FirmwareType = 0 # 0 - SystemFirmware, 1 - NvRam
> +AddressType = 0 # 0 - relative address, 1 - absolute address.
> +BaseAddress = 0x002F0000 # Base address offset on flash
> +Length = 0x00010000 # Length
> +ImageOffset = 0x002F0000 # Image offset of this SystemFirmware image
> +FileGuid = 642e4fcf-2df7-4415-8b70-a03909c57b55 # PcdEdkiiSystemFirmwareFileGuid
> +
> +[SysNvRam]
> +FirmwareType = 1 # 0 - SystemFirmware, 1 - NvRam
> +AddressType = 0 # 0 - relative address, 1 - absolute address.
> +BaseAddress = 0x002D0000 # Base address offset on flash
> +Length = 0x00020000 # Length
> +ImageOffset = 0x002D0000 # Image offset of this SystemFirmware image
> +FileGuid = 642e4fcf-2df7-4415-8b70-a03909c57b55 # PcdEdkiiSystemFirmwareFileGuid
> diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc
> index e1e3b14..82c8bb4 100644
> --- a/Platform/Hisilicon/D03/D03.dsc
> +++ b/Platform/Hisilicon/D03/D03.dsc
> @@ -65,7 +65,6 @@
> OemAddressMapLib|Platform/Hisilicon/D03/Library/OemAddressMap2P/OemAddressMap2PHi1610.inf
> PlatformSysCtrlLib|Silicon/Hisilicon/Hi1610/Library/PlatformSysCtrlLibHi1610/PlatformSysCtrlLibHi1610.inf
>
> - CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
> GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
> PlatformBdsLib|Silicon/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf
> BmcConfigBootLib|Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf
> @@ -115,6 +114,11 @@
> gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
> gHisiTokenSpaceGuid.PcdIsItsSupported|TRUE
>
> +[PcdsDynamicExDefault.common.DEFAULT]
> + gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor|{0x0}|VOID*|0x100
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSystemFmpCapsuleImageTypeIdGuid|{0x29, 0x3d, 0x4b, 0xd3, 0x85, 0x00, 0xb3, 0x4a, 0x8b, 0xe8, 0x84, 0x18, 0x8c, 0xc5, 0x04, 0x89}
> + gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareFileGuid|{0xcf, 0x4f, 0x2e, 0x64, 0xf7, 0x2d, 0x15, 0x44, 0x8b, 0x70, 0xa0, 0x39, 0x09, 0xc5, 0x7b, 0x55}
> +
> [PcdsFixedAtBuild.common]
> gArmPlatformTokenSpaceGuid.PcdCoreCount|8
>
> @@ -305,6 +309,8 @@
> Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf
> Silicon/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
>
> + Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
> +
> MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
> <LibraryClasses>
> NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
> @@ -405,6 +411,9 @@
>
> Platform/Hisilicon/D03/Drivers/Sas/SasDxeDriver.inf
>
> + SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf
> + MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf
> +
> #
> # FAT filesystem + GPT/MBR partitioning
> #
> @@ -472,6 +481,12 @@
> MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
> MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
> MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
> + SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf {
> + <LibraryClasses>
> + FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibPkcs7/FmpAuthenticationLibPkcs7.inf
> + }
> +
> + MdeModulePkg/Application/CapsuleApp/CapsuleApp.inf
>
> #
> # UEFI application (Shell Embedded Boot Loader)
> diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf
> index 474f37f..6462a53 100644
> --- a/Platform/Hisilicon/D03/D03.fdf
> +++ b/Platform/Hisilicon/D03/D03.fdf
> @@ -275,6 +275,8 @@ READ_LOCK_STATUS = TRUE
> INF Platform/Hisilicon/D03/Drivers/SasPlatform/SasPlatform.inf
> INF Platform/Hisilicon/D03/Drivers/Sas/SasDxeDriver.inf
>
> + INF SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf
> + INF MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf
> #
> # Build Shell from latest source code instead of prebuilt binary
> #
> @@ -330,12 +332,80 @@ READ_LOCK_STATUS = TRUE
>
> INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
>
> + INF RuleOverride = FMP_IMAGE_DESC Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
> +
> FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
> SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
> SECTION FV_IMAGE = FVMAIN
> }
> }
>
> +[FV.CapsuleDispatchFv]
> +FvAlignment = 16
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +
> + INF SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf
> +
> +[FV.SystemFirmwareUpdateCargo]
> +FvAlignment = 16
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +
> + FILE RAW = 642e4fcf-2df7-4415-8b70-a03909c57b55 { # PcdEdkiiSystemFirmwareFileGuid
> + FD = D03
> + }
> +
> + FILE RAW = ce57b167-b0e4-41e8-a897-5f4feb781d40 { # gEdkiiSystemFmpCapsuleDriverFvFileGuid
> + FV = CapsuleDispatchFv
> + }
> +
> + FILE RAW = 812136D3-4D3A-433A-9418-29BB9BF78F6E { # gEdkiiSystemFmpCapsuleConfigFileGuid
> + Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
> + }
> +
> +[FmpPayload.FmpPayloadSystemFirmwarePkcs7]
> +IMAGE_HEADER_INIT_VERSION = 0x02
> +IMAGE_TYPE_ID = 44c850f2-85ff-4be5-bf34-a59528df22d3 # PcdSystemFmpCapsuleImageTypeIdGuid
> +IMAGE_INDEX = 0x1
> +HARDWARE_INSTANCE = 0x0
> +MONOTONIC_COUNT = 0x1
> +CERTIFICATE_GUID = 4AAFD29D-68DF-49EE-8AA9-347D375665A7 # PKCS7
> +
> + FV = SystemFirmwareUpdateCargo
> +
> +[Capsule.StyxFirmwareUpdateCapsuleFmpPkcs7]
> +CAPSULE_GUID = 6dcbd5ed-e82d-4c44-bda1-7194199ad92a # gEfiFmpCapsuleGuid
> +CAPSULE_HEADER_SIZE = 0x20
> +CAPSULE_HEADER_INIT_VERSION = 0x1
> +
> + FMP_PAYLOAD = FmpPayloadSystemFirmwarePkcs7
>
> !include Silicon/Hisilicon/Hisilicon.fdf.inc
>
> diff --git a/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc b/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
> new file mode 100644
> index 0000000..d9f4a00
> --- /dev/null
> +++ b/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
> @@ -0,0 +1,81 @@
> +/** @file
> + System Firmware descriptor.
> +
> + Copyright (c) 2018, Hisilicon Limited. All rights reserved.
> + Copyright (c) 2018, Linaro Limited. All rights reserved.
> + Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <PiPei.h>
> +#include <Guid/EdkiiSystemFmpCapsule.h>
> +#include <Protocol/FirmwareManagement.h>
> +
> +#define PACKAGE_VERSION 0xFFFFFFFF
> +#define PACKAGE_VERSION_STRING L"Unknown"
> +
> +#define CURRENT_FIRMWARE_VERSION 0x00000002
> +#define CURRENT_FIRMWARE_VERSION_STRING L"0x00000002"
> +#define LOWEST_SUPPORTED_FIRMWARE_VERSION 0x00000001
> +
> +#define IMAGE_ID SIGNATURE_64('H','W','A', 'R', 'M', '_', 'F', 'd')
> +#define IMAGE_ID_STRING L"ARMPlatformFd"
> +
> +// PcdSystemFmpCapsuleImageTypeIdGuid
> +#define IMAGE_TYPE_ID_GUID { 0x44c850f2, 0x85ff, 0x4be5, { 0xbf, 0x34, 0xa5, 0x95, 0x28, 0xdf, 0x22, 0xd3 } }
> +
> +typedef struct {
> + EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR Descriptor;
> + // real string data
> + CHAR16 ImageIdNameStr[sizeof(IMAGE_ID_STRING) / sizeof(CHAR16)];
> + CHAR16 VersionNameStr[sizeof(CURRENT_FIRMWARE_VERSION_STRING) / sizeof(CHAR16)];
> + CHAR16 PackageVersionNameStr[sizeof(PACKAGE_VERSION_STRING) / sizeof(CHAR16)];
> +} IMAGE_DESCRIPTOR;
> +
> +IMAGE_DESCRIPTOR mImageDescriptor =
> +{
> + {
> + EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR_SIGNATURE,
> + sizeof (EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR),
> + sizeof (IMAGE_DESCRIPTOR),
> + PACKAGE_VERSION, // PackageVersion
> + OFFSET_OF (IMAGE_DESCRIPTOR, PackageVersionNameStr), // PackageVersionName
> + 1, // ImageIndex;
> + {0x0}, // Reserved
> + IMAGE_TYPE_ID_GUID, // ImageTypeId;
> + IMAGE_ID, // ImageId;
> + OFFSET_OF (IMAGE_DESCRIPTOR, ImageIdNameStr), // ImageIdName;
> + CURRENT_FIRMWARE_VERSION, // Version;
> + OFFSET_OF (IMAGE_DESCRIPTOR, VersionNameStr), // VersionName;
> + {0x0}, // Reserved2
> + FixedPcdGet32 (PcdFdSize), // Size;
> + IMAGE_ATTRIBUTE_IMAGE_UPDATABLE |
> + IMAGE_ATTRIBUTE_RESET_REQUIRED |
> + IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED |
> + IMAGE_ATTRIBUTE_IN_USE, // AttributesSupported;
> + IMAGE_ATTRIBUTE_IMAGE_UPDATABLE |
> + IMAGE_ATTRIBUTE_RESET_REQUIRED |
> + IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED |
> + IMAGE_ATTRIBUTE_IN_USE, // AttributesSetting;
> + 0x0, // Compatibilities;
> + LOWEST_SUPPORTED_FIRMWARE_VERSION, // LowestSupportedImageVersion;
> + 0x00000000, // LastAttemptVersion;
> + 0, // LastAttemptStatus;
> + {0x0}, // Reserved3
> + 0, // HardwareInstance;
> + },
> + // real string data
> + {IMAGE_ID_STRING},
> + {CURRENT_FIRMWARE_VERSION_STRING},
> + {PACKAGE_VERSION_STRING},
> +};
> +
> +VOID* CONST ReferenceAcpiTable = &mImageDescriptor;
> diff --git a/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf b/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
> new file mode 100644
> index 0000000..c38a809
> --- /dev/null
> +++ b/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
> @@ -0,0 +1,50 @@
> +## @file
> +# System Firmware descriptor.
> +#
> +# Copyright (c) 2018, Hisilicon Limited. All rights reserved.
> +# Copyright (c) 2018, Linaro Limited. All rights reserved.
> +# Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = SystemFirmwareDescriptor
> + FILE_GUID = 90B2B846-CA6D-4D6E-A8D3-C140A8E110AC
> + MODULE_TYPE = PEIM
> + VERSION_STRING = 1.0
> + ENTRY_POINT = SystemFirmwareDescriptorPeimEntry
> +
> +[Sources]
> + SystemFirmwareDescriptorPei.c
> + SystemFirmwareDescriptor.aslc
> +
> +[Packages]
> + ArmPkg/ArmPkg.dec
> + ArmPlatformPkg/ArmPlatformPkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + MdePkg/MdePkg.dec
> + SignedCapsulePkg/SignedCapsulePkg.dec
> +
> +[LibraryClasses]
> + DebugLib
> + PcdLib
> + PeimEntryPoint
> + PeiServicesLib
> +
> +[FixedPcd]
> + gArmTokenSpaceGuid.PcdFdSize
> +
> +[Pcd]
> + gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor
> +
> +[Depex]
> + TRUE
> diff --git a/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c b/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c
> new file mode 100644
> index 0000000..27c0a71
> --- /dev/null
> +++ b/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c
> @@ -0,0 +1,70 @@
> +/** @file
> + System Firmware descriptor producer.
> +
> + Copyright (c) 2018, Hisilicon Limited. All rights reserved.
> + Copyright (c) 2018, Linaro Limited. All rights reserved.
> + Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <PiPei.h>
> +#include <Guid/EdkiiSystemFmpCapsule.h>
> +#include <Library/DebugLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/PeiServicesLib.h>
> +#include <Protocol/FirmwareManagement.h>
> +
> +/**
> + Entrypoint for SystemFirmwareDescriptor PEIM.
> +
> + @param[in] FileHandle Handle of the file being invoked.
> + @param[in] PeiServices Describes the list of possible PEI Services.
> +
> + @retval EFI_SUCCESS PPI successfully installed.
> +**/
> +EFI_STATUS
> +EFIAPI
> +SystemFirmwareDescriptorPeimEntry (
> + IN EFI_PEI_FILE_HANDLE FileHandle,
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + )
> +{
> + EFI_STATUS Status;
> + EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR *Descriptor;
> + UINTN Size;
> + UINTN Index;
> + UINT32 AuthenticationStatus;
> +
> + //
> + // Search RAW section.
> + //
> +
> + Index = 0;
> + while (TRUE) {
> + Status = PeiServicesFfsFindSectionData3 (EFI_SECTION_RAW, Index, FileHandle, (VOID **)&Descriptor, &AuthenticationStatus);
> + if (EFI_ERROR (Status)) {
> + // Should not happen, must something wrong in FDF.
> + DEBUG ((DEBUG_ERROR, "Not found SystemFirmwareDescriptor in fdf !\n"));
> + return EFI_NOT_FOUND;
> + }
> + if (Descriptor->Signature == EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR_SIGNATURE) {
> + break;
> + }
> + Index++;
> + }
> +
> + DEBUG ((DEBUG_INFO, "EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR size - 0x%x\n", Descriptor->Length));
> +
> + Size = Descriptor->Length;
> + PcdSetPtrS (PcdEdkiiSystemFirmwareImageDescriptor, &Size, Descriptor);
> +
> + return EFI_SUCCESS;
> +}
> diff --git a/Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini b/Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
> new file mode 100644
> index 0000000..fc834d9
> --- /dev/null
> +++ b/Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
> @@ -0,0 +1,45 @@
> +#
> +# Copyright (c) 2018, Hisilicon Limited. All rights reserved.
> +# Copyright (c) 2018, Linaro Limited. All rights reserved.
> +# Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +##
> +
> +[Head]
> +NumOfUpdate = 3
> +NumOfRecovery = 0
> +Update0 = SysFvMain
> +Update1 = SysCustom
> +Update2 = SysNvRam
> +
> +[SysFvMain]
> +FirmwareType = 0 # 0 - SystemFirmware, 1 - NvRam
> +AddressType = 0 # 0 - relative address, 1 - absolute address.
> +BaseAddress = 0x00000000 # Base address offset on flash
> +Length = 0x002D0000 # Length
> +ImageOffset = 0x00000000 # Image offset of this SystemFirmware image
> +FileGuid = 642e4fcf-2df7-4415-8b70-a03909c57b55 # PcdEdkiiSystemFirmwareFileGuid
> +
> +[SysCustom]
> +FirmwareType = 0 # 0 - SystemFirmware, 1 - NvRam
> +AddressType = 0 # 0 - relative address, 1 - absolute address.
> +BaseAddress = 0x002F0000 # Base address offset on flash
> +Length = 0x00010000 # Length
> +ImageOffset = 0x002F0000 # Image offset of this SystemFirmware image
> +FileGuid = 642e4fcf-2df7-4415-8b70-a03909c57b55 # PcdEdkiiSystemFirmwareFileGuid
> +
> +[SysNvRam]
> +FirmwareType = 1 # 0 - SystemFirmware, 1 - NvRam
> +AddressType = 0 # 0 - relative address, 1 - absolute address.
> +BaseAddress = 0x002D0000 # Base address offset on flash
> +Length = 0x00020000 # Length
> +ImageOffset = 0x002D0000 # Image offset of this SystemFirmware image
> +FileGuid = 642e4fcf-2df7-4415-8b70-a03909c57b55 # PcdEdkiiSystemFirmwareFileGuid
> diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
> index ac7da04..e39acb1 100644
> --- a/Platform/Hisilicon/D05/D05.dsc
> +++ b/Platform/Hisilicon/D05/D05.dsc
> @@ -81,7 +81,6 @@
> OemAddressMapLib|Platform/Hisilicon/D05/Library/OemAddressMapD05/OemAddressMapD05.inf
> PlatformSysCtrlLib|Silicon/Hisilicon/Hi1616/Library/PlatformSysCtrlLibHi1616/PlatformSysCtrlLibHi1616.inf
>
> - CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
> GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
> PlatformBdsLib|Silicon/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf
> BmcConfigBootLib|Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf
> @@ -128,6 +127,11 @@
> gHisiTokenSpaceGuid.PcdIsItsSupported|TRUE
> gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE
>
> +[PcdsDynamicExDefault.common.DEFAULT]
> + gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor|{0x0}|VOID*|0x100
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSystemFmpCapsuleImageTypeIdGuid|{0x29, 0x3d, 0x4b, 0xd3, 0x85, 0x00, 0xb3, 0x4a, 0x8b, 0xe8, 0x84, 0x18, 0x8c, 0xc5, 0x04, 0x89}
> + gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareFileGuid|{0xcf, 0x4f, 0x2e, 0x64, 0xf7, 0x2d, 0x15, 0x44, 0x8b, 0x70, 0xa0, 0x39, 0x09, 0xc5, 0x7b, 0x55}
> +
> [PcdsFixedAtBuild.common]
> gArmPlatformTokenSpaceGuid.PcdCoreCount|8
>
> @@ -444,6 +448,8 @@
> Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf
> Silicon/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
>
> + Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
> +
> MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
> <LibraryClasses>
> NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
> @@ -560,6 +566,9 @@
>
> Platform/Hisilicon/D05/Drivers/Sas/SasDxeDriver.inf
>
> + SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf
> + MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf
> +
> #
> # FAT filesystem + GPT/MBR partitioning
> #
> @@ -625,6 +634,14 @@
> MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
> MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
> MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
> +
> + SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf {
> + <LibraryClasses>
> + FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibPkcs7/FmpAuthenticationLibPkcs7.inf
> + }
> +
> + MdeModulePkg/Application/CapsuleApp/CapsuleApp.inf
> +
> #
> # UEFI application (Shell Embedded Boot Loader)
> #
> diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf
> index 9f8dc2a..b0296e1 100644
> --- a/Platform/Hisilicon/D05/D05.fdf
> +++ b/Platform/Hisilicon/D05/D05.fdf
> @@ -297,6 +297,8 @@ READ_LOCK_STATUS = TRUE
> INF Platform/Hisilicon/D05/Drivers/SasPlatform/SasPlatform.inf
> INF Platform/Hisilicon/D05/Drivers/Sas/SasDxeDriver.inf
>
> + INF SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf
> + INF MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf
> #
> # Build Shell from latest source code instead of prebuilt binary
> #
> @@ -355,12 +357,80 @@ READ_LOCK_STATUS = TRUE
>
> INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
>
> + INF RuleOverride = FMP_IMAGE_DESC Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
> +
> FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
> SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
> SECTION FV_IMAGE = FVMAIN
> }
> }
>
> +[FV.CapsuleDispatchFv]
> +FvAlignment = 16
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +
> + INF SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf
> +
> +[FV.SystemFirmwareUpdateCargo]
> +FvAlignment = 16
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +
> + FILE RAW = 642e4fcf-2df7-4415-8b70-a03909c57b55 { # PcdEdkiiSystemFirmwareFileGuid
> + FD = D05
> + }
> +
> + FILE RAW = ce57b167-b0e4-41e8-a897-5f4feb781d40 { # gEdkiiSystemFmpCapsuleDriverFvFileGuid
> + FV = CapsuleDispatchFv
> + }
> +
> + FILE RAW = 812136D3-4D3A-433A-9418-29BB9BF78F6E { # gEdkiiSystemFmpCapsuleConfigFileGuid
> + Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
> + }
> +
> +[FmpPayload.FmpPayloadSystemFirmwarePkcs7]
> +IMAGE_HEADER_INIT_VERSION = 0x02
> +IMAGE_TYPE_ID = 7978365d-7978-45fd-ad77-b27693cfe85b # PcdSystemFmpCapsuleImageTypeIdGuid
> +IMAGE_INDEX = 0x1
> +HARDWARE_INSTANCE = 0x0
> +MONOTONIC_COUNT = 0x1
> +CERTIFICATE_GUID = 4AAFD29D-68DF-49EE-8AA9-347D375665A7 # PKCS7
> +
> + FV = SystemFirmwareUpdateCargo
> +
> +[Capsule.StyxFirmwareUpdateCapsuleFmpPkcs7]
> +CAPSULE_GUID = 6dcbd5ed-e82d-4c44-bda1-7194199ad92a # gEfiFmpCapsuleGuid
> +CAPSULE_HEADER_SIZE = 0x20
> +CAPSULE_HEADER_INIT_VERSION = 0x1
> +
> + FMP_PAYLOAD = FmpPayloadSystemFirmwarePkcs7
>
> !include Silicon/Hisilicon/Hisilicon.fdf.inc
>
> diff --git a/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc b/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
> new file mode 100644
> index 0000000..9f65bb9
> --- /dev/null
> +++ b/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
> @@ -0,0 +1,81 @@
> +/** @file
> + System Firmware descriptor.
> +
> + Copyright (c) 2018, Hisilicon Limited. All rights reserved.
> + Copyright (c) 2018, Linaro Limited. All rights reserved.
> + Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <PiPei.h>
> +#include <Guid/EdkiiSystemFmpCapsule.h>
> +#include <Protocol/FirmwareManagement.h>
> +
> +#define PACKAGE_VERSION 0xFFFFFFFF
> +#define PACKAGE_VERSION_STRING L"Unknown"
> +
> +#define CURRENT_FIRMWARE_VERSION 0x00000002
> +#define CURRENT_FIRMWARE_VERSION_STRING L"0x00000002"
> +#define LOWEST_SUPPORTED_FIRMWARE_VERSION 0x00000001
> +
> +#define IMAGE_ID SIGNATURE_64('H','W','A', 'R', 'M', '_', 'F', 'd')
> +#define IMAGE_ID_STRING L"ARMPlatformFd"
> +
> +// PcdSystemFmpCapsuleImageTypeIdGuid
> +#define IMAGE_TYPE_ID_GUID { 0x7978365d, 0x7978, 0x45fd, { 0xad, 0x77, 0xb2, 0x76, 0x93, 0xcf, 0xe8, 0x5b } }
> +
> +typedef struct {
> + EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR Descriptor;
> + // real string data
> + CHAR16 ImageIdNameStr[sizeof(IMAGE_ID_STRING) / sizeof(CHAR16)];
> + CHAR16 VersionNameStr[sizeof(CURRENT_FIRMWARE_VERSION_STRING) / sizeof(CHAR16)];
> + CHAR16 PackageVersionNameStr[sizeof(PACKAGE_VERSION_STRING) / sizeof(CHAR16)];
> +} IMAGE_DESCRIPTOR;
> +
> +IMAGE_DESCRIPTOR mImageDescriptor =
> +{
> + {
> + EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR_SIGNATURE,
> + sizeof (EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR),
> + sizeof (IMAGE_DESCRIPTOR),
> + PACKAGE_VERSION, // PackageVersion
> + OFFSET_OF (IMAGE_DESCRIPTOR, PackageVersionNameStr), // PackageVersionName
> + 1, // ImageIndex;
> + {0x0}, // Reserved
> + IMAGE_TYPE_ID_GUID, // ImageTypeId;
> + IMAGE_ID, // ImageId;
> + OFFSET_OF (IMAGE_DESCRIPTOR, ImageIdNameStr), // ImageIdName;
> + CURRENT_FIRMWARE_VERSION, // Version;
> + OFFSET_OF (IMAGE_DESCRIPTOR, VersionNameStr), // VersionName;
> + {0x0}, // Reserved2
> + FixedPcdGet32 (PcdFdSize), // Size;
> + IMAGE_ATTRIBUTE_IMAGE_UPDATABLE |
> + IMAGE_ATTRIBUTE_RESET_REQUIRED |
> + IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED |
> + IMAGE_ATTRIBUTE_IN_USE, // AttributesSupported;
> + IMAGE_ATTRIBUTE_IMAGE_UPDATABLE |
> + IMAGE_ATTRIBUTE_RESET_REQUIRED |
> + IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED |
> + IMAGE_ATTRIBUTE_IN_USE, // AttributesSetting;
> + 0x0, // Compatibilities;
> + LOWEST_SUPPORTED_FIRMWARE_VERSION, // LowestSupportedImageVersion;
> + 0x00000000, // LastAttemptVersion;
> + 0, // LastAttemptStatus;
> + {0x0}, // Reserved3
> + 0, // HardwareInstance;
> + },
> + // real string data
> + {IMAGE_ID_STRING},
> + {CURRENT_FIRMWARE_VERSION_STRING},
> + {PACKAGE_VERSION_STRING},
> +};
> +
> +VOID* CONST ReferenceAcpiTable = &mImageDescriptor;
> diff --git a/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf b/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
> new file mode 100644
> index 0000000..c38a809
> --- /dev/null
> +++ b/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
> @@ -0,0 +1,50 @@
> +## @file
> +# System Firmware descriptor.
> +#
> +# Copyright (c) 2018, Hisilicon Limited. All rights reserved.
> +# Copyright (c) 2018, Linaro Limited. All rights reserved.
> +# Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = SystemFirmwareDescriptor
> + FILE_GUID = 90B2B846-CA6D-4D6E-A8D3-C140A8E110AC
> + MODULE_TYPE = PEIM
> + VERSION_STRING = 1.0
> + ENTRY_POINT = SystemFirmwareDescriptorPeimEntry
> +
> +[Sources]
> + SystemFirmwareDescriptorPei.c
> + SystemFirmwareDescriptor.aslc
> +
> +[Packages]
> + ArmPkg/ArmPkg.dec
> + ArmPlatformPkg/ArmPlatformPkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + MdePkg/MdePkg.dec
> + SignedCapsulePkg/SignedCapsulePkg.dec
> +
> +[LibraryClasses]
> + DebugLib
> + PcdLib
> + PeimEntryPoint
> + PeiServicesLib
> +
> +[FixedPcd]
> + gArmTokenSpaceGuid.PcdFdSize
> +
> +[Pcd]
> + gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor
> +
> +[Depex]
> + TRUE
> diff --git a/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c b/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c
> new file mode 100644
> index 0000000..27c0a71
> --- /dev/null
> +++ b/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c
> @@ -0,0 +1,70 @@
> +/** @file
> + System Firmware descriptor producer.
> +
> + Copyright (c) 2018, Hisilicon Limited. All rights reserved.
> + Copyright (c) 2018, Linaro Limited. All rights reserved.
> + Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <PiPei.h>
> +#include <Guid/EdkiiSystemFmpCapsule.h>
> +#include <Library/DebugLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/PeiServicesLib.h>
> +#include <Protocol/FirmwareManagement.h>
> +
> +/**
> + Entrypoint for SystemFirmwareDescriptor PEIM.
> +
> + @param[in] FileHandle Handle of the file being invoked.
> + @param[in] PeiServices Describes the list of possible PEI Services.
> +
> + @retval EFI_SUCCESS PPI successfully installed.
> +**/
> +EFI_STATUS
> +EFIAPI
> +SystemFirmwareDescriptorPeimEntry (
> + IN EFI_PEI_FILE_HANDLE FileHandle,
> + IN CONST EFI_PEI_SERVICES **PeiServices
> + )
> +{
> + EFI_STATUS Status;
> + EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR *Descriptor;
> + UINTN Size;
> + UINTN Index;
> + UINT32 AuthenticationStatus;
> +
> + //
> + // Search RAW section.
> + //
> +
> + Index = 0;
> + while (TRUE) {
> + Status = PeiServicesFfsFindSectionData3 (EFI_SECTION_RAW, Index, FileHandle, (VOID **)&Descriptor, &AuthenticationStatus);
> + if (EFI_ERROR (Status)) {
> + // Should not happen, must something wrong in FDF.
> + DEBUG ((DEBUG_ERROR, "Not found SystemFirmwareDescriptor in fdf !\n"));
> + return EFI_NOT_FOUND;
> + }
> + if (Descriptor->Signature == EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR_SIGNATURE) {
> + break;
> + }
> + Index++;
> + }
> +
> + DEBUG ((DEBUG_INFO, "EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR size - 0x%x\n", Descriptor->Length));
> +
> + Size = Descriptor->Length;
> + PcdSetPtrS (PcdEdkiiSystemFirmwareImageDescriptor, &Size, Descriptor);
> +
> + return EFI_SUCCESS;
> +}
> diff --git a/Silicon/Hisilicon/Hisilicon.dsc.inc b/Silicon/Hisilicon/Hisilicon.dsc.inc
> index 308064b..dfa11d1 100644
> --- a/Silicon/Hisilicon/Hisilicon.dsc.inc
> +++ b/Silicon/Hisilicon/Hisilicon.dsc.inc
> @@ -104,6 +104,15 @@
> ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
> SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
>
> + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibFmp/DxeCapsuleLib.inf
> + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
> + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
> + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
> + FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibPkcs7/FmpAuthenticationLibPkcs7.inf
> + EdkiiSystemCapsuleLib|SignedCapsulePkg/Library/EdkiiSystemCapsuleLib/EdkiiSystemCapsuleLib.inf
> + IniParsingLib|SignedCapsulePkg/Library/IniParsingLib/IniParsingLib.inf
> + PlatformFlashAccessLib|Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf
> +
> #
> # It is not possible to prevent the ARM compiler for generic intrinsic functions.
> # This library provides the instrinsic functions generate by a given compiler.
> @@ -198,7 +207,7 @@
> HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
> MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
> ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf
> - CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
> + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibFmp/DxeRuntimeCapsuleLib.inf
> SerialPortLib|Silicon/Hisilicon/Library/Dw8250SerialPortRuntimeLib/Dw8250SerialPortRuntimeLib.inf
> DebugLib|IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
>
> diff --git a/Silicon/Hisilicon/Hisilicon.fdf.inc b/Silicon/Hisilicon/Hisilicon.fdf.inc
> index ee87cd1..986dd75 100644
> --- a/Silicon/Hisilicon/Hisilicon.fdf.inc
> +++ b/Silicon/Hisilicon/Hisilicon.fdf.inc
> @@ -76,6 +76,15 @@
> }
> }
>
> +[Rule.Common.PEIM.FMP_IMAGE_DESC]
> + FILE PEIM = $(NAMED_GUID) {
> + RAW BIN |.acpi
> + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 Align=4K $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> [Rule.Common.DXE_CORE]
> FILE DXE_CORE = $(NAMED_GUID) {
> PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> diff --git a/Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c b/Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c
> new file mode 100644
> index 0000000..62da61c
> --- /dev/null
> +++ b/Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c
> @@ -0,0 +1,123 @@
> +/** @file
> + Platform Flash Access library.
> +
> + Copyright (c) 2018, Hisilicon Limited. All rights reserved.
> + Copyright (c) 2018, Linaro Limited. All rights reserved.
> + Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <PiDxe.h>
> +#include <Library/BaseLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/PlatformFlashAccessLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Protocol/HisiSpiFlashProtocol.h>
> +
> +STATIC EFI_PHYSICAL_ADDRESS mInternalFdAddress;
> +STATIC EFI_PHYSICAL_ADDRESS mSFCMEM0BaseAddress;
> +
> +STATIC HISI_SPI_FLASH_PROTOCOL *mSpiProtocol;
> +
> +/**
> + Perform flash write opreation.
> +
> + @param[in] FirmwareType The type of firmware.
> + @param[in] FlashAddress The address of flash device to be accessed.
> + @param[in] FlashAddressType The type of flash device address.
> + @param[in] Buffer The pointer to the data buffer.
> + @param[in] Length The length of data buffer in bytes.
> +
> + @retval EFI_SUCCESS The operation returns successfully.
> + @retval EFI_WRITE_PROTECTED The flash device is read only.
> + @retval EFI_UNSUPPORTED The flash device access is unsupported.
> + @retval EFI_INVALID_PARAMETER The input parameter is not valid.
> +**/
> +EFI_STATUS
> +EFIAPI
> +PerformFlashWrite (
> + IN PLATFORM_FIRMWARE_TYPE FirmwareType,
> + IN EFI_PHYSICAL_ADDRESS FlashAddress,
> + IN FLASH_ADDRESS_TYPE FlashAddressType,
> + IN VOID *Buffer,
> + IN UINTN Length
> + )
> +{
> + UINT32 RomAddress;
> + EFI_STATUS Status;
> +
> + DEBUG ((DEBUG_INFO,
> + "PerformFlashWrite - 0x%x(%x) - 0x%x\n",
> + (UINTN)FlashAddress,
> + (UINTN)FlashAddressType,
> + Length));
> +
> + if (FlashAddressType == FlashAddressTypeAbsoluteAddress) {
> + FlashAddress = FlashAddress - mInternalFdAddress;
> + }
> +
> + RomAddress = (UINT32)FlashAddress + (mInternalFdAddress - mSFCMEM0BaseAddress);
> +
> + DEBUG ((DEBUG_INFO, "Erase and Write Flash Start\n"));
> +
> + Status = mSpiProtocol->EraseWrite (
> + mSpiProtocol,
> + (UINT32) RomAddress,
> + (UINT8 *)Buffer,
> + (UINT32) Length
> + );
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "Erase and Write Status = %r \n", Status));
> + }
> +
> + return Status;
> +}
> +
> +/**
> + Platform Flash Access Lib Constructor.
> +
> + @param[in] ImageHandle The firmware allocated handle for the EFI image.
> + @param[in] SystemTable A pointer to the EFI System Table.
> +
> + @retval EFI_SUCCESS Constructor returns successfully.
> +**/
> +EFI_STATUS
> +EFIAPI
> +PerformFlashAccessLibConstructor (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> +
> + mInternalFdAddress = (EFI_PHYSICAL_ADDRESS) PcdGet64 (PcdFdBaseAddress);
> +
> + mSFCMEM0BaseAddress = (EFI_PHYSICAL_ADDRESS) PcdGet64 (PcdSFCMEM0BaseAddress);
> +
> + DEBUG ((DEBUG_INFO,
> + "PcdFlashAreaBaseAddress - 0x%x, PcdSFCMEM0BaseAddress - 0x%x \n",
> + mInternalFdAddress,
> + mSFCMEM0BaseAddress));
> +
> + Status = gBS->LocateProtocol (
> + &gHisiSpiFlashProtocolGuid,
> + NULL,
> + (VOID **)&mSpiProtocol);
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR,
> + "LocateProtocol gHisiSpiFlashProtocolGuid Status = %r \n",
> + Status));
> + }
> +
> + return Status;
> +}
> diff --git a/Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf b/Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf
> new file mode 100644
> index 0000000..ba209c9
> --- /dev/null
> +++ b/Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf
> @@ -0,0 +1,51 @@
> +## @file
> +# Platform Flash Access library.
> +#
> +# Copyright (c) 2018, Hisilicon Limited. All rights reserved.
> +# Copyright (c) 2018, Linaro Limited. All rights reserved.
> +# Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = PlatformFlashAccessLibDxe
> + FILE_GUID = c230e06c-c0d8-4935-8c23-9b8f7d33d1c4
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = PlatformFlashAccessLib|DXE_DRIVER
> + CONSTRUCTOR = PerformFlashAccessLibConstructor
> +
> +[Sources]
> + PlatformFlashAccessLibDxe.c
> +
> +[Packages]
> + ArmPkg/ArmPkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + MdePkg/MdePkg.dec
> + SignedCapsulePkg/SignedCapsulePkg.dec
> + Silicon/Hisilicon/HisiPkg.dec
> +
> +[LibraryClasses]
> + BaseMemoryLib
> + DebugLib
> + PcdLib
> + UefiBootServicesTableLib
> +
> +[Protocols]
> + gHisiSpiFlashProtocolGuid
> +
> +[FixedPcd]
> + gArmTokenSpaceGuid.PcdFdBaseAddress
> + gHisiTokenSpaceGuid.PcdSFCMEM0BaseAddress
> +
> +[Depex]
> + gHisiSpiFlashProtocolGuid
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH edk2-platforms v2 05/15] Hisilicon D03/D05: Add capsule upgrade support
2018-01-29 19:58 ` Leif Lindholm
@ 2018-01-30 12:48 ` Huangming (Mark)
2018-01-30 13:21 ` Leif Lindholm
0 siblings, 1 reply; 30+ messages in thread
From: Huangming (Mark) @ 2018-01-30 12:48 UTC (permalink / raw)
To: Leif Lindholm, Ming Huang
Cc: linaro-uefi, edk2-devel, graeme.gregory, ard.biesheuvel, guoheyi,
wanghuiqiang, zhangjinsong2, mengfanrong, huangdaode, waip23
On 2018/1/30 3:58, Leif Lindholm wrote:
> A few style comments below.
>
> On Fri, Jan 26, 2018 at 04:00:40PM +0800, Ming Huang wrote:
>> From: Jason Zhang <zhangjinsong2@huawei.com>
>>
>> This module support updating the boot CPU firmware only.
>>
>> Contributed-under: TianoCore Contribution Agreement 1.1
>> Signed-off-by: Jason Zhang <zhangjinsong2@huawei.com>
>> Signed-off-by: Ming Huang <huangming23@huawei.com>
>> Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
>> ---
>> Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini | 45 +++++++
>> Platform/Hisilicon/D03/D03.dsc | 17 ++-
>> Platform/Hisilicon/D03/D03.fdf | 70 +++++++++++
>> Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc | 81 +++++++++++++
>> Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 50 ++++++++
>> Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c | 70 +++++++++++
>> Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini | 45 +++++++
>> Platform/Hisilicon/D05/D05.dsc | 19 ++-
>> Platform/Hisilicon/D05/D05.fdf | 70 +++++++++++
>> Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc | 81 +++++++++++++
>> Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 50 ++++++++
>> Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c | 70 +++++++++++
>> Silicon/Hisilicon/Hisilicon.dsc.inc | 11 +-
>> Silicon/Hisilicon/Hisilicon.fdf.inc | 9 ++
>> Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c | 123 ++++++++++++++++++++
>> Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf | 51 ++++++++
>> 16 files changed, 859 insertions(+), 3 deletions(-)
>>
>
>> diff --git a/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc b/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
>> new file mode 100644
>> index 0000000..d9f4a00
>> --- /dev/null
>> +++ b/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
>> @@ -0,0 +1,81 @@
>> +/** @file
>> + System Firmware descriptor.
>> +
>> + Copyright (c) 2018, Hisilicon Limited. All rights reserved.
>> + Copyright (c) 2018, Linaro Limited. All rights reserved.
>> + Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
>> +
>> + This program and the accompanying materials
>> + are licensed and made available under the terms and conditions of the BSD License
>> + which accompanies this distribution. The full text of the license may be found at
>> + http://opensource.org/licenses/bsd-license.php
>> +
>> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +
>> +**/
>> +
>> +#include <PiPei.h>
>> +#include <Guid/EdkiiSystemFmpCapsule.h>
>> +#include <Protocol/FirmwareManagement.h>
>> +
>> +#define PACKAGE_VERSION 0xFFFFFFFF
>> +#define PACKAGE_VERSION_STRING L"Unknown"
>> +
>> +#define CURRENT_FIRMWARE_VERSION 0x00000002
>> +#define CURRENT_FIRMWARE_VERSION_STRING L"0x00000002"
>> +#define LOWEST_SUPPORTED_FIRMWARE_VERSION 0x00000001
>> +
>> +#define IMAGE_ID SIGNATURE_64('H','W','A', 'R', 'M', '_', 'F', 'd')
>> +#define IMAGE_ID_STRING L"ARMPlatformFd"
>> +
>> +// PcdSystemFmpCapsuleImageTypeIdGuid
>> +#define IMAGE_TYPE_ID_GUID { 0x44c850f2, 0x85ff, 0x4be5, { 0xbf, 0x34, 0xa5, 0x95, 0x28, 0xdf, 0x22, 0xd3 } }
>> +
>> +typedef struct {
>> + EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR Descriptor;
>> + // real string data
>> + CHAR16 ImageIdNameStr[sizeof(IMAGE_ID_STRING) / sizeof(CHAR16)];
>> + CHAR16 VersionNameStr[sizeof(CURRENT_FIRMWARE_VERSION_STRING) / sizeof(CHAR16)];
>> + CHAR16 PackageVersionNameStr[sizeof(PACKAGE_VERSION_STRING) / sizeof(CHAR16)];
>
> Use ARRAY_SIZE for the 3 above?
>
If use ARRAY_SIZE, the three macro must change to array of CHAR16.
It is not necessary maybe.The same style is found in SystemFirmwareDescriptor.aslc from other platform,like AMD,Socionext.
Thanks,
Ming
>> +} IMAGE_DESCRIPTOR;
>> +
>> +IMAGE_DESCRIPTOR mImageDescriptor =
>> +{
>> + {
>> + EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR_SIGNATURE,
>> + sizeof (EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR),
>> + sizeof (IMAGE_DESCRIPTOR),
>> + PACKAGE_VERSION, // PackageVersion
>> + OFFSET_OF (IMAGE_DESCRIPTOR, PackageVersionNameStr), // PackageVersionName
>> + 1, // ImageIndex;
>> + {0x0}, // Reserved
>> + IMAGE_TYPE_ID_GUID, // ImageTypeId;
>> + IMAGE_ID, // ImageId;
>> + OFFSET_OF (IMAGE_DESCRIPTOR, ImageIdNameStr), // ImageIdName;
>> + CURRENT_FIRMWARE_VERSION, // Version;
>> + OFFSET_OF (IMAGE_DESCRIPTOR, VersionNameStr), // VersionName;
>> + {0x0}, // Reserved2
>> + FixedPcdGet32 (PcdFdSize), // Size;
>> + IMAGE_ATTRIBUTE_IMAGE_UPDATABLE |
>> + IMAGE_ATTRIBUTE_RESET_REQUIRED |
>> + IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED |
>> + IMAGE_ATTRIBUTE_IN_USE, // AttributesSupported;
>> + IMAGE_ATTRIBUTE_IMAGE_UPDATABLE |
>> + IMAGE_ATTRIBUTE_RESET_REQUIRED |
>> + IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED |
>> + IMAGE_ATTRIBUTE_IN_USE, // AttributesSetting;
>> + 0x0, // Compatibilities;
>> + LOWEST_SUPPORTED_FIRMWARE_VERSION, // LowestSupportedImageVersion;
>> + 0x00000000, // LastAttemptVersion;
>> + 0, // LastAttemptStatus;
>> + {0x0}, // Reserved3
>> + 0, // HardwareInstance;
>> + },
>> + // real string data
>> + {IMAGE_ID_STRING},
>> + {CURRENT_FIRMWARE_VERSION_STRING},
>> + {PACKAGE_VERSION_STRING},
>> +};
>> +
>> +VOID* CONST ReferenceAcpiTable = &mImageDescriptor;
>> diff --git a/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf b/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
>> new file mode 100644
>> index 0000000..c38a809
>> --- /dev/null
>> +++ b/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
>> @@ -0,0 +1,50 @@
>> +## @file
>> +# System Firmware descriptor.
>> +#
>> +# Copyright (c) 2018, Hisilicon Limited. All rights reserved.
>> +# Copyright (c) 2018, Linaro Limited. All rights reserved.
>> +# Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
>> +#
>> +# This program and the accompanying materials
>> +# are licensed and made available under the terms and conditions of the BSD License
>> +# which accompanies this distribution. The full text of the license may be found at
>> +# http://opensource.org/licenses/bsd-license.php
>> +#
>> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +#
>> +##
>> +
>> +[Defines]
>> + INF_VERSION = 0x00010005
>
> 0x0001001A
>
>> + BASE_NAME = SystemFirmwareDescriptor
>> + FILE_GUID = 90B2B846-CA6D-4D6E-A8D3-C140A8E110AC
>> + MODULE_TYPE = PEIM
>> + VERSION_STRING = 1.0
>> + ENTRY_POINT = SystemFirmwareDescriptorPeimEntry
>> +
>> +[Sources]
>> + SystemFirmwareDescriptorPei.c
>> + SystemFirmwareDescriptor.aslc
>> +
>> +[Packages]
>> + ArmPkg/ArmPkg.dec
>> + ArmPlatformPkg/ArmPlatformPkg.dec
>> + MdeModulePkg/MdeModulePkg.dec
>> + MdePkg/MdePkg.dec
>> + SignedCapsulePkg/SignedCapsulePkg.dec
>> +
>> +[LibraryClasses]
>> + DebugLib
>> + PcdLib
>> + PeimEntryPoint
>> + PeiServicesLib
>> +
>> +[FixedPcd]
>> + gArmTokenSpaceGuid.PcdFdSize
>> +
>> +[Pcd]
>> + gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor
>> +
>> +[Depex]
>> + TRUE
>
>> diff --git a/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc b/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
>> new file mode 100644
>> index 0000000..9f65bb9
>> --- /dev/null
>> +++ b/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
>> @@ -0,0 +1,81 @@
>> +/** @file
>> + System Firmware descriptor.
>> +
>> + Copyright (c) 2018, Hisilicon Limited. All rights reserved.
>> + Copyright (c) 2018, Linaro Limited. All rights reserved.
>> + Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
>> +
>> + This program and the accompanying materials
>> + are licensed and made available under the terms and conditions of the BSD License
>> + which accompanies this distribution. The full text of the license may be found at
>> + http://opensource.org/licenses/bsd-license.php
>> +
>> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +
>> +**/
>> +
>> +#include <PiPei.h>
>> +#include <Guid/EdkiiSystemFmpCapsule.h>
>> +#include <Protocol/FirmwareManagement.h>
>> +
>> +#define PACKAGE_VERSION 0xFFFFFFFF
>> +#define PACKAGE_VERSION_STRING L"Unknown"
>> +
>> +#define CURRENT_FIRMWARE_VERSION 0x00000002
>> +#define CURRENT_FIRMWARE_VERSION_STRING L"0x00000002"
>> +#define LOWEST_SUPPORTED_FIRMWARE_VERSION 0x00000001
>> +
>> +#define IMAGE_ID SIGNATURE_64('H','W','A', 'R', 'M', '_', 'F', 'd')
>> +#define IMAGE_ID_STRING L"ARMPlatformFd"
>> +
>> +// PcdSystemFmpCapsuleImageTypeIdGuid
>> +#define IMAGE_TYPE_ID_GUID { 0x7978365d, 0x7978, 0x45fd, { 0xad, 0x77, 0xb2, 0x76, 0x93, 0xcf, 0xe8, 0x5b } }
>> +
>> +typedef struct {
>> + EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR Descriptor;
>> + // real string data
>> + CHAR16 ImageIdNameStr[sizeof(IMAGE_ID_STRING) / sizeof(CHAR16)];
>> + CHAR16 VersionNameStr[sizeof(CURRENT_FIRMWARE_VERSION_STRING) / sizeof(CHAR16)];
>> + CHAR16 PackageVersionNameStr[sizeof(PACKAGE_VERSION_STRING) / sizeof(CHAR16)];
>
> 3x ARRAY_SIZE?
>
>> +} IMAGE_DESCRIPTOR;
>> +
>> +IMAGE_DESCRIPTOR mImageDescriptor =
>> +{
>> + {
>> + EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR_SIGNATURE,
>> + sizeof (EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR),
>> + sizeof (IMAGE_DESCRIPTOR),
>> + PACKAGE_VERSION, // PackageVersion
>> + OFFSET_OF (IMAGE_DESCRIPTOR, PackageVersionNameStr), // PackageVersionName
>> + 1, // ImageIndex;
>> + {0x0}, // Reserved
>> + IMAGE_TYPE_ID_GUID, // ImageTypeId;
>> + IMAGE_ID, // ImageId;
>> + OFFSET_OF (IMAGE_DESCRIPTOR, ImageIdNameStr), // ImageIdName;
>> + CURRENT_FIRMWARE_VERSION, // Version;
>> + OFFSET_OF (IMAGE_DESCRIPTOR, VersionNameStr), // VersionName;
>> + {0x0}, // Reserved2
>> + FixedPcdGet32 (PcdFdSize), // Size;
>> + IMAGE_ATTRIBUTE_IMAGE_UPDATABLE |
>> + IMAGE_ATTRIBUTE_RESET_REQUIRED |
>> + IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED |
>> + IMAGE_ATTRIBUTE_IN_USE, // AttributesSupported;
>> + IMAGE_ATTRIBUTE_IMAGE_UPDATABLE |
>> + IMAGE_ATTRIBUTE_RESET_REQUIRED |
>> + IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED |
>> + IMAGE_ATTRIBUTE_IN_USE, // AttributesSetting;
>> + 0x0, // Compatibilities;
>> + LOWEST_SUPPORTED_FIRMWARE_VERSION, // LowestSupportedImageVersion;
>> + 0x00000000, // LastAttemptVersion;
>> + 0, // LastAttemptStatus;
>> + {0x0}, // Reserved3
>> + 0, // HardwareInstance;
>> + },
>> + // real string data
>> + {IMAGE_ID_STRING},
>> + {CURRENT_FIRMWARE_VERSION_STRING},
>> + {PACKAGE_VERSION_STRING},
>> +};
>> +
>> +VOID* CONST ReferenceAcpiTable = &mImageDescriptor;
>> diff --git a/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf b/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
>> new file mode 100644
>> index 0000000..c38a809
>> --- /dev/null
>> +++ b/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
>> @@ -0,0 +1,50 @@
>> +## @file
>> +# System Firmware descriptor.
>> +#
>> +# Copyright (c) 2018, Hisilicon Limited. All rights reserved.
>> +# Copyright (c) 2018, Linaro Limited. All rights reserved.
>> +# Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
>> +#
>> +# This program and the accompanying materials
>> +# are licensed and made available under the terms and conditions of the BSD License
>> +# which accompanies this distribution. The full text of the license may be found at
>> +# http://opensource.org/licenses/bsd-license.php
>> +#
>> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +#
>> +##
>> +
>> +[Defines]
>> + INF_VERSION = 0x00010005
>
> 0x0001001A
>
>> + BASE_NAME = SystemFirmwareDescriptor
>> + FILE_GUID = 90B2B846-CA6D-4D6E-A8D3-C140A8E110AC
>> + MODULE_TYPE = PEIM
>> + VERSION_STRING = 1.0
>> + ENTRY_POINT = SystemFirmwareDescriptorPeimEntry
>> +
>> +[Sources]
>> + SystemFirmwareDescriptorPei.c
>> + SystemFirmwareDescriptor.aslc
>> +
>> +[Packages]
>> + ArmPkg/ArmPkg.dec
>> + ArmPlatformPkg/ArmPlatformPkg.dec
>> + MdeModulePkg/MdeModulePkg.dec
>> + MdePkg/MdePkg.dec
>> + SignedCapsulePkg/SignedCapsulePkg.dec
>> +
>> +[LibraryClasses]
>> + DebugLib
>> + PcdLib
>> + PeimEntryPoint
>> + PeiServicesLib
>> +
>> +[FixedPcd]
>> + gArmTokenSpaceGuid.PcdFdSize
>> +
>> +[Pcd]
>> + gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor
>> +
>> +[Depex]
>> + TRUE
>
> .
>
--
Best Regards,
Ming
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH edk2-platforms v2 05/15] Hisilicon D03/D05: Add capsule upgrade support
2018-01-30 12:48 ` Huangming (Mark)
@ 2018-01-30 13:21 ` Leif Lindholm
2018-01-31 1:14 ` Huangming (Mark)
0 siblings, 1 reply; 30+ messages in thread
From: Leif Lindholm @ 2018-01-30 13:21 UTC (permalink / raw)
To: Huangming (Mark)
Cc: Ming Huang, linaro-uefi, edk2-devel, graeme.gregory,
ard.biesheuvel, guoheyi, wanghuiqiang, zhangjinsong2, mengfanrong,
huangdaode, waip23
On Tue, Jan 30, 2018 at 08:48:27PM +0800, Huangming (Mark) wrote:
>
>
> On 2018/1/30 3:58, Leif Lindholm wrote:
> > A few style comments below.
> >
> > On Fri, Jan 26, 2018 at 04:00:40PM +0800, Ming Huang wrote:
> >> From: Jason Zhang <zhangjinsong2@huawei.com>
> >>
> >> This module support updating the boot CPU firmware only.
> >>
> >> Contributed-under: TianoCore Contribution Agreement 1.1
> >> Signed-off-by: Jason Zhang <zhangjinsong2@huawei.com>
> >> Signed-off-by: Ming Huang <huangming23@huawei.com>
> >> Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
> >> ---
> >> Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini | 45 +++++++
> >> Platform/Hisilicon/D03/D03.dsc | 17 ++-
> >> Platform/Hisilicon/D03/D03.fdf | 70 +++++++++++
> >> Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc | 81 +++++++++++++
> >> Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 50 ++++++++
> >> Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c | 70 +++++++++++
> >> Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini | 45 +++++++
> >> Platform/Hisilicon/D05/D05.dsc | 19 ++-
> >> Platform/Hisilicon/D05/D05.fdf | 70 +++++++++++
> >> Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc | 81 +++++++++++++
> >> Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 50 ++++++++
> >> Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c | 70 +++++++++++
> >> Silicon/Hisilicon/Hisilicon.dsc.inc | 11 +-
> >> Silicon/Hisilicon/Hisilicon.fdf.inc | 9 ++
> >> Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c | 123 ++++++++++++++++++++
> >> Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf | 51 ++++++++
> >> 16 files changed, 859 insertions(+), 3 deletions(-)
> >>
> >
> >> diff --git a/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc b/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
> >> new file mode 100644
> >> index 0000000..d9f4a00
> >> --- /dev/null
> >> +++ b/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
> >> @@ -0,0 +1,81 @@
> >> +/** @file
> >> + System Firmware descriptor.
> >> +
> >> + Copyright (c) 2018, Hisilicon Limited. All rights reserved.
> >> + Copyright (c) 2018, Linaro Limited. All rights reserved.
> >> + Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
> >> +
> >> + This program and the accompanying materials
> >> + are licensed and made available under the terms and conditions of the BSD License
> >> + which accompanies this distribution. The full text of the license may be found at
> >> + http://opensource.org/licenses/bsd-license.php
> >> +
> >> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> >> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> >> +
> >> +**/
> >> +
> >> +#include <PiPei.h>
> >> +#include <Guid/EdkiiSystemFmpCapsule.h>
> >> +#include <Protocol/FirmwareManagement.h>
> >> +
> >> +#define PACKAGE_VERSION 0xFFFFFFFF
> >> +#define PACKAGE_VERSION_STRING L"Unknown"
> >> +
> >> +#define CURRENT_FIRMWARE_VERSION 0x00000002
> >> +#define CURRENT_FIRMWARE_VERSION_STRING L"0x00000002"
> >> +#define LOWEST_SUPPORTED_FIRMWARE_VERSION 0x00000001
> >> +
> >> +#define IMAGE_ID SIGNATURE_64('H','W','A', 'R', 'M', '_', 'F', 'd')
> >> +#define IMAGE_ID_STRING L"ARMPlatformFd"
> >> +
> >> +// PcdSystemFmpCapsuleImageTypeIdGuid
> >> +#define IMAGE_TYPE_ID_GUID { 0x44c850f2, 0x85ff, 0x4be5, { 0xbf, 0x34, 0xa5, 0x95, 0x28, 0xdf, 0x22, 0xd3 } }
> >> +
> >> +typedef struct {
> >> + EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR Descriptor;
> >> + // real string data
> >> + CHAR16 ImageIdNameStr[sizeof(IMAGE_ID_STRING) / sizeof(CHAR16)];
> >> + CHAR16 VersionNameStr[sizeof(CURRENT_FIRMWARE_VERSION_STRING) / sizeof(CHAR16)];
> >> + CHAR16 PackageVersionNameStr[sizeof(PACKAGE_VERSION_STRING) / sizeof(CHAR16)];
> >
> > Use ARRAY_SIZE for the 3 above?
>
> If use ARRAY_SIZE, the three macro must change to array of CHAR16.
What problem are you encountering when simply replacing
CHAR16 ImageIdNameStr[sizeof(IMAGE_ID_STRING) / sizeof(CHAR16)];
with
CHAR16 ImageIdNameStr[ARRAY_SIZE (IMAGE_ID_STRING)];
?
> It is not necessary maybe.The same style is found in
> SystemFirmwareDescriptor.aslc from other platform,like
> AMD,Socionext.
Patches welcome.
ARRAY_SIZE was only added to MdePkg in October 2016.
Ideally, all code should be using this macro, but at least we can try
to make sure all _new_ code uses it, when we spot missed opportunities.
/
Leif
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH edk2-platforms v2 01/15] Hisilicon/D05: Move Madt definition to head file
2018-01-26 8:00 ` [PATCH edk2-platforms v2 01/15] Hisilicon/D05: Move Madt definition to head file Ming Huang
@ 2018-01-30 14:27 ` graeme.gregory
0 siblings, 0 replies; 30+ messages in thread
From: graeme.gregory @ 2018-01-30 14:27 UTC (permalink / raw)
To: Ming Huang
Cc: leif.lindholm, linaro-uefi, edk2-devel, ard.biesheuvel, guoheyi,
wanghuiqiang, huangming23, zhangjinsong2, mengfanrong, huangdaode,
waip23
[-- Attachment #1: Type: text/plain, Size: 4708 bytes --]
On Fri, Jan 26, 2018 at 04:00:36PM +0800, Ming Huang wrote:
> Move definition of Madt struct to head file, so PPTT driver
> can include it.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ming Huang <huangming23@huawei.com>
> Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
> ---
Looks sane to me
Reviewed-by: Graeme Gregory <graeme@xora.org.uk>
> Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h | 30 +++++++++++++++++++-
> Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc | 23 +--------------
> 2 files changed, 30 insertions(+), 23 deletions(-)
>
> diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h
> index 808219a..ad73aa2 100644
> --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h
> +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h
> @@ -1,7 +1,7 @@
> /** @file
> *
> * Copyright (c) 2011-2015, ARM Limited. All rights reserved.
> -* Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.
> +* Copyright (c) 2015-2018, Hisilicon Limited. All rights reserved.
> * Copyright (c) 2015-2016, Linaro Limited. All rights reserved.
> *
> * This program and the accompanying materials
> @@ -20,6 +20,8 @@
> #ifndef _HI1610_PLATFORM_H_
> #define _HI1610_PLATFORM_H_
>
> +#include <IndustryStandard/Acpi.h>
> +
> //
> // ACPI table information used to initialize tables.
> //
> @@ -44,5 +46,31 @@
> }
>
> #define HI1616_WATCHDOG_COUNT 2
> +#define HI1616_GIC_STRUCTURE_COUNT 64
> +
> +#define HI1616_MPID_TA_BASE 0x10000
> +#define HI1616_MPID_TB_BASE 0x30000
> +#define HI1616_MPID_TA_2_BASE 0x50000
> +#define HI1616_MPID_TB_2_BASE 0x70000
> +
> +// Differs from Juno, we have another affinity level beyond cluster and core
> +#define PLATFORM_GET_MPID_TA(ClusterId, CoreId) (HI1616_MPID_TA_BASE | ((ClusterId) << 8) | (CoreId))
> +#define PLATFORM_GET_MPID_TB(ClusterId, CoreId) (HI1616_MPID_TB_BASE | ((ClusterId) << 8) | (CoreId))
> +#define PLATFORM_GET_MPID_TA_2(ClusterId, CoreId) (HI1616_MPID_TA_2_BASE | ((ClusterId) << 8) | (CoreId))
> +#define PLATFORM_GET_MPID_TB_2(ClusterId, CoreId) (HI1616_MPID_TB_2_BASE | ((ClusterId) << 8) | (CoreId))
> +
> +//
> +// Multiple APIC Description Table
> +//
> +#pragma pack (1)
> +
> +typedef struct {
> + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
> + EFI_ACPI_6_1_GIC_STRUCTURE GicInterfaces[HI1616_GIC_STRUCTURE_COUNT];
> + EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
> + EFI_ACPI_6_1_GIC_ITS_STRUCTURE GicITS[8];
> +} EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE;
> +
> +#pragma pack ()
>
> #endif
> diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc b/Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc
> index 169ee72..54605a6 100644
> --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc
> +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc
> @@ -2,7 +2,7 @@
> * Multiple APIC Description Table (MADT)
> *
> * Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
> -* Copyright (c) 2015 - 2016, Hisilicon Limited. All rights reserved.
> +* Copyright (c) 2015 - 2018, Hisilicon Limited. All rights reserved.
> * Copyright (c) 2015 - 2016, Linaro Limited. All rights reserved.
> *
> * This program and the accompanying materials
> @@ -27,27 +27,6 @@
> #include <Library/PcdLib.h>
> #include "Hi1616Platform.h"
>
> -// Differs from Juno, we have another affinity level beyond cluster and core
> -// 0x20000 is only for socket 0
> -#define PLATFORM_GET_MPID_TA(ClusterId, CoreId) (0x10000 | ((ClusterId) << 8) | (CoreId))
> -#define PLATFORM_GET_MPID_TB(ClusterId, CoreId) (0x30000 | ((ClusterId) << 8) | (CoreId))
> -#define PLATFORM_GET_MPID_TA_2(ClusterId, CoreId) (0x50000 | ((ClusterId) << 8) | (CoreId))
> -#define PLATFORM_GET_MPID_TB_2(ClusterId, CoreId) (0x70000 | ((ClusterId) << 8) | (CoreId))
> -
> -//
> -// Multiple APIC Description Table
> -//
> -#pragma pack (1)
> -
> -typedef struct {
> - EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
> - EFI_ACPI_6_1_GIC_STRUCTURE GicInterfaces[64];
> - EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
> - EFI_ACPI_6_1_GIC_ITS_STRUCTURE GicITS[8];
> -} EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE;
> -
> -#pragma pack ()
> -
> EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
> {
> ARM_ACPI_HEADER (
> --
> 1.9.1
>
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH edk2-platforms v2 02/15] Hisilicon/D05: Add PPTT support
2018-01-26 8:00 ` [PATCH edk2-platforms v2 02/15] Hisilicon/D05: Add PPTT support Ming Huang
@ 2018-01-30 14:28 ` graeme.gregory
2018-02-01 1:11 ` Jeremy Linton
1 sibling, 0 replies; 30+ messages in thread
From: graeme.gregory @ 2018-01-30 14:28 UTC (permalink / raw)
To: Ming Huang
Cc: leif.lindholm, linaro-uefi, edk2-devel, ard.biesheuvel, guoheyi,
wanghuiqiang, huangming23, zhangjinsong2, mengfanrong, huangdaode,
waip23
[-- Attachment #1: Type: text/plain, Size: 27448 bytes --]
On Fri, Jan 26, 2018 at 04:00:37PM +0800, Ming Huang wrote:
> Add Processor Properties Topology Table, PPTT include
> Processor hierarchy node, Cache Type Structure and ID structure.
>
> PPTT is needed for lscpu command to show socket information correctly.
> https://bugs.linaro.org/show_bug.cgi?id=3206
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ming Huang <huangming23@huawei.com>
> Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
> ---
Code looks sane enough to me, but I cant give an indepth review of the
PPTT bit.
Reviewed-by: Graeme Gregory <graeme@xora.org.uk>
> Platform/Hisilicon/D05/D05.dsc | 1 +
> Platform/Hisilicon/D05/D05.fdf | 1 +
> Silicon/Hisilicon/Hi1616/Pptt/Pptt.c | 540 ++++++++++++++++++++
> Silicon/Hisilicon/Hi1616/Pptt/Pptt.h | 88 ++++
> Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf | 48 ++
> 5 files changed, 678 insertions(+)
>
> diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
> index 77a89fd..710339c 100644
> --- a/Platform/Hisilicon/D05/D05.dsc
> +++ b/Platform/Hisilicon/D05/D05.dsc
> @@ -506,6 +506,7 @@
> MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
>
> Silicon/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
> + Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf
> Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
>
> #
> diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf
> index 78ab0c8..97de4d2 100644
> --- a/Platform/Hisilicon/D05/D05.fdf
> +++ b/Platform/Hisilicon/D05/D05.fdf
> @@ -241,6 +241,7 @@ READ_LOCK_STATUS = TRUE
> INF Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
>
> INF RuleOverride=ACPITABLE Silicon/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
> + INF Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf
> INF Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
>
> #
> diff --git a/Silicon/Hisilicon/Hi1616/Pptt/Pptt.c b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.c
> new file mode 100644
> index 0000000..71c456c
> --- /dev/null
> +++ b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.c
> @@ -0,0 +1,540 @@
> +/** @file
> +*
> +* Copyright (c) 2018, Hisilicon Limited. All rights reserved.
> +* Copyright (c) 2018, Linaro Limited. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +* Based on the files under Platform/ARM/JunoPkg/AcpiTables/
> +*
> +**/
> +
> +#include "Pptt.h"
> +
> +EFI_ACPI_TABLE_PROTOCOL *mAcpiTableProtocol = NULL;
> +EFI_ACPI_SDT_PROTOCOL *mAcpiSdtProtocol = NULL;
> +
> +EFI_ACPI_DESCRIPTION_HEADER mPpttHeader =
> + ARM_ACPI_HEADER (
> + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
> + EFI_ACPI_DESCRIPTION_HEADER,
> + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
> + );
> +
> +EFI_ACPI_6_2_PPTT_STRUCTURE_ID mPpttSocketType2[PPTT_SOCKET_COMPONENT_NO] =
> +{
> + {2, sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID), {0, 0}, 0, 0, 0, 0, 0, 0}
> +};
> +
> +EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE mPpttCacheType1[PPTT_CACHE_NO];
> +
> +
> +STATIC
> +VOID
> +InitCacheInfo (
> + VOID
> + )
> +{
> + UINT8 Index;
> + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES Type1Attributes;
> + CSSELR_DATA CsselrData;
> + CCSIDR_DATA CcsidrData;
> +
> + for (Index = 0; Index < PPTT_CACHE_NO; Index++) {
> + CsselrData.Data = 0;
> + CcsidrData.Data = 0;
> + SetMem (
> + &Type1Attributes,
> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES),
> + 0
> + );
> +
> + if (Index == 0) { //L1I
> + CsselrData.Bits.InD = 1;
> + CsselrData.Bits.Level = 0;
> + Type1Attributes.CacheType = 1;
> + } else if (Index == 1) {
> + Type1Attributes.CacheType = 0;
> + CsselrData.Bits.Level = Index - 1;
> + } else {
> + Type1Attributes.CacheType = 2;
> + CsselrData.Bits.Level = Index - 1;
> + }
> +
> + CcsidrData.Data = ReadCCSIDR (CsselrData.Data);
> +
> + if (CcsidrData.Bits.Wa == 1) {
> + Type1Attributes.AllocationType = PPTT_TYPE1_ALLOCATION_WRITE;
> + if (CcsidrData.Bits.Ra == 1) {
> + Type1Attributes.AllocationType = PPTT_TYPE1_ALLOCATION_READ_WRITE;
> + }
> + }
> +
> + if (CcsidrData.Bits.Wt == 1) {
> + Type1Attributes.WritePolicy = 1;
> + }
> + DEBUG ((DEBUG_INFO,
> + "[Acpi PPTT] Level = %x!CcsidrData = %x!\n",
> + CsselrData.Bits.Level,
> + CcsidrData.Data));
> +
> + mPpttCacheType1[Index].Type = EFI_ACPI_6_2_PPTT_TYPE_CACHE;
> + mPpttCacheType1[Index].Length = sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE);
> + mPpttCacheType1[Index].Reserved[0] = 0;
> + mPpttCacheType1[Index].Reserved[1] = 0;
> + mPpttCacheType1[Index].Flags.SizePropertyValid = 1;
> + mPpttCacheType1[Index].Flags.NumberOfSetsValid = 1;
> + mPpttCacheType1[Index].Flags.AssociativityValid = 1;
> + mPpttCacheType1[Index].Flags.AllocationTypeValid = 1;
> + mPpttCacheType1[Index].Flags.CacheTypeValid = 1;
> + mPpttCacheType1[Index].Flags.WritePolicyValid = 1;
> + mPpttCacheType1[Index].Flags.LineSizeValid = 1;
> + mPpttCacheType1[Index].Flags.Reserved = 0;
> + mPpttCacheType1[Index].NextLevelOfCache = 0;
> +
> + if (Index != PPTT_CACHE_NO - 1) {
> + mPpttCacheType1[Index].NumberOfSets = (UINT16)CcsidrData.Bits.NumSets + 1;
> + mPpttCacheType1[Index].Associativity = (UINT16)CcsidrData.Bits.Associativity + 1;
> + mPpttCacheType1[Index].LineSize = (UINT16)( 1 << (CcsidrData.Bits.LineSize + 4));
> + mPpttCacheType1[Index].Size = mPpttCacheType1[Index].LineSize * \
> + mPpttCacheType1[Index].Associativity * \
> + mPpttCacheType1[Index].NumberOfSets;
> + CopyMem (
> + &mPpttCacheType1[Index].Attributes,
> + &Type1Attributes,
> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES)
> + );
> + } else {
> + // L3 cache
> + mPpttCacheType1[Index].Size = 0x1000000; // 16m
> + mPpttCacheType1[Index].NumberOfSets = 0x2000;
> + mPpttCacheType1[Index].Associativity = 0x10; // CacheAssociativity16Way
> + SetMem (
> + &mPpttCacheType1[Index].Attributes,
> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES),
> + 0x0A
> + );
> + mPpttCacheType1[Index].LineSize = 0x80; // 128byte
> + }
> + }
> +}
> +
> +STATIC
> +EFI_STATUS
> +AddCoreTable (
> + IN EFI_ACPI_DESCRIPTION_HEADER *PpttTable,
> + IN OUT UINT32 *PpttTableLengthRemain,
> + IN UINT32 Flags,
> + IN UINT32 Parent,
> + IN UINT32 ResourceNo,
> + IN UINT32 ProcessorId
> + )
> +{
> + EFI_ACPI_6_2_PPTT_TYPE0 *PpttType0;
> + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *PpttType1;
> + UINT32 *PrivateResource;
> + UINT8 Index;
> +
> + if (*PpttTableLengthRemain <
> + (sizeof (EFI_ACPI_6_2_PPTT_TYPE0) + ResourceNo * 4)) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> + PpttType0 = (EFI_ACPI_6_2_PPTT_TYPE0 *)((UINT8 *)PpttTable +
> + PpttTable->Length);
> + PpttType0->Type = 0;
> + CopyMem (&PpttType0->Flags, &Flags, sizeof(PpttType0->Flags));;
> + PpttType0->Parent= Parent;
> + PpttType0->AcpiProcessorId = ProcessorId;
> + PpttType0->NumberOfPrivateResources = ResourceNo;
> + PpttType0->Length = sizeof (EFI_ACPI_6_2_PPTT_TYPE0) +
> + ResourceNo * 4;
> +
> + *PpttTableLengthRemain -= (UINTN)PpttType0->Length;
> + PpttTable->Length += PpttType0->Length;
> + PrivateResource = (UINT32 *)((UINT8 *)PpttType0 +
> + sizeof (EFI_ACPI_6_2_PPTT_TYPE0));
> +
> + // Add cache type structure
> + for (Index = 0; Index < ResourceNo; Index++, PrivateResource++) {
> + if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE)) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> + *PrivateResource = PpttTable->Length;
> + PpttType1 = (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *)((UINT8 *)PpttTable +
> + PpttTable->Length);
> + gBS->CopyMem (
> + PpttType1,
> + &mPpttCacheType1[Index],
> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE)
> + );
> + *PpttTableLengthRemain -= PpttType1->Length;
> + PpttTable->Length += PpttType1->Length;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +STATIC
> +EFI_STATUS
> +AddClusterTable (
> + IN EFI_ACPI_DESCRIPTION_HEADER *PpttTable,
> + IN OUT UINT32 *PpttTableLengthRemain,
> + IN UINT32 Flags,
> + IN UINT32 Parent,
> + IN UINT32 ResourceNo
> + )
> +{
> + EFI_ACPI_6_2_PPTT_TYPE0 *PpttType0;
> + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *PpttType1;
> + UINT32 *PrivateResource;
> +
> + if ((*PpttTableLengthRemain) <
> + (sizeof (EFI_ACPI_6_2_PPTT_TYPE0) + ResourceNo * 4)) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> + PpttType0 = (EFI_ACPI_6_2_PPTT_TYPE0 *)((UINT8 *)PpttTable +
> + PpttTable->Length);
> + PpttType0->Type = 0;
> + CopyMem (&PpttType0->Flags, &Flags, sizeof(PpttType0->Flags));;
> + PpttType0->Parent= Parent;
> + PpttType0->NumberOfPrivateResources = ResourceNo;
> + PpttType0->Length = sizeof (EFI_ACPI_6_2_PPTT_TYPE0) +
> + ResourceNo * 4;
> +
> + *PpttTableLengthRemain -= PpttType0->Length;
> + PpttTable->Length += PpttType0->Length;
> + PrivateResource = (UINT32 *)((UINT8 *)PpttType0 +
> + sizeof (EFI_ACPI_6_2_PPTT_TYPE0));
> +
> + // Add cache type structure
> + if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE)) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> + *PrivateResource = PpttTable->Length;
> + PpttType1 = (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *)((UINT8 *)PpttTable +
> + PpttTable->Length);
> + gBS->CopyMem (
> + PpttType1,
> + &mPpttCacheType1[2],
> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE)
> + );
> + *PpttTableLengthRemain -= PpttType1->Length;
> + PpttTable->Length += PpttType1->Length;
> +
> + return EFI_SUCCESS;
> +}
> +
> +STATIC
> +EFI_STATUS
> +AddScclTable (
> + IN EFI_ACPI_DESCRIPTION_HEADER *PpttTable,
> + IN OUT UINT32 *PpttTableLengthRemain,
> + IN UINT32 Flags,
> + IN UINT32 Parent,
> + IN UINT32 ResourceNo
> + )
> +{
> + EFI_ACPI_6_2_PPTT_TYPE0 *PpttType0;
> + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *PpttType1;
> + UINT32 *PrivateResource;
> +
> + if (*PpttTableLengthRemain <
> + (sizeof (EFI_ACPI_6_2_PPTT_TYPE0) + ResourceNo * 4)) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> + PpttType0 = (EFI_ACPI_6_2_PPTT_TYPE0 *)((UINT8 *)PpttTable +
> + PpttTable->Length);
> + PpttType0->Type = 0;
> + CopyMem (&PpttType0->Flags, &Flags, sizeof(PpttType0->Flags));;
> + PpttType0->Parent= Parent;
> + PpttType0->NumberOfPrivateResources = ResourceNo;
> + PpttType0->Length = sizeof (EFI_ACPI_6_2_PPTT_TYPE0) +
> + ResourceNo * 4;
> +
> + *PpttTableLengthRemain -= PpttType0->Length;
> + PpttTable->Length += PpttType0->Length;
> + PrivateResource = (UINT32 *)((UINT8 *)PpttType0 +
> + sizeof (EFI_ACPI_6_2_PPTT_TYPE0));
> +
> + // Add cache type structure
> + if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE)) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> + *PrivateResource = PpttTable->Length;
> + PpttType1 = (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *)((UINT8 *)PpttTable +
> + PpttTable->Length);
> + gBS->CopyMem (
> + PpttType1,
> + &mPpttCacheType1[3],
> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE)
> + );
> + *PpttTableLengthRemain -= PpttType1->Length;
> + PpttTable->Length += PpttType1->Length;
> +
> + return EFI_SUCCESS;
> +}
> +
> +STATIC
> +EFI_STATUS
> +AddSocketTable (
> + IN EFI_ACPI_DESCRIPTION_HEADER *PpttTable,
> + IN OUT UINT32 *PpttTableLengthRemain,
> + IN UINT32 Flags,
> + IN UINT32 Parent,
> + IN UINT32 ResourceNo
> + )
> +{
> + EFI_ACPI_6_2_PPTT_TYPE0 *PpttType0;
> + EFI_ACPI_6_2_PPTT_STRUCTURE_ID *PpttType2;
> + UINT32 *PrivateResource;
> + UINT8 Index;
> +
> + if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_TYPE0)) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> + PpttType0 = (EFI_ACPI_6_2_PPTT_TYPE0 *)((UINT8 *)PpttTable +
> + PpttTable->Length);
> + PpttType0->Type = 0;
> + CopyMem (&PpttType0->Flags, &Flags, sizeof(PpttType0->Flags));;
> + PpttType0->Parent= Parent;
> + PpttType0->NumberOfPrivateResources = ResourceNo;
> + PpttType0->Length = sizeof (EFI_ACPI_6_2_PPTT_TYPE0) +
> + ResourceNo * 4;
> + PpttTable->Length += PpttType0->Length;
> +
> + *PpttTableLengthRemain -= PpttType0->Length;
> + if (*PpttTableLengthRemain < ResourceNo * 4) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> + PrivateResource = (UINT32 *)((UINT8 *)PpttType0 +
> + sizeof (EFI_ACPI_6_2_PPTT_TYPE0));
> + DEBUG ((DEBUG_INFO,
> + "[Acpi PPTT] sizeof(EFI_ACPI_6_2_PPTT_STRUCTURE_ID) = %x!\n",
> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID)));
> +
> + for (Index = 0; Index < ResourceNo; Index++, PrivateResource++) {
> + if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID)) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> + *PrivateResource = PpttTable->Length;
> + PpttType2 = (EFI_ACPI_6_2_PPTT_STRUCTURE_ID *)((UINT8 *)PpttTable +
> + PpttTable->Length);
> + gBS->CopyMem (
> + PpttType2,
> + &mPpttSocketType2[Index],
> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID)
> + );
> + *PpttTableLengthRemain -= PpttType2->Length;
> + PpttTable->Length += PpttType2->Length;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +STATIC
> +VOID
> +GetApic (
> + IN EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE *ApicTable,
> + IN OUT EFI_ACPI_DESCRIPTION_HEADER *PpttTable,
> + IN UINT32 PpttTableLengthRemain,
> + IN UINT32 Index1
> +)
> +{
> + UINT32 IndexSocket, IndexSccl, IndexCluster, IndexCore;
> + UINT32 SocketOffset, ScclOffset, ClusterOffset;
> + UINT32 Parent = 0;
> + UINT32 Flags = 0;
> + UINT32 ResourceNo = 0;
> +
> + // Get APIC data
> + for (IndexSocket = 0; IndexSocket < PPTT_SOCKET_NO; IndexSocket++) {
> + SocketOffset = 0;
> + for (IndexSccl = 0; IndexSccl < PPTT_SCCL_NO; IndexSccl++) {
> + ScclOffset = 0;
> + for (IndexCluster = 0; IndexCluster < PPTT_CLUSTER_NO; IndexCluster++) {
> + ClusterOffset = 0;
> + for (IndexCore = 0; IndexCore < PPTT_CORE_NO; IndexCore++) {
> + if (ApicTable->GicInterfaces[Index1].AcpiProcessorUid != Index1) {
> + // This processor is unusable
> + DEBUG ((DEBUG_ERROR, "[Acpi PPTT] Please check MADT table for UID!\n"));
> + return;
> + }
> + if ((ApicTable->GicInterfaces[Index1].Flags & BIT0) == 0) {
> + // This processor is unusable
> + Index1++;
> + continue;
> + }
> +
> + if (SocketOffset == 0) {
> + // Add socket0 for type0 table
> + ResourceNo = PPTT_SOCKET_COMPONENT_NO;
> + SocketOffset = PpttTable->Length;
> + Parent = 0;
> + Flags = PPTT_TYPE0_SOCKET_FLAG;
> + AddSocketTable (
> + PpttTable,
> + &PpttTableLengthRemain,
> + Flags,
> + Parent,
> + ResourceNo
> + );
> + }
> + if (ScclOffset == 0) {
> + // Add socket0sccl0 for type0 table
> + ResourceNo = 1;
> + ScclOffset = PpttTable->Length;
> + Parent = SocketOffset;
> + Flags = PPTT_TYPE0_SCCL_FLAG;
> + AddScclTable (
> + PpttTable,
> + &PpttTableLengthRemain,
> + Flags,
> + Parent,
> + ResourceNo
> + );
> + }
> + if (ClusterOffset == 0) {
> + // Add socket0sccl0ClusterId for type0 table
> + ResourceNo = 1;
> + ClusterOffset = PpttTable->Length ;
> + Parent = ScclOffset;
> + Flags = PPTT_TYPE0_CLUSTER_FLAG;
> + AddClusterTable (
> + PpttTable,
> + &PpttTableLengthRemain,
> + Flags,
> + Parent,
> + ResourceNo
> + );
> + }
> +
> + // Add socket0sccl0ClusterIdCoreId for type0 table
> + ResourceNo = 2;
> + Parent = ClusterOffset;
> + Flags = PPTT_TYPE0_CORE_FLAG;
> + AddCoreTable (
> + PpttTable,
> + &PpttTableLengthRemain,
> + Flags,
> + Parent,
> + ResourceNo,
> + Index1
> + );
> +
> + Index1++;
> + }
> + }
> + }
> + }
> + return ;
> +}
> +
> +STATIC
> +VOID
> +PpttSetAcpiTable (
> + IN EFI_EVENT Event,
> + IN VOID *Context
> + )
> +{
> + UINTN AcpiTableHandle;
> + EFI_STATUS Status;
> + UINT8 Checksum;
> + EFI_ACPI_SDT_HEADER *Table;
> + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE *ApicTable;
> + EFI_ACPI_TABLE_VERSION TableVersion;
> + EFI_ACPI_DESCRIPTION_HEADER *PpttTable;
> + UINTN TableKey;
> + UINT32 Index0, Index1;
> + UINT32 PpttTableLengthRemain = 0;
> +
> + gBS->CloseEvent (Event);
> +
> + InitCacheInfo ();
> +
> + PpttTable = (EFI_ACPI_DESCRIPTION_HEADER *)AllocateZeroPool (PPTT_TABLE_MAX_LEN);
> + gBS->CopyMem (
> + (VOID *)PpttTable,
> + &mPpttHeader,
> + sizeof (EFI_ACPI_DESCRIPTION_HEADER)
> + );
> + PpttTableLengthRemain = PPTT_TABLE_MAX_LEN - sizeof (EFI_ACPI_DESCRIPTION_HEADER);
> +
> + for (Index0 = 0; Index0 < EFI_ACPI_MAX_NUM_TABLES; Index0++) {
> + Status = mAcpiSdtProtocol->GetAcpiTable (
> + Index0,
> + &Table,
> + &TableVersion,
> + &TableKey
> + );
> + if (EFI_ERROR (Status)) {
> + break;
> + }
> +
> + // Find APIC table
> + if (Table->Signature == EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE) {
> + break;
> + }
> +
> + }
> +
> + if (!EFI_ERROR (Status) && (Index0 != EFI_ACPI_MAX_NUM_TABLES)) {
> + ApicTable = (EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE *)Table;
> + Index1 = 0;
> +
> + GetApic (ApicTable, PpttTable, PpttTableLengthRemain, Index1);
> +
> + Checksum = CalculateCheckSum8 ((UINT8 *)(PpttTable), PpttTable->Length);
> + PpttTable->Checksum = Checksum;
> +
> + AcpiTableHandle = 0;
> + Status = mAcpiTableProtocol->InstallAcpiTable (
> + mAcpiTableProtocol,
> + PpttTable,
> + PpttTable->Length,
> + &AcpiTableHandle);
> + }
> +
> + FreePool (PpttTable);
> + return ;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +PpttEntryPoint(
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> + EFI_EVENT ReadyToBootEvent;
> +
> + Status = gBS->LocateProtocol (
> + &gEfiAcpiTableProtocolGuid,
> + NULL,
> + (VOID **)&mAcpiTableProtocol);
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = gBS->LocateProtocol (
> + &gEfiAcpiSdtProtocolGuid,
> + NULL,
> + (VOID **)&mAcpiSdtProtocol);
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = EfiCreateEventReadyToBootEx (
> + TPL_NOTIFY,
> + PpttSetAcpiTable,
> + NULL,
> + &ReadyToBootEvent
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + DEBUG ((DEBUG_INFO, "Acpi Pptt init done.\n"));
> +
> + return Status;
> +}
> diff --git a/Silicon/Hisilicon/Hi1616/Pptt/Pptt.h b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.h
> new file mode 100644
> index 0000000..57f8386
> --- /dev/null
> +++ b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.h
> @@ -0,0 +1,88 @@
> +/** @file
> +*
> +* Copyright (c) 2018, Hisilicon Limited. All rights reserved.
> +* Copyright (c) 2018, Linaro Limited. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +* Based on the files under Platform/ARM/JunoPkg/AcpiTables/
> +*
> +**/
> +
> +#ifndef _PPTT_H_
> +#define _PPTT_H_
> +
> +#include <IndustryStandard/Acpi.h>
> +#include <Library/ArmLib/ArmLibPrivate.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/UefiLib.h>
> +#include <Protocol/AcpiSystemDescriptionTable.h>
> +#include <Protocol/AcpiTable.h>
> +#include "../D05AcpiTables/Hi1616Platform.h"
> +
> +#define EFI_ACPI_MAX_NUM_TABLES 20
> +
> +#define PPTT_TABLE_MAX_LEN 0x6000
> +#define PPTT_SOCKET_NO 0x2
> +#define PPTT_SCCL_NO 0x2
> +#define PPTT_CLUSTER_NO 0x4
> +#define PPTT_CORE_NO 0x4
> +#define PPTT_SOCKET_COMPONENT_NO 0x1
> +#define PPTT_CACHE_NO 0x4
> +
> +#define PPTT_TYPE0_PHYSICAL_PKG BIT0
> +#define PPTT_TYPE0_PROCESSORID_VALID BIT1
> +#define PPTT_TYPE0_SOCKET_FLAG PPTT_TYPE0_PHYSICAL_PKG
> +#define PPTT_TYPE0_SCCL_FLAG 0
> +#define PPTT_TYPE0_CLUSTER_FLAG 0
> +#define PPTT_TYPE0_CORE_FLAG PPTT_TYPE0_PROCESSORID_VALID
> +
> +#define PPTT_TYPE1_ALLOCATION_WRITE 0x1
> +#define PPTT_TYPE1_ALLOCATION_READ_WRITE 0x2
> +
> +typedef union {
> + struct {
> + UINT32 InD :1;
> + UINT32 Level :3;
> + UINT32 Reserved :28;
> + } Bits;
> + UINT32 Data;
> +} CSSELR_DATA;
> +
> +typedef union {
> + struct {
> + UINT32 LineSize :3;
> + UINT32 Associativity :10;
> + UINT32 NumSets :15;
> + UINT32 Wa :1;
> + UINT32 Ra :1;
> + UINT32 Wb :1;
> + UINT32 Wt :1;
> + } Bits;
> + UINT32 Data;
> +} CCSIDR_DATA;
> +
> +//
> +// Processor Hierarchy Node Structure
> +//
> +typedef struct {
> + UINT8 Type;
> + UINT8 Length;
> + UINT8 Reserved[2];
> + UINT32 Flags;
> + UINT32 Parent;
> + UINT32 AcpiProcessorId;
> + UINT32 NumberOfPrivateResources;
> +} EFI_ACPI_6_2_PPTT_TYPE0;
> +
> +#endif // _PPTT_H_
> +
> diff --git a/Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf
> new file mode 100644
> index 0000000..ff6f772
> --- /dev/null
> +++ b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf
> @@ -0,0 +1,48 @@
> +/** @file
> +*
> +* Copyright (c) 2018, Hisilicon Limited. All rights reserved.
> +* Copyright (c) 2018, Linaro Limited. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +* Based on the files under Platform/ARM/JunoPkg/AcpiTables/
> +*
> +**/
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = AcpiPptt
> + FILE_GUID = AAB14F90-DC2E-4f33-A594-C7894A5B412D
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + ENTRY_POINT = PpttEntryPoint
> +
> +[Sources.common]
> + Pptt.c
> +
> +[Packages]
> + ArmPkg/ArmPkg.dec
> + MdePkg/MdePkg.dec
> + Silicon/Hisilicon/HisiPkg.dec
> +
> +[LibraryClasses]
> + ArmLib
> + BaseMemoryLib
> + DebugLib
> + HobLib
> + UefiDriverEntryPoint
> + UefiRuntimeServicesTableLib
> +
> +[Protocols]
> + gEfiAcpiSdtProtocolGuid ## PROTOCOL ALWAYS_CONSUMED
> + gEfiAcpiTableProtocolGuid ## PROTOCOL ALWAYS_CONSUMED
> +
> +[Depex]
> + gEfiAcpiTableProtocolGuid AND gEfiAcpiSdtProtocolGuid
> +
> --
> 1.9.1
>
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* Re: [PATCH edk2-platforms v2 13/15] Hisilicon/D05/ACPI: Add ITS PXM
2018-01-26 8:00 ` [PATCH edk2-platforms v2 13/15] Hisilicon/D05/ACPI: Add ITS PXM Ming Huang
@ 2018-01-30 14:30 ` graeme.gregory
0 siblings, 0 replies; 30+ messages in thread
From: graeme.gregory @ 2018-01-30 14:30 UTC (permalink / raw)
To: Ming Huang
Cc: leif.lindholm, linaro-uefi, edk2-devel, ard.biesheuvel, guoheyi,
wanghuiqiang, huangming23, zhangjinsong2, mengfanrong, huangdaode,
waip23
[-- Attachment #1: Type: text/plain, Size: 3848 bytes --]
On Fri, Jan 26, 2018 at 04:00:48PM +0800, Ming Huang wrote:
> Add ITS affinity structure in SRAT.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ming Huang <huangming23@huawei.com>
> Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
> ---
Looks sane to me.
Reviewed-by: Graeme Gregory <graeme@xora.org.uk>
> Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc | 10 ++++++++++
> Silicon/Hisilicon/Include/Library/AcpiNextLib.h | 10 +++++++++-
> 2 files changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc
> index b448a29..8ea0c4b 100644
> --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc
> +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc
> @@ -121,6 +121,16 @@ EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE Srat = {
> EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003E,0x00000001,0x00000000), //GICC Affinity Processor 62
> EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003F,0x00000001,0x00000000) //GICC Affinity Processor 63
> },
> + {
> + EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x00000000, 0x00000000),
> + EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x00000001, 0x00000001),
> + EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x00000000, 0x00000002),
> + EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x00000001, 0x00000003),
> + EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x00000002, 0x00000004),
> + EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x00000003, 0x00000005),
> + EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x00000002, 0x00000006),
> + EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x00000003, 0x00000007)
> + },
> };
>
> //
> diff --git a/Silicon/Hisilicon/Include/Library/AcpiNextLib.h b/Silicon/Hisilicon/Include/Library/AcpiNextLib.h
> index 60f9925..fd05a3b 100644
> --- a/Silicon/Hisilicon/Include/Library/AcpiNextLib.h
> +++ b/Silicon/Hisilicon/Include/Library/AcpiNextLib.h
> @@ -39,6 +39,13 @@
> ACPIProcessorUID, Flags, ClockDomain \
> }
>
> +#define EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT( \
> + ProximityDomain, ItsId) \
> + { \
> + 4, sizeof (EFI_ACPI_6_2_GIC_ITS_AFFINITY_STRUCTURE), ProximityDomain, \
> + {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, ItsId \
> + }
> +
> #define EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT( \
> ProximityDomain, AddressBaseLow, AddressBaseHigh, LengthLow, LengthHigh, Flags) \
> { \
> @@ -70,12 +77,13 @@
> //
> #define EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT 64
> #define EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT 10
> -
> +#define EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_COUNT 8
>
> typedef struct {
> EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER Header;
> EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE Memory[EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT];
> EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE Gicc[EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT];
> + EFI_ACPI_6_2_GIC_ITS_AFFINITY_STRUCTURE Its[EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_COUNT];
> } EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE;
>
> #pragma pack()
> --
> 1.9.1
>
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* Re: [PATCH edk2-platforms v2 14/15] Hisilicon/D05/ACPI: Add Pcie, HNS and SAS PXM
2018-01-26 8:00 ` [PATCH edk2-platforms v2 14/15] Hisilicon/D05/ACPI: Add Pcie, HNS and SAS PXM Ming Huang
@ 2018-01-30 14:31 ` graeme.gregory
0 siblings, 0 replies; 30+ messages in thread
From: graeme.gregory @ 2018-01-30 14:31 UTC (permalink / raw)
To: Ming Huang
Cc: leif.lindholm, linaro-uefi, edk2-devel, ard.biesheuvel, guoheyi,
wanghuiqiang, huangming23, zhangjinsong2, mengfanrong, huangdaode,
waip23
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On Fri, Jan 26, 2018 at 04:00:49PM +0800, Ming Huang wrote:
> Add PXM method for Pcie device, HNS device and SAS device.
> Add STA method for HNS.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: hensonwang <wanghuiqiang@huawei.com>
> Signed-off-by: Ming Huang <huangming23@huawei.com>
> Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
> ---
Looks sane to me
Reviewed-by: Graeme Gregory <graeme@xora.org.uk>
> Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl | 9 ++++++
> Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 34 ++++++++++++++++++--
> Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl | 19 +++++++++--
> 3 files changed, 57 insertions(+), 5 deletions(-)
>
> diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl
> index 11c28ba..7aa04af 100644
> --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl
> +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl
> @@ -233,6 +233,15 @@ Scope(_SB)
> }
> })
>
> + Method (_PXM, 0, NotSerialized)
> + {
> + Return(0x00)
> + }
> + Method (_STA, 0, NotSerialized)
> + {
> + Return(0x0F)
> + }
> +
> //reset XGE port
> //Arg0 : XGE port index in dsaf
> //Arg1 : 0 reset, 1 cancle reset
> diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl
> index 55c7f50..122e4f0 100644
> --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl
> +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl
> @@ -141,7 +141,10 @@ Scope(_SB)
> {
> Return (0xf)
> }
> -
> + Method (_PXM, 0, NotSerialized)
> + {
> + Return(0x00)
> + }
> } // Device(PCI2)
>
> Device (RES2)
> @@ -240,7 +243,10 @@ Scope(_SB)
> {
> Return (RBYV())
> }
> -
> + Method (_PXM, 0, NotSerialized)
> + {
> + Return(0x01)
> + }
> } // Device(PCI4)
> Device (RES4)
> {
> @@ -338,6 +344,10 @@ Scope(_SB)
> {
> Return (RBYV())
> }
> + Method (_PXM, 0, NotSerialized)
> + {
> + Return(0x01)
> + }
> } // Device(PCI5)
> Device (RES5)
> {
> @@ -435,6 +445,10 @@ Scope(_SB)
> {
> Return (RBYV())
> }
> + Method (_PXM, 0, NotSerialized)
> + {
> + Return(0x01)
> + }
> } // Device(PCI6)
> Device (RES6)
> {
> @@ -531,6 +545,10 @@ Scope(_SB)
> {
> Return (RBYV())
> }
> + Method (_PXM, 0, NotSerialized)
> + {
> + Return(0x01)
> + }
> } // Device(PCI7)
> Device (RES7)
> {
> @@ -690,6 +708,10 @@ Scope(_SB)
> {
> Return (0xf)
> }
> + Method (_PXM, 0, NotSerialized)
> + {
> + Return(0x02)
> + }
> } // Device(PCIa)
> Device (RESa)
> {
> @@ -810,6 +832,10 @@ Scope(_SB)
> {
> Return (RBYV())
> }
> + Method (_PXM, 0, NotSerialized)
> + {
> + Return(0x03)
> + }
> } // Device(PCIc)
>
> Device (RESc)
> @@ -907,6 +933,10 @@ Scope(_SB)
> {
> Return (RBYV())
> }
> + Method (_PXM, 0, NotSerialized)
> + {
> + Return(0x03)
> + }
> } // Device(PCId)
> Device (RESd)
> {
> diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl
> index 6455130..d5b7e2f 100644
> --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl
> +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl
> @@ -88,7 +88,10 @@ Scope(_SB)
> Store(0x7ffff, CLK)
> Sleep(1)
> }
> -
> + Method (_PXM, 0, NotSerialized)
> + {
> + Return(0x00)
> + }
> Method (_STA, 0, NotSerialized)
> {
> Return (0x0)
> @@ -169,8 +172,15 @@ Scope(_SB)
> Store(0x7ffff, CLK)
> Sleep(1)
> }
> + Method (_PXM, 0, NotSerialized)
> + {
> + Return(0x00)
> + }
> + Method (_STA, 0, NotSerialized)
> + {
> + Return(0x0F)
> + }
> }
> -
> Device(SAS2) {
> Name(_HID, "HISI0162")
> Name(_CCA, 1)
> @@ -244,7 +254,10 @@ Scope(_SB)
> Store(0x7ffff, CLK)
> Sleep(1)
> }
> -
> + Method (_PXM, 0, NotSerialized)
> + {
> + Return(0x00)
> + }
> Method (_STA, 0, NotSerialized)
> {
> Return (0x0)
> --
> 1.9.1
>
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH edk2-platforms v2 05/15] Hisilicon D03/D05: Add capsule upgrade support
2018-01-30 13:21 ` Leif Lindholm
@ 2018-01-31 1:14 ` Huangming (Mark)
0 siblings, 0 replies; 30+ messages in thread
From: Huangming (Mark) @ 2018-01-31 1:14 UTC (permalink / raw)
To: Leif Lindholm
Cc: Ming Huang, linaro-uefi, edk2-devel, graeme.gregory,
ard.biesheuvel, guoheyi, wanghuiqiang, zhangjinsong2, mengfanrong,
huangdaode, waip23
On 2018/1/30 21:21, Leif Lindholm wrote:
> On Tue, Jan 30, 2018 at 08:48:27PM +0800, Huangming (Mark) wrote:
>>
>>
>> On 2018/1/30 3:58, Leif Lindholm wrote:
>>> A few style comments below.
>>>
>>> On Fri, Jan 26, 2018 at 04:00:40PM +0800, Ming Huang wrote:
>>>> From: Jason Zhang <zhangjinsong2@huawei.com>
>>>>
>>>> This module support updating the boot CPU firmware only.
>>>>
>>>> Contributed-under: TianoCore Contribution Agreement 1.1
>>>> Signed-off-by: Jason Zhang <zhangjinsong2@huawei.com>
>>>> Signed-off-by: Ming Huang <huangming23@huawei.com>
>>>> Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
>>>> ---
>>>> Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini | 45 +++++++
>>>> Platform/Hisilicon/D03/D03.dsc | 17 ++-
>>>> Platform/Hisilicon/D03/D03.fdf | 70 +++++++++++
>>>> Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc | 81 +++++++++++++
>>>> Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 50 ++++++++
>>>> Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c | 70 +++++++++++
>>>> Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini | 45 +++++++
>>>> Platform/Hisilicon/D05/D05.dsc | 19 ++-
>>>> Platform/Hisilicon/D05/D05.fdf | 70 +++++++++++
>>>> Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc | 81 +++++++++++++
>>>> Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 50 ++++++++
>>>> Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c | 70 +++++++++++
>>>> Silicon/Hisilicon/Hisilicon.dsc.inc | 11 +-
>>>> Silicon/Hisilicon/Hisilicon.fdf.inc | 9 ++
>>>> Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c | 123 ++++++++++++++++++++
>>>> Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf | 51 ++++++++
>>>> 16 files changed, 859 insertions(+), 3 deletions(-)
>>>>
>>>
>>>> diff --git a/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc b/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
>>>> new file mode 100644
>>>> index 0000000..d9f4a00
>>>> --- /dev/null
>>>> +++ b/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
>>>> @@ -0,0 +1,81 @@
>>>> +/** @file
>>>> + System Firmware descriptor.
>>>> +
>>>> + Copyright (c) 2018, Hisilicon Limited. All rights reserved.
>>>> + Copyright (c) 2018, Linaro Limited. All rights reserved.
>>>> + Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
>>>> +
>>>> + This program and the accompanying materials
>>>> + are licensed and made available under the terms and conditions of the BSD License
>>>> + which accompanies this distribution. The full text of the license may be found at
>>>> + http://opensource.org/licenses/bsd-license.php
>>>> +
>>>> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>>>> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>>>> +
>>>> +**/
>>>> +
>>>> +#include <PiPei.h>
>>>> +#include <Guid/EdkiiSystemFmpCapsule.h>
>>>> +#include <Protocol/FirmwareManagement.h>
>>>> +
>>>> +#define PACKAGE_VERSION 0xFFFFFFFF
>>>> +#define PACKAGE_VERSION_STRING L"Unknown"
>>>> +
>>>> +#define CURRENT_FIRMWARE_VERSION 0x00000002
>>>> +#define CURRENT_FIRMWARE_VERSION_STRING L"0x00000002"
>>>> +#define LOWEST_SUPPORTED_FIRMWARE_VERSION 0x00000001
>>>> +
>>>> +#define IMAGE_ID SIGNATURE_64('H','W','A', 'R', 'M', '_', 'F', 'd')
>>>> +#define IMAGE_ID_STRING L"ARMPlatformFd"
>>>> +
>>>> +// PcdSystemFmpCapsuleImageTypeIdGuid
>>>> +#define IMAGE_TYPE_ID_GUID { 0x44c850f2, 0x85ff, 0x4be5, { 0xbf, 0x34, 0xa5, 0x95, 0x28, 0xdf, 0x22, 0xd3 } }
>>>> +
>>>> +typedef struct {
>>>> + EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR Descriptor;
>>>> + // real string data
>>>> + CHAR16 ImageIdNameStr[sizeof(IMAGE_ID_STRING) / sizeof(CHAR16)];
>>>> + CHAR16 VersionNameStr[sizeof(CURRENT_FIRMWARE_VERSION_STRING) / sizeof(CHAR16)];
>>>> + CHAR16 PackageVersionNameStr[sizeof(PACKAGE_VERSION_STRING) / sizeof(CHAR16)];
>>>
>>> Use ARRAY_SIZE for the 3 above?
>>
>> If use ARRAY_SIZE, the three macro must change to array of CHAR16.
>
> What problem are you encountering when simply replacing
> CHAR16 ImageIdNameStr[sizeof(IMAGE_ID_STRING) / sizeof(CHAR16)];
> with
> CHAR16 ImageIdNameStr[ARRAY_SIZE (IMAGE_ID_STRING)];
> ?
>
In my mind, simply replacing can not be compiled, but actually it works.
I will replace it as your comments.
Thanks,
Ming
>> It is not necessary maybe.The same style is found in
>> SystemFirmwareDescriptor.aslc from other platform,like
>> AMD,Socionext.
>
> Patches welcome.
>
> ARRAY_SIZE was only added to MdePkg in October 2016.
> Ideally, all code should be using this macro, but at least we can try
> to make sure all _new_ code uses it, when we spot missed opportunities.
>
> /
> Leif
>
> .
>
--
Best Regards,
Ming
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH edk2-platforms v2 02/15] Hisilicon/D05: Add PPTT support
2018-01-26 8:00 ` [PATCH edk2-platforms v2 02/15] Hisilicon/D05: Add PPTT support Ming Huang
2018-01-30 14:28 ` graeme.gregory
@ 2018-02-01 1:11 ` Jeremy Linton
2018-02-02 3:42 ` Huangming (Mark)
1 sibling, 1 reply; 30+ messages in thread
From: Jeremy Linton @ 2018-02-01 1:11 UTC (permalink / raw)
To: Ming Huang, leif.lindholm, linaro-uefi, edk2-devel,
graeme.gregory
Cc: huangming23, ard.biesheuvel, zhangjinsong2, wanghuiqiang, guoheyi,
waip23, mengfanrong, huangdaode
Hi,
On 01/26/2018 02:00 AM, Ming Huang wrote:
> Add Processor Properties Topology Table, PPTT include
> Processor hierarchy node, Cache Type Structure and ID structure.
>
> PPTT is needed for lscpu command to show socket information correctly.
> https://bugs.linaro.org/show_bug.cgi?id=3206
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ming Huang <huangming23@huawei.com>
> Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
> ---
> Platform/Hisilicon/D05/D05.dsc | 1 +
> Platform/Hisilicon/D05/D05.fdf | 1 +
> Silicon/Hisilicon/Hi1616/Pptt/Pptt.c | 540 ++++++++++++++++++++
> Silicon/Hisilicon/Hi1616/Pptt/Pptt.h | 88 ++++
> Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf | 48 ++
> 5 files changed, 678 insertions(+)
>
> diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
> index 77a89fd..710339c 100644
> --- a/Platform/Hisilicon/D05/D05.dsc
> +++ b/Platform/Hisilicon/D05/D05.dsc
> @@ -506,6 +506,7 @@
> MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
>
> Silicon/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
> + Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf
> Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
>
> #
> diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf
> index 78ab0c8..97de4d2 100644
> --- a/Platform/Hisilicon/D05/D05.fdf
> +++ b/Platform/Hisilicon/D05/D05.fdf
> @@ -241,6 +241,7 @@ READ_LOCK_STATUS = TRUE
> INF Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
>
> INF RuleOverride=ACPITABLE Silicon/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
> + INF Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf
> INF Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
>
> #
> diff --git a/Silicon/Hisilicon/Hi1616/Pptt/Pptt.c b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.c
> new file mode 100644
> index 0000000..71c456c
> --- /dev/null
> +++ b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.c
> @@ -0,0 +1,540 @@
> +/** @file
> +*
> +* Copyright (c) 2018, Hisilicon Limited. All rights reserved.
> +* Copyright (c) 2018, Linaro Limited. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +* Based on the files under Platform/ARM/JunoPkg/AcpiTables/
> +*
> +**/
> +
> +#include "Pptt.h"
> +
> +EFI_ACPI_TABLE_PROTOCOL *mAcpiTableProtocol = NULL;
> +EFI_ACPI_SDT_PROTOCOL *mAcpiSdtProtocol = NULL;
> +
> +EFI_ACPI_DESCRIPTION_HEADER mPpttHeader =
> + ARM_ACPI_HEADER (
> + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
> + EFI_ACPI_DESCRIPTION_HEADER,
> + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
> + );
> +
> +EFI_ACPI_6_2_PPTT_STRUCTURE_ID mPpttSocketType2[PPTT_SOCKET_COMPONENT_NO] =
> +{
> + {2, sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID), {0, 0}, 0, 0, 0, 0, 0, 0}
> +};
I missed this the first time. I think at a minimum the VENDOR_ID needs
to contain something other than 0 if your populating a type2 structure.
Did I miss it getting overridden somewhere?
Checking the ACPI id, registry there is an existing entry for Hisilicon
Technologies Co.., LTD and its 'HISI'.
I would suggest you use that, and come up with a plan for how the
remaining fields are provided.
> +
> +EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE mPpttCacheType1[PPTT_CACHE_NO];
> +
> +
> +STATIC
> +VOID
> +InitCacheInfo (
> + VOID
> + )
> +{
> + UINT8 Index;
> + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES Type1Attributes;
> + CSSELR_DATA CsselrData;
> + CCSIDR_DATA CcsidrData;
> +
> + for (Index = 0; Index < PPTT_CACHE_NO; Index++) {
> + CsselrData.Data = 0;
> + CcsidrData.Data = 0;
> + SetMem (
> + &Type1Attributes,
> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES),
> + 0
> + );
> +
> + if (Index == 0) { //L1I
> + CsselrData.Bits.InD = 1;
> + CsselrData.Bits.Level = 0;
> + Type1Attributes.CacheType = 1;
> + } else if (Index == 1) {
> + Type1Attributes.CacheType = 0;
> + CsselrData.Bits.Level = Index - 1;
> + } else {
> + Type1Attributes.CacheType = 2;
> + CsselrData.Bits.Level = Index - 1;
> + }
> +
> + CcsidrData.Data = ReadCCSIDR (CsselrData.Data);
> +
> + if (CcsidrData.Bits.Wa == 1) {
> + Type1Attributes.AllocationType = PPTT_TYPE1_ALLOCATION_WRITE;
> + if (CcsidrData.Bits.Ra == 1) {
> + Type1Attributes.AllocationType = PPTT_TYPE1_ALLOCATION_READ_WRITE;
> + }
> + }
> +
> + if (CcsidrData.Bits.Wt == 1) {
> + Type1Attributes.WritePolicy = 1;
> + }
> + DEBUG ((DEBUG_INFO,
> + "[Acpi PPTT] Level = %x!CcsidrData = %x!\n",
> + CsselrData.Bits.Level,
> + CcsidrData.Data));
> +
> + mPpttCacheType1[Index].Type = EFI_ACPI_6_2_PPTT_TYPE_CACHE;
> + mPpttCacheType1[Index].Length = sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE);
> + mPpttCacheType1[Index].Reserved[0] = 0;
> + mPpttCacheType1[Index].Reserved[1] = 0;
> + mPpttCacheType1[Index].Flags.SizePropertyValid = 1;
> + mPpttCacheType1[Index].Flags.NumberOfSetsValid = 1;
> + mPpttCacheType1[Index].Flags.AssociativityValid = 1;
> + mPpttCacheType1[Index].Flags.AllocationTypeValid = 1;
> + mPpttCacheType1[Index].Flags.CacheTypeValid = 1;
> + mPpttCacheType1[Index].Flags.WritePolicyValid = 1;
> + mPpttCacheType1[Index].Flags.LineSizeValid = 1;
> + mPpttCacheType1[Index].Flags.Reserved = 0;
> + mPpttCacheType1[Index].NextLevelOfCache = 0;
> +
> + if (Index != PPTT_CACHE_NO - 1) {
> + mPpttCacheType1[Index].NumberOfSets = (UINT16)CcsidrData.Bits.NumSets + 1;
> + mPpttCacheType1[Index].Associativity = (UINT16)CcsidrData.Bits.Associativity + 1;
> + mPpttCacheType1[Index].LineSize = (UINT16)( 1 << (CcsidrData.Bits.LineSize + 4));
> + mPpttCacheType1[Index].Size = mPpttCacheType1[Index].LineSize * \
> + mPpttCacheType1[Index].Associativity * \
> + mPpttCacheType1[Index].NumberOfSets;
> + CopyMem (
> + &mPpttCacheType1[Index].Attributes,
> + &Type1Attributes,
> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES)
> + );
> + } else {
> + // L3 cache
> + mPpttCacheType1[Index].Size = 0x1000000; // 16m
> + mPpttCacheType1[Index].NumberOfSets = 0x2000;
> + mPpttCacheType1[Index].Associativity = 0x10; // CacheAssociativity16Way
> + SetMem (
> + &mPpttCacheType1[Index].Attributes,
> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES),
> + 0x0A
> + );
> + mPpttCacheType1[Index].LineSize = 0x80; // 128byte
> + }
> + }
> +}
> +
> +STATIC
> +EFI_STATUS
> +AddCoreTable (
> + IN EFI_ACPI_DESCRIPTION_HEADER *PpttTable,
> + IN OUT UINT32 *PpttTableLengthRemain,
> + IN UINT32 Flags,
> + IN UINT32 Parent,
> + IN UINT32 ResourceNo,
> + IN UINT32 ProcessorId
> + )
> +{
> + EFI_ACPI_6_2_PPTT_TYPE0 *PpttType0;
> + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *PpttType1;
> + UINT32 *PrivateResource;
> + UINT8 Index;
> +
> + if (*PpttTableLengthRemain <
> + (sizeof (EFI_ACPI_6_2_PPTT_TYPE0) + ResourceNo * 4)) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> + PpttType0 = (EFI_ACPI_6_2_PPTT_TYPE0 *)((UINT8 *)PpttTable +
> + PpttTable->Length);
> + PpttType0->Type = 0;
> + CopyMem (&PpttType0->Flags, &Flags, sizeof(PpttType0->Flags));;
> + PpttType0->Parent= Parent;
> + PpttType0->AcpiProcessorId = ProcessorId;
> + PpttType0->NumberOfPrivateResources = ResourceNo;
> + PpttType0->Length = sizeof (EFI_ACPI_6_2_PPTT_TYPE0) +
> + ResourceNo * 4;
> +
> + *PpttTableLengthRemain -= (UINTN)PpttType0->Length;
> + PpttTable->Length += PpttType0->Length;
> + PrivateResource = (UINT32 *)((UINT8 *)PpttType0 +
> + sizeof (EFI_ACPI_6_2_PPTT_TYPE0));
> +
> + // Add cache type structure
> + for (Index = 0; Index < ResourceNo; Index++, PrivateResource++) {
> + if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE)) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> + *PrivateResource = PpttTable->Length;
> + PpttType1 = (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *)((UINT8 *)PpttTable +
> + PpttTable->Length);
> + gBS->CopyMem (
> + PpttType1,
> + &mPpttCacheType1[Index],
> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE)
> + );
> + *PpttTableLengthRemain -= PpttType1->Length;
> + PpttTable->Length += PpttType1->Length;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +STATIC
> +EFI_STATUS
> +AddClusterTable (
> + IN EFI_ACPI_DESCRIPTION_HEADER *PpttTable,
> + IN OUT UINT32 *PpttTableLengthRemain,
> + IN UINT32 Flags,
> + IN UINT32 Parent,
> + IN UINT32 ResourceNo
> + )
> +{
> + EFI_ACPI_6_2_PPTT_TYPE0 *PpttType0;
> + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *PpttType1;
> + UINT32 *PrivateResource;
> +
> + if ((*PpttTableLengthRemain) <
> + (sizeof (EFI_ACPI_6_2_PPTT_TYPE0) + ResourceNo * 4)) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> + PpttType0 = (EFI_ACPI_6_2_PPTT_TYPE0 *)((UINT8 *)PpttTable +
> + PpttTable->Length);
> + PpttType0->Type = 0;
> + CopyMem (&PpttType0->Flags, &Flags, sizeof(PpttType0->Flags));;
> + PpttType0->Parent= Parent;
> + PpttType0->NumberOfPrivateResources = ResourceNo;
> + PpttType0->Length = sizeof (EFI_ACPI_6_2_PPTT_TYPE0) +
> + ResourceNo * 4;
> +
> + *PpttTableLengthRemain -= PpttType0->Length;
> + PpttTable->Length += PpttType0->Length;
> + PrivateResource = (UINT32 *)((UINT8 *)PpttType0 +
> + sizeof (EFI_ACPI_6_2_PPTT_TYPE0));
> +
> + // Add cache type structure
> + if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE)) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> + *PrivateResource = PpttTable->Length;
> + PpttType1 = (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *)((UINT8 *)PpttTable +
> + PpttTable->Length);
> + gBS->CopyMem (
> + PpttType1,
> + &mPpttCacheType1[2],
> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE)
> + );
> + *PpttTableLengthRemain -= PpttType1->Length;
> + PpttTable->Length += PpttType1->Length;
> +
> + return EFI_SUCCESS;
> +}
> +
> +STATIC
> +EFI_STATUS
> +AddScclTable (
> + IN EFI_ACPI_DESCRIPTION_HEADER *PpttTable,
> + IN OUT UINT32 *PpttTableLengthRemain,
> + IN UINT32 Flags,
> + IN UINT32 Parent,
> + IN UINT32 ResourceNo
> + )
> +{
> + EFI_ACPI_6_2_PPTT_TYPE0 *PpttType0;
> + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *PpttType1;
> + UINT32 *PrivateResource;
> +
> + if (*PpttTableLengthRemain <
> + (sizeof (EFI_ACPI_6_2_PPTT_TYPE0) + ResourceNo * 4)) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> + PpttType0 = (EFI_ACPI_6_2_PPTT_TYPE0 *)((UINT8 *)PpttTable +
> + PpttTable->Length);
> + PpttType0->Type = 0;
> + CopyMem (&PpttType0->Flags, &Flags, sizeof(PpttType0->Flags));;
> + PpttType0->Parent= Parent;
> + PpttType0->NumberOfPrivateResources = ResourceNo;
> + PpttType0->Length = sizeof (EFI_ACPI_6_2_PPTT_TYPE0) +
> + ResourceNo * 4;
> +
> + *PpttTableLengthRemain -= PpttType0->Length;
> + PpttTable->Length += PpttType0->Length;
> + PrivateResource = (UINT32 *)((UINT8 *)PpttType0 +
> + sizeof (EFI_ACPI_6_2_PPTT_TYPE0));
> +
> + // Add cache type structure
> + if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE)) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> + *PrivateResource = PpttTable->Length;
> + PpttType1 = (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *)((UINT8 *)PpttTable +
> + PpttTable->Length);
> + gBS->CopyMem (
> + PpttType1,
> + &mPpttCacheType1[3],
> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE)
> + );
> + *PpttTableLengthRemain -= PpttType1->Length;
> + PpttTable->Length += PpttType1->Length;
> +
> + return EFI_SUCCESS;
> +}
> +
> +STATIC
> +EFI_STATUS
> +AddSocketTable (
> + IN EFI_ACPI_DESCRIPTION_HEADER *PpttTable,
> + IN OUT UINT32 *PpttTableLengthRemain,
> + IN UINT32 Flags,
> + IN UINT32 Parent,
> + IN UINT32 ResourceNo
> + )
> +{
> + EFI_ACPI_6_2_PPTT_TYPE0 *PpttType0;
> + EFI_ACPI_6_2_PPTT_STRUCTURE_ID *PpttType2;
> + UINT32 *PrivateResource;
> + UINT8 Index;
> +
> + if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_TYPE0)) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> + PpttType0 = (EFI_ACPI_6_2_PPTT_TYPE0 *)((UINT8 *)PpttTable +
> + PpttTable->Length);
> + PpttType0->Type = 0;
> + CopyMem (&PpttType0->Flags, &Flags, sizeof(PpttType0->Flags));;
> + PpttType0->Parent= Parent;
> + PpttType0->NumberOfPrivateResources = ResourceNo;
> + PpttType0->Length = sizeof (EFI_ACPI_6_2_PPTT_TYPE0) +
> + ResourceNo * 4;
> + PpttTable->Length += PpttType0->Length;
> +
> + *PpttTableLengthRemain -= PpttType0->Length;
> + if (*PpttTableLengthRemain < ResourceNo * 4) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> + PrivateResource = (UINT32 *)((UINT8 *)PpttType0 +
> + sizeof (EFI_ACPI_6_2_PPTT_TYPE0));
> + DEBUG ((DEBUG_INFO,
> + "[Acpi PPTT] sizeof(EFI_ACPI_6_2_PPTT_STRUCTURE_ID) = %x!\n",
> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID)));
> +
> + for (Index = 0; Index < ResourceNo; Index++, PrivateResource++) {
> + if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID)) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> + *PrivateResource = PpttTable->Length;
> + PpttType2 = (EFI_ACPI_6_2_PPTT_STRUCTURE_ID *)((UINT8 *)PpttTable +
> + PpttTable->Length);
> + gBS->CopyMem (
> + PpttType2,
> + &mPpttSocketType2[Index],
> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID)
> + );
> + *PpttTableLengthRemain -= PpttType2->Length;
> + PpttTable->Length += PpttType2->Length;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +STATIC
> +VOID
> +GetApic (
> + IN EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE *ApicTable,
> + IN OUT EFI_ACPI_DESCRIPTION_HEADER *PpttTable,
> + IN UINT32 PpttTableLengthRemain,
> + IN UINT32 Index1
> +)
> +{
> + UINT32 IndexSocket, IndexSccl, IndexCluster, IndexCore;
> + UINT32 SocketOffset, ScclOffset, ClusterOffset;
> + UINT32 Parent = 0;
> + UINT32 Flags = 0;
> + UINT32 ResourceNo = 0;
> +
> + // Get APIC data
> + for (IndexSocket = 0; IndexSocket < PPTT_SOCKET_NO; IndexSocket++) {
> + SocketOffset = 0;
> + for (IndexSccl = 0; IndexSccl < PPTT_SCCL_NO; IndexSccl++) {
> + ScclOffset = 0;
> + for (IndexCluster = 0; IndexCluster < PPTT_CLUSTER_NO; IndexCluster++) {
> + ClusterOffset = 0;
> + for (IndexCore = 0; IndexCore < PPTT_CORE_NO; IndexCore++) {
> + if (ApicTable->GicInterfaces[Index1].AcpiProcessorUid != Index1) {
> + // This processor is unusable
> + DEBUG ((DEBUG_ERROR, "[Acpi PPTT] Please check MADT table for UID!\n"));
> + return;
> + }
> + if ((ApicTable->GicInterfaces[Index1].Flags & BIT0) == 0) {
> + // This processor is unusable
> + Index1++;
> + continue;
> + }
> +
> + if (SocketOffset == 0) {
> + // Add socket0 for type0 table
> + ResourceNo = PPTT_SOCKET_COMPONENT_NO;
> + SocketOffset = PpttTable->Length;
> + Parent = 0;
> + Flags = PPTT_TYPE0_SOCKET_FLAG;
> + AddSocketTable (
> + PpttTable,
> + &PpttTableLengthRemain,
> + Flags,
> + Parent,
> + ResourceNo
> + );
> + }
> + if (ScclOffset == 0) {
> + // Add socket0sccl0 for type0 table
> + ResourceNo = 1;
> + ScclOffset = PpttTable->Length;
> + Parent = SocketOffset;
> + Flags = PPTT_TYPE0_SCCL_FLAG;
> + AddScclTable (
> + PpttTable,
> + &PpttTableLengthRemain,
> + Flags,
> + Parent,
> + ResourceNo
> + );
> + }
> + if (ClusterOffset == 0) {
> + // Add socket0sccl0ClusterId for type0 table
> + ResourceNo = 1;
> + ClusterOffset = PpttTable->Length ;
> + Parent = ScclOffset;
> + Flags = PPTT_TYPE0_CLUSTER_FLAG;
> + AddClusterTable (
> + PpttTable,
> + &PpttTableLengthRemain,
> + Flags,
> + Parent,
> + ResourceNo
> + );
> + }
> +
> + // Add socket0sccl0ClusterIdCoreId for type0 table
> + ResourceNo = 2;
> + Parent = ClusterOffset;
> + Flags = PPTT_TYPE0_CORE_FLAG;
> + AddCoreTable (
> + PpttTable,
> + &PpttTableLengthRemain,
> + Flags,
> + Parent,
> + ResourceNo,
> + Index1
> + );
> +
> + Index1++;
> + }
> + }
> + }
> + }
> + return ;
> +}
> +
> +STATIC
> +VOID
> +PpttSetAcpiTable (
> + IN EFI_EVENT Event,
> + IN VOID *Context
> + )
> +{
> + UINTN AcpiTableHandle;
> + EFI_STATUS Status;
> + UINT8 Checksum;
> + EFI_ACPI_SDT_HEADER *Table;
> + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE *ApicTable;
> + EFI_ACPI_TABLE_VERSION TableVersion;
> + EFI_ACPI_DESCRIPTION_HEADER *PpttTable;
> + UINTN TableKey;
> + UINT32 Index0, Index1;
> + UINT32 PpttTableLengthRemain = 0;
> +
> + gBS->CloseEvent (Event);
> +
> + InitCacheInfo ();
> +
> + PpttTable = (EFI_ACPI_DESCRIPTION_HEADER *)AllocateZeroPool (PPTT_TABLE_MAX_LEN);
> + gBS->CopyMem (
> + (VOID *)PpttTable,
> + &mPpttHeader,
> + sizeof (EFI_ACPI_DESCRIPTION_HEADER)
> + );
> + PpttTableLengthRemain = PPTT_TABLE_MAX_LEN - sizeof (EFI_ACPI_DESCRIPTION_HEADER);
> +
> + for (Index0 = 0; Index0 < EFI_ACPI_MAX_NUM_TABLES; Index0++) {
> + Status = mAcpiSdtProtocol->GetAcpiTable (
> + Index0,
> + &Table,
> + &TableVersion,
> + &TableKey
> + );
> + if (EFI_ERROR (Status)) {
> + break;
> + }
> +
> + // Find APIC table
> + if (Table->Signature == EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE) {
> + break;
> + }
> +
> + }
> +
> + if (!EFI_ERROR (Status) && (Index0 != EFI_ACPI_MAX_NUM_TABLES)) {
> + ApicTable = (EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE *)Table;
> + Index1 = 0;
> +
> + GetApic (ApicTable, PpttTable, PpttTableLengthRemain, Index1);
> +
> + Checksum = CalculateCheckSum8 ((UINT8 *)(PpttTable), PpttTable->Length);
> + PpttTable->Checksum = Checksum;
> +
> + AcpiTableHandle = 0;
> + Status = mAcpiTableProtocol->InstallAcpiTable (
> + mAcpiTableProtocol,
> + PpttTable,
> + PpttTable->Length,
> + &AcpiTableHandle);
> + }
> +
> + FreePool (PpttTable);
> + return ;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +PpttEntryPoint(
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> + EFI_EVENT ReadyToBootEvent;
> +
> + Status = gBS->LocateProtocol (
> + &gEfiAcpiTableProtocolGuid,
> + NULL,
> + (VOID **)&mAcpiTableProtocol);
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = gBS->LocateProtocol (
> + &gEfiAcpiSdtProtocolGuid,
> + NULL,
> + (VOID **)&mAcpiSdtProtocol);
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = EfiCreateEventReadyToBootEx (
> + TPL_NOTIFY,
> + PpttSetAcpiTable,
> + NULL,
> + &ReadyToBootEvent
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + DEBUG ((DEBUG_INFO, "Acpi Pptt init done.\n"));
> +
> + return Status;
> +}
> diff --git a/Silicon/Hisilicon/Hi1616/Pptt/Pptt.h b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.h
> new file mode 100644
> index 0000000..57f8386
> --- /dev/null
> +++ b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.h
> @@ -0,0 +1,88 @@
> +/** @file
> +*
> +* Copyright (c) 2018, Hisilicon Limited. All rights reserved.
> +* Copyright (c) 2018, Linaro Limited. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +* Based on the files under Platform/ARM/JunoPkg/AcpiTables/
> +*
> +**/
> +
> +#ifndef _PPTT_H_
> +#define _PPTT_H_
> +
> +#include <IndustryStandard/Acpi.h>
> +#include <Library/ArmLib/ArmLibPrivate.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/UefiLib.h>
> +#include <Protocol/AcpiSystemDescriptionTable.h>
> +#include <Protocol/AcpiTable.h>
> +#include "../D05AcpiTables/Hi1616Platform.h"
> +
> +#define EFI_ACPI_MAX_NUM_TABLES 20
> +
> +#define PPTT_TABLE_MAX_LEN 0x6000
> +#define PPTT_SOCKET_NO 0x2
> +#define PPTT_SCCL_NO 0x2
> +#define PPTT_CLUSTER_NO 0x4
> +#define PPTT_CORE_NO 0x4
> +#define PPTT_SOCKET_COMPONENT_NO 0x1
> +#define PPTT_CACHE_NO 0x4
> +
> +#define PPTT_TYPE0_PHYSICAL_PKG BIT0
> +#define PPTT_TYPE0_PROCESSORID_VALID BIT1
I think these two flags belong in the acpi header file.. That said they
are already defined by the bitfields in
EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR_FLAGS so it might be a good idea
to just remove them and convert the following definitions to the struct.
That said, its a bit ugly either way, so your choice.
> +#define PPTT_TYPE0_SOCKET_FLAG PPTT_TYPE0_PHYSICAL_PKG
> +#define PPTT_TYPE0_SCCL_FLAG 0
> +#define PPTT_TYPE0_CLUSTER_FLAG 0
> +#define PPTT_TYPE0_CORE_FLAG PPTT_TYPE0_PROCESSORID_VALID
> +
> +#define PPTT_TYPE1_ALLOCATION_WRITE 0x1
> +#define PPTT_TYPE1_ALLOCATION_READ_WRITE 0x2
Its more clear for these two, they should be in the acpi header file.
While your at it the write policy and cache type should also probably be
defined and used in your init routing.
> +
> +typedef union {
> + struct {
> + UINT32 InD :1;
> + UINT32 Level :3;
> + UINT32 Reserved :28;
> + } Bits;
> + UINT32 Data;
> +} CSSELR_DATA;
> +
> +typedef union {
> + struct {
> + UINT32 LineSize :3;
> + UINT32 Associativity :10;
> + UINT32 NumSets :15;
> + UINT32 Wa :1;
> + UINT32 Ra :1;
> + UINT32 Wb :1;
> + UINT32 Wt :1;
> + } Bits;
> + UINT32 Data;
> +} CCSIDR_DATA;
This feels like it belongs in a diffrent header file closer to the
ReadCCISDR() function (ArmLibPrivate.h).
> +
> +//
> +// Processor Hierarchy Node Structure
> +//
> +typedef struct {
> + UINT8 Type;
> + UINT8 Length;
> + UINT8 Reserved[2];
> + UINT32 Flags;
> + UINT32 Parent;
> + UINT32 AcpiProcessorId;
> + UINT32 NumberOfPrivateResources;
> +} EFI_ACPI_6_2_PPTT_TYPE0;
This belongs in the common ACPI header too.
> +
> +#endif // _PPTT_H_
> +
> diff --git a/Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf
> new file mode 100644
> index 0000000..ff6f772
> --- /dev/null
> +++ b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf
> @@ -0,0 +1,48 @@
> +/** @file
> +*
> +* Copyright (c) 2018, Hisilicon Limited. All rights reserved.
> +* Copyright (c) 2018, Linaro Limited. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +* Based on the files under Platform/ARM/JunoPkg/AcpiTables/
> +*
> +**/
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = AcpiPptt
> + FILE_GUID = AAB14F90-DC2E-4f33-A594-C7894A5B412D
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + ENTRY_POINT = PpttEntryPoint
> +
> +[Sources.common]
> + Pptt.c
> +
> +[Packages]
> + ArmPkg/ArmPkg.dec
> + MdePkg/MdePkg.dec
> + Silicon/Hisilicon/HisiPkg.dec
> +
> +[LibraryClasses]
> + ArmLib
> + BaseMemoryLib
> + DebugLib
> + HobLib
> + UefiDriverEntryPoint
> + UefiRuntimeServicesTableLib
> +
> +[Protocols]
> + gEfiAcpiSdtProtocolGuid ## PROTOCOL ALWAYS_CONSUMED
> + gEfiAcpiTableProtocolGuid ## PROTOCOL ALWAYS_CONSUMED
> +
> +[Depex]
> + gEfiAcpiTableProtocolGuid AND gEfiAcpiSdtProtocolGuid
> +
>
Ok, so other than the above comments i'm pretty happy with it. IMHO the
largest problem is the Type2 id definition which definitly needs to be
'HISI'.
Reveiwed-by: Jeremy Linton <jeremy.linton@arm.com>
Generally, I think this is a pretty good way to build the table. Enough
so, that the next person to do an arm PPTT implementation should make an
effort to move some of your helper functions (InitCacheInfo, Add*
routines) into a generic library and tweak them enough that they can be
resused across multiple platforms.
Thanks,
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH edk2-platforms v2 02/15] Hisilicon/D05: Add PPTT support
2018-02-01 1:11 ` Jeremy Linton
@ 2018-02-02 3:42 ` Huangming (Mark)
2018-02-02 16:17 ` Jeremy Linton
0 siblings, 1 reply; 30+ messages in thread
From: Huangming (Mark) @ 2018-02-02 3:42 UTC (permalink / raw)
To: Jeremy Linton, Ming Huang, leif.lindholm, linaro-uefi, edk2-devel,
graeme.gregory
Cc: ard.biesheuvel, zhangjinsong2, wanghuiqiang, guoheyi, waip23,
mengfanrong, huangdaode
On 2018/2/1 9:11, Jeremy Linton wrote:
> Hi,
>
>
> On 01/26/2018 02:00 AM, Ming Huang wrote:
>> Add Processor Properties Topology Table, PPTT include
>> Processor hierarchy node, Cache Type Structure and ID structure.
>>
>> PPTT is needed for lscpu command to show socket information correctly.
>> https://bugs.linaro.org/show_bug.cgi?id=3206
>>
>> Contributed-under: TianoCore Contribution Agreement 1.1
>> Signed-off-by: Ming Huang <huangming23@huawei.com>
>> Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
>> ---
>> Platform/Hisilicon/D05/D05.dsc | 1 +
>> Platform/Hisilicon/D05/D05.fdf | 1 +
>> Silicon/Hisilicon/Hi1616/Pptt/Pptt.c | 540 ++++++++++++++++++++
>> Silicon/Hisilicon/Hi1616/Pptt/Pptt.h | 88 ++++
>> Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf | 48 ++
>> 5 files changed, 678 insertions(+)
>>
>> diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
>> index 77a89fd..710339c 100644
>> --- a/Platform/Hisilicon/D05/D05.dsc
>> +++ b/Platform/Hisilicon/D05/D05.dsc
>> @@ -506,6 +506,7 @@
>> MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
>> Silicon/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
>> + Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf
>> Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
>> #
>> diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf
>> index 78ab0c8..97de4d2 100644
>> --- a/Platform/Hisilicon/D05/D05.fdf
>> +++ b/Platform/Hisilicon/D05/D05.fdf
>> @@ -241,6 +241,7 @@ READ_LOCK_STATUS = TRUE
>> INF Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
>> INF RuleOverride=ACPITABLE Silicon/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
>> + INF Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf
>> INF Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
>> #
>> diff --git a/Silicon/Hisilicon/Hi1616/Pptt/Pptt.c b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.c
>> new file mode 100644
>> index 0000000..71c456c
>> --- /dev/null
>> +++ b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.c
>> @@ -0,0 +1,540 @@
>> +/** @file
>> +*
>> +* Copyright (c) 2018, Hisilicon Limited. All rights reserved.
>> +* Copyright (c) 2018, Linaro Limited. All rights reserved.
>> +*
>> +* This program and the accompanying materials
>> +* are licensed and made available under the terms and conditions of the BSD License
>> +* which accompanies this distribution. The full text of the license may be found at
>> +* http://opensource.org/licenses/bsd-license.php
>> +*
>> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +*
>> +* Based on the files under Platform/ARM/JunoPkg/AcpiTables/
>> +*
>> +**/
>> +
>> +#include "Pptt.h"
>> +
>> +EFI_ACPI_TABLE_PROTOCOL *mAcpiTableProtocol = NULL;
>> +EFI_ACPI_SDT_PROTOCOL *mAcpiSdtProtocol = NULL;
>> +
>> +EFI_ACPI_DESCRIPTION_HEADER mPpttHeader =
>> + ARM_ACPI_HEADER (
>> + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
>> + EFI_ACPI_DESCRIPTION_HEADER,
>> + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
>> + );
>> +
>> +EFI_ACPI_6_2_PPTT_STRUCTURE_ID mPpttSocketType2[PPTT_SOCKET_COMPONENT_NO] =
>> +{
>> + {2, sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID), {0, 0}, 0, 0, 0, 0, 0, 0}
>> +};
>
> I missed this the first time. I think at a minimum the VENDOR_ID needs to contain something other than 0 if your populating a type2 structure. Did I miss it getting overridden somewhere?
>
> Checking the ACPI id, registry there is an existing entry for Hisilicon Technologies Co.., LTD and its 'HISI'.
>
> I would suggest you use that, and come up with a plan for how the remaining fields are provided.
>
>
VENDOR_ID uses the value of 'HISI', there is no a appropriate value for remaining fields now.
>> +
>> +EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE mPpttCacheType1[PPTT_CACHE_NO];
>> +
>> +
>> +STATIC
>> +VOID
>> +InitCacheInfo (
>> + VOID
>> + )
>> +{
>> + UINT8 Index;
>> + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES Type1Attributes;
>> + CSSELR_DATA CsselrData;
>> + CCSIDR_DATA CcsidrData;
>> +
>> + for (Index = 0; Index < PPTT_CACHE_NO; Index++) {
>> + CsselrData.Data = 0;
>> + CcsidrData.Data = 0;
>> + SetMem (
>> + &Type1Attributes,
>> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES),
>> + 0
>> + );
>> +
>> + if (Index == 0) { //L1I
>> + CsselrData.Bits.InD = 1;
>> + CsselrData.Bits.Level = 0;
>> + Type1Attributes.CacheType = 1;
>> + } else if (Index == 1) {
>> + Type1Attributes.CacheType = 0;
>> + CsselrData.Bits.Level = Index - 1;
>> + } else {
>> + Type1Attributes.CacheType = 2;
>> + CsselrData.Bits.Level = Index - 1;
>> + }
>> +
>> + CcsidrData.Data = ReadCCSIDR (CsselrData.Data);
>> +
>> + if (CcsidrData.Bits.Wa == 1) {
>> + Type1Attributes.AllocationType = PPTT_TYPE1_ALLOCATION_WRITE;
>> + if (CcsidrData.Bits.Ra == 1) {
>> + Type1Attributes.AllocationType = PPTT_TYPE1_ALLOCATION_READ_WRITE;
>> + }
>> + }
>> +
>> + if (CcsidrData.Bits.Wt == 1) {
>> + Type1Attributes.WritePolicy = 1;
>> + }
>> + DEBUG ((DEBUG_INFO,
>> + "[Acpi PPTT] Level = %x!CcsidrData = %x!\n",
>> + CsselrData.Bits.Level,
>> + CcsidrData.Data));
>> +
>> + mPpttCacheType1[Index].Type = EFI_ACPI_6_2_PPTT_TYPE_CACHE;
>> + mPpttCacheType1[Index].Length = sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE);
>> + mPpttCacheType1[Index].Reserved[0] = 0;
>> + mPpttCacheType1[Index].Reserved[1] = 0;
>> + mPpttCacheType1[Index].Flags.SizePropertyValid = 1;
>> + mPpttCacheType1[Index].Flags.NumberOfSetsValid = 1;
>> + mPpttCacheType1[Index].Flags.AssociativityValid = 1;
>> + mPpttCacheType1[Index].Flags.AllocationTypeValid = 1;
>> + mPpttCacheType1[Index].Flags.CacheTypeValid = 1;
>> + mPpttCacheType1[Index].Flags.WritePolicyValid = 1;
>> + mPpttCacheType1[Index].Flags.LineSizeValid = 1;
>> + mPpttCacheType1[Index].Flags.Reserved = 0;
>> + mPpttCacheType1[Index].NextLevelOfCache = 0;
>> +
>> + if (Index != PPTT_CACHE_NO - 1) {
>> + mPpttCacheType1[Index].NumberOfSets = (UINT16)CcsidrData.Bits.NumSets + 1;
>> + mPpttCacheType1[Index].Associativity = (UINT16)CcsidrData.Bits.Associativity + 1;
>> + mPpttCacheType1[Index].LineSize = (UINT16)( 1 << (CcsidrData.Bits.LineSize + 4));
>> + mPpttCacheType1[Index].Size = mPpttCacheType1[Index].LineSize * \
>> + mPpttCacheType1[Index].Associativity * \
>> + mPpttCacheType1[Index].NumberOfSets;
>> + CopyMem (
>> + &mPpttCacheType1[Index].Attributes,
>> + &Type1Attributes,
>> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES)
>> + );
>> + } else {
>> + // L3 cache
>> + mPpttCacheType1[Index].Size = 0x1000000; // 16m
>> + mPpttCacheType1[Index].NumberOfSets = 0x2000;
>> + mPpttCacheType1[Index].Associativity = 0x10; // CacheAssociativity16Way
>> + SetMem (
>> + &mPpttCacheType1[Index].Attributes,
>> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES),
>> + 0x0A
>> + );
>> + mPpttCacheType1[Index].LineSize = 0x80; // 128byte
>> + }
>> + }
>> +}
>> +
>> +STATIC
>> +EFI_STATUS
>> +AddCoreTable (
>> + IN EFI_ACPI_DESCRIPTION_HEADER *PpttTable,
>> + IN OUT UINT32 *PpttTableLengthRemain,
>> + IN UINT32 Flags,
>> + IN UINT32 Parent,
>> + IN UINT32 ResourceNo,
>> + IN UINT32 ProcessorId
>> + )
>> +{
>> + EFI_ACPI_6_2_PPTT_TYPE0 *PpttType0;
>> + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *PpttType1;
>> + UINT32 *PrivateResource;
>> + UINT8 Index;
>> +
>> + if (*PpttTableLengthRemain <
>> + (sizeof (EFI_ACPI_6_2_PPTT_TYPE0) + ResourceNo * 4)) {
>> + return EFI_OUT_OF_RESOURCES;
>> + }
>> + PpttType0 = (EFI_ACPI_6_2_PPTT_TYPE0 *)((UINT8 *)PpttTable +
>> + PpttTable->Length);
>> + PpttType0->Type = 0;
>> + CopyMem (&PpttType0->Flags, &Flags, sizeof(PpttType0->Flags));;
>> + PpttType0->Parent= Parent;
>> + PpttType0->AcpiProcessorId = ProcessorId;
>> + PpttType0->NumberOfPrivateResources = ResourceNo;
>> + PpttType0->Length = sizeof (EFI_ACPI_6_2_PPTT_TYPE0) +
>> + ResourceNo * 4;
>> +
>> + *PpttTableLengthRemain -= (UINTN)PpttType0->Length;
>> + PpttTable->Length += PpttType0->Length;
>> + PrivateResource = (UINT32 *)((UINT8 *)PpttType0 +
>> + sizeof (EFI_ACPI_6_2_PPTT_TYPE0));
>> +
>> + // Add cache type structure
>> + for (Index = 0; Index < ResourceNo; Index++, PrivateResource++) {
>> + if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE)) {
>> + return EFI_OUT_OF_RESOURCES;
>> + }
>> + *PrivateResource = PpttTable->Length;
>> + PpttType1 = (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *)((UINT8 *)PpttTable +
>> + PpttTable->Length);
>> + gBS->CopyMem (
>> + PpttType1,
>> + &mPpttCacheType1[Index],
>> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE)
>> + );
>> + *PpttTableLengthRemain -= PpttType1->Length;
>> + PpttTable->Length += PpttType1->Length;
>> + }
>> +
>> + return EFI_SUCCESS;
>> +}
>> +
>> +STATIC
>> +EFI_STATUS
>> +AddClusterTable (
>> + IN EFI_ACPI_DESCRIPTION_HEADER *PpttTable,
>> + IN OUT UINT32 *PpttTableLengthRemain,
>> + IN UINT32 Flags,
>> + IN UINT32 Parent,
>> + IN UINT32 ResourceNo
>> + )
>> +{
>> + EFI_ACPI_6_2_PPTT_TYPE0 *PpttType0;
>> + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *PpttType1;
>> + UINT32 *PrivateResource;
>> +
>> + if ((*PpttTableLengthRemain) <
>> + (sizeof (EFI_ACPI_6_2_PPTT_TYPE0) + ResourceNo * 4)) {
>> + return EFI_OUT_OF_RESOURCES;
>> + }
>> + PpttType0 = (EFI_ACPI_6_2_PPTT_TYPE0 *)((UINT8 *)PpttTable +
>> + PpttTable->Length);
>> + PpttType0->Type = 0;
>> + CopyMem (&PpttType0->Flags, &Flags, sizeof(PpttType0->Flags));;
>> + PpttType0->Parent= Parent;
>> + PpttType0->NumberOfPrivateResources = ResourceNo;
>> + PpttType0->Length = sizeof (EFI_ACPI_6_2_PPTT_TYPE0) +
>> + ResourceNo * 4;
>> +
>> + *PpttTableLengthRemain -= PpttType0->Length;
>> + PpttTable->Length += PpttType0->Length;
>> + PrivateResource = (UINT32 *)((UINT8 *)PpttType0 +
>> + sizeof (EFI_ACPI_6_2_PPTT_TYPE0));
>> +
>> + // Add cache type structure
>> + if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE)) {
>> + return EFI_OUT_OF_RESOURCES;
>> + }
>> + *PrivateResource = PpttTable->Length;
>> + PpttType1 = (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *)((UINT8 *)PpttTable +
>> + PpttTable->Length);
>> + gBS->CopyMem (
>> + PpttType1,
>> + &mPpttCacheType1[2],
>> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE)
>> + );
>> + *PpttTableLengthRemain -= PpttType1->Length;
>> + PpttTable->Length += PpttType1->Length;
>> +
>> + return EFI_SUCCESS;
>> +}
>> +
>> +STATIC
>> +EFI_STATUS
>> +AddScclTable (
>> + IN EFI_ACPI_DESCRIPTION_HEADER *PpttTable,
>> + IN OUT UINT32 *PpttTableLengthRemain,
>> + IN UINT32 Flags,
>> + IN UINT32 Parent,
>> + IN UINT32 ResourceNo
>> + )
>> +{
>> + EFI_ACPI_6_2_PPTT_TYPE0 *PpttType0;
>> + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *PpttType1;
>> + UINT32 *PrivateResource;
>> +
>> + if (*PpttTableLengthRemain <
>> + (sizeof (EFI_ACPI_6_2_PPTT_TYPE0) + ResourceNo * 4)) {
>> + return EFI_OUT_OF_RESOURCES;
>> + }
>> + PpttType0 = (EFI_ACPI_6_2_PPTT_TYPE0 *)((UINT8 *)PpttTable +
>> + PpttTable->Length);
>> + PpttType0->Type = 0;
>> + CopyMem (&PpttType0->Flags, &Flags, sizeof(PpttType0->Flags));;
>> + PpttType0->Parent= Parent;
>> + PpttType0->NumberOfPrivateResources = ResourceNo;
>> + PpttType0->Length = sizeof (EFI_ACPI_6_2_PPTT_TYPE0) +
>> + ResourceNo * 4;
>> +
>> + *PpttTableLengthRemain -= PpttType0->Length;
>> + PpttTable->Length += PpttType0->Length;
>> + PrivateResource = (UINT32 *)((UINT8 *)PpttType0 +
>> + sizeof (EFI_ACPI_6_2_PPTT_TYPE0));
>> +
>> + // Add cache type structure
>> + if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE)) {
>> + return EFI_OUT_OF_RESOURCES;
>> + }
>> + *PrivateResource = PpttTable->Length;
>> + PpttType1 = (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *)((UINT8 *)PpttTable +
>> + PpttTable->Length);
>> + gBS->CopyMem (
>> + PpttType1,
>> + &mPpttCacheType1[3],
>> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE)
>> + );
>> + *PpttTableLengthRemain -= PpttType1->Length;
>> + PpttTable->Length += PpttType1->Length;
>> +
>> + return EFI_SUCCESS;
>> +}
>> +
>> +STATIC
>> +EFI_STATUS
>> +AddSocketTable (
>> + IN EFI_ACPI_DESCRIPTION_HEADER *PpttTable,
>> + IN OUT UINT32 *PpttTableLengthRemain,
>> + IN UINT32 Flags,
>> + IN UINT32 Parent,
>> + IN UINT32 ResourceNo
>> + )
>> +{
>> + EFI_ACPI_6_2_PPTT_TYPE0 *PpttType0;
>> + EFI_ACPI_6_2_PPTT_STRUCTURE_ID *PpttType2;
>> + UINT32 *PrivateResource;
>> + UINT8 Index;
>> +
>> + if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_TYPE0)) {
>> + return EFI_OUT_OF_RESOURCES;
>> + }
>> + PpttType0 = (EFI_ACPI_6_2_PPTT_TYPE0 *)((UINT8 *)PpttTable +
>> + PpttTable->Length);
>> + PpttType0->Type = 0;
>> + CopyMem (&PpttType0->Flags, &Flags, sizeof(PpttType0->Flags));;
>> + PpttType0->Parent= Parent;
>> + PpttType0->NumberOfPrivateResources = ResourceNo;
>> + PpttType0->Length = sizeof (EFI_ACPI_6_2_PPTT_TYPE0) +
>> + ResourceNo * 4;
>> + PpttTable->Length += PpttType0->Length;
>> +
>> + *PpttTableLengthRemain -= PpttType0->Length;
>> + if (*PpttTableLengthRemain < ResourceNo * 4) {
>> + return EFI_OUT_OF_RESOURCES;
>> + }
>> + PrivateResource = (UINT32 *)((UINT8 *)PpttType0 +
>> + sizeof (EFI_ACPI_6_2_PPTT_TYPE0));
>> + DEBUG ((DEBUG_INFO,
>> + "[Acpi PPTT] sizeof(EFI_ACPI_6_2_PPTT_STRUCTURE_ID) = %x!\n",
>> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID)));
>> +
>> + for (Index = 0; Index < ResourceNo; Index++, PrivateResource++) {
>> + if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID)) {
>> + return EFI_OUT_OF_RESOURCES;
>> + }
>> + *PrivateResource = PpttTable->Length;
>> + PpttType2 = (EFI_ACPI_6_2_PPTT_STRUCTURE_ID *)((UINT8 *)PpttTable +
>> + PpttTable->Length);
>> + gBS->CopyMem (
>> + PpttType2,
>> + &mPpttSocketType2[Index],
>> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID)
>> + );
>> + *PpttTableLengthRemain -= PpttType2->Length;
>> + PpttTable->Length += PpttType2->Length;
>> + }
>> +
>> + return EFI_SUCCESS;
>> +}
>> +
>> +STATIC
>> +VOID
>> +GetApic (
>> + IN EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE *ApicTable,
>> + IN OUT EFI_ACPI_DESCRIPTION_HEADER *PpttTable,
>> + IN UINT32 PpttTableLengthRemain,
>> + IN UINT32 Index1
>> +)
>> +{
>> + UINT32 IndexSocket, IndexSccl, IndexCluster, IndexCore;
>> + UINT32 SocketOffset, ScclOffset, ClusterOffset;
>> + UINT32 Parent = 0;
>> + UINT32 Flags = 0;
>> + UINT32 ResourceNo = 0;
>> +
>> + // Get APIC data
>> + for (IndexSocket = 0; IndexSocket < PPTT_SOCKET_NO; IndexSocket++) {
>> + SocketOffset = 0;
>> + for (IndexSccl = 0; IndexSccl < PPTT_SCCL_NO; IndexSccl++) {
>> + ScclOffset = 0;
>> + for (IndexCluster = 0; IndexCluster < PPTT_CLUSTER_NO; IndexCluster++) {
>> + ClusterOffset = 0;
>> + for (IndexCore = 0; IndexCore < PPTT_CORE_NO; IndexCore++) {
>> + if (ApicTable->GicInterfaces[Index1].AcpiProcessorUid != Index1) {
>> + // This processor is unusable
>> + DEBUG ((DEBUG_ERROR, "[Acpi PPTT] Please check MADT table for UID!\n"));
>> + return;
>> + }
>> + if ((ApicTable->GicInterfaces[Index1].Flags & BIT0) == 0) {
>> + // This processor is unusable
>> + Index1++;
>> + continue;
>> + }
>> +
>> + if (SocketOffset == 0) {
>> + // Add socket0 for type0 table
>> + ResourceNo = PPTT_SOCKET_COMPONENT_NO;
>> + SocketOffset = PpttTable->Length;
>> + Parent = 0;
>> + Flags = PPTT_TYPE0_SOCKET_FLAG;
>> + AddSocketTable (
>> + PpttTable,
>> + &PpttTableLengthRemain,
>> + Flags,
>> + Parent,
>> + ResourceNo
>> + );
>> + }
>> + if (ScclOffset == 0) {
>> + // Add socket0sccl0 for type0 table
>> + ResourceNo = 1;
>> + ScclOffset = PpttTable->Length;
>> + Parent = SocketOffset;
>> + Flags = PPTT_TYPE0_SCCL_FLAG;
>> + AddScclTable (
>> + PpttTable,
>> + &PpttTableLengthRemain,
>> + Flags,
>> + Parent,
>> + ResourceNo
>> + );
>> + }
>> + if (ClusterOffset == 0) {
>> + // Add socket0sccl0ClusterId for type0 table
>> + ResourceNo = 1;
>> + ClusterOffset = PpttTable->Length ;
>> + Parent = ScclOffset;
>> + Flags = PPTT_TYPE0_CLUSTER_FLAG;
>> + AddClusterTable (
>> + PpttTable,
>> + &PpttTableLengthRemain,
>> + Flags,
>> + Parent,
>> + ResourceNo
>> + );
>> + }
>> +
>> + // Add socket0sccl0ClusterIdCoreId for type0 table
>> + ResourceNo = 2;
>> + Parent = ClusterOffset;
>> + Flags = PPTT_TYPE0_CORE_FLAG;
>> + AddCoreTable (
>> + PpttTable,
>> + &PpttTableLengthRemain,
>> + Flags,
>> + Parent,
>> + ResourceNo,
>> + Index1
>> + );
>> +
>> + Index1++;
>> + }
>> + }
>> + }
>> + }
>> + return ;
>> +}
>> +
>> +STATIC
>> +VOID
>> +PpttSetAcpiTable (
>> + IN EFI_EVENT Event,
>> + IN VOID *Context
>> + )
>> +{
>> + UINTN AcpiTableHandle;
>> + EFI_STATUS Status;
>> + UINT8 Checksum;
>> + EFI_ACPI_SDT_HEADER *Table;
>> + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE *ApicTable;
>> + EFI_ACPI_TABLE_VERSION TableVersion;
>> + EFI_ACPI_DESCRIPTION_HEADER *PpttTable;
>> + UINTN TableKey;
>> + UINT32 Index0, Index1;
>> + UINT32 PpttTableLengthRemain = 0;
>> +
>> + gBS->CloseEvent (Event);
>> +
>> + InitCacheInfo ();
>> +
>> + PpttTable = (EFI_ACPI_DESCRIPTION_HEADER *)AllocateZeroPool (PPTT_TABLE_MAX_LEN);
>> + gBS->CopyMem (
>> + (VOID *)PpttTable,
>> + &mPpttHeader,
>> + sizeof (EFI_ACPI_DESCRIPTION_HEADER)
>> + );
>> + PpttTableLengthRemain = PPTT_TABLE_MAX_LEN - sizeof (EFI_ACPI_DESCRIPTION_HEADER);
>> +
>> + for (Index0 = 0; Index0 < EFI_ACPI_MAX_NUM_TABLES; Index0++) {
>> + Status = mAcpiSdtProtocol->GetAcpiTable (
>> + Index0,
>> + &Table,
>> + &TableVersion,
>> + &TableKey
>> + );
>> + if (EFI_ERROR (Status)) {
>> + break;
>> + }
>> +
>> + // Find APIC table
>> + if (Table->Signature == EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE) {
>> + break;
>> + }
>> +
>> + }
>> +
>> + if (!EFI_ERROR (Status) && (Index0 != EFI_ACPI_MAX_NUM_TABLES)) {
>> + ApicTable = (EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE *)Table;
>> + Index1 = 0;
>> +
>> + GetApic (ApicTable, PpttTable, PpttTableLengthRemain, Index1);
>> +
>> + Checksum = CalculateCheckSum8 ((UINT8 *)(PpttTable), PpttTable->Length);
>> + PpttTable->Checksum = Checksum;
>> +
>> + AcpiTableHandle = 0;
>> + Status = mAcpiTableProtocol->InstallAcpiTable (
>> + mAcpiTableProtocol,
>> + PpttTable,
>> + PpttTable->Length,
>> + &AcpiTableHandle);
>> + }
>> +
>> + FreePool (PpttTable);
>> + return ;
>> +}
>> +
>> +EFI_STATUS
>> +EFIAPI
>> +PpttEntryPoint(
>> + IN EFI_HANDLE ImageHandle,
>> + IN EFI_SYSTEM_TABLE *SystemTable
>> + )
>> +{
>> + EFI_STATUS Status;
>> + EFI_EVENT ReadyToBootEvent;
>> +
>> + Status = gBS->LocateProtocol (
>> + &gEfiAcpiTableProtocolGuid,
>> + NULL,
>> + (VOID **)&mAcpiTableProtocol);
>> + ASSERT_EFI_ERROR (Status);
>> +
>> + Status = gBS->LocateProtocol (
>> + &gEfiAcpiSdtProtocolGuid,
>> + NULL,
>> + (VOID **)&mAcpiSdtProtocol);
>> + ASSERT_EFI_ERROR (Status);
>> +
>> + Status = EfiCreateEventReadyToBootEx (
>> + TPL_NOTIFY,
>> + PpttSetAcpiTable,
>> + NULL,
>> + &ReadyToBootEvent
>> + );
>> + ASSERT_EFI_ERROR (Status);
>> +
>> + DEBUG ((DEBUG_INFO, "Acpi Pptt init done.\n"));
>> +
>> + return Status;
>> +}
>> diff --git a/Silicon/Hisilicon/Hi1616/Pptt/Pptt.h b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.h
>> new file mode 100644
>> index 0000000..57f8386
>> --- /dev/null
>> +++ b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.h
>> @@ -0,0 +1,88 @@
>> +/** @file
>> +*
>> +* Copyright (c) 2018, Hisilicon Limited. All rights reserved.
>> +* Copyright (c) 2018, Linaro Limited. All rights reserved.
>> +*
>> +* This program and the accompanying materials
>> +* are licensed and made available under the terms and conditions of the BSD License
>> +* which accompanies this distribution. The full text of the license may be found at
>> +* http://opensource.org/licenses/bsd-license.php
>> +*
>> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +*
>> +* Based on the files under Platform/ARM/JunoPkg/AcpiTables/
>> +*
>> +**/
>> +
>> +#ifndef _PPTT_H_
>> +#define _PPTT_H_
>> +
>> +#include <IndustryStandard/Acpi.h>
>> +#include <Library/ArmLib/ArmLibPrivate.h>
>> +#include <Library/BaseMemoryLib.h>
>> +#include <Library/DebugLib.h>
>> +#include <Library/MemoryAllocationLib.h>
>> +#include <Library/UefiBootServicesTableLib.h>
>> +#include <Library/UefiLib.h>
>> +#include <Protocol/AcpiSystemDescriptionTable.h>
>> +#include <Protocol/AcpiTable.h>
>> +#include "../D05AcpiTables/Hi1616Platform.h"
>> +
>> +#define EFI_ACPI_MAX_NUM_TABLES 20
>> +
>> +#define PPTT_TABLE_MAX_LEN 0x6000
>> +#define PPTT_SOCKET_NO 0x2
>> +#define PPTT_SCCL_NO 0x2
>> +#define PPTT_CLUSTER_NO 0x4
>> +#define PPTT_CORE_NO 0x4
>> +#define PPTT_SOCKET_COMPONENT_NO 0x1
>> +#define PPTT_CACHE_NO 0x4
>> +
>> +#define PPTT_TYPE0_PHYSICAL_PKG BIT0
>> +#define PPTT_TYPE0_PROCESSORID_VALID BIT1
>
> I think these two flags belong in the acpi header file.. That said they are already defined by the bitfields in EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR_FLAGS so it might be a good idea to just remove them and convert the following definitions to the struct.
>
> That said, its a bit ugly either way, so your choice.
I plan to move these tow flags to Acpi62.h, and optimize the code for Flags.
>
>
>> +#define PPTT_TYPE0_SOCKET_FLAG PPTT_TYPE0_PHYSICAL_PKG
>> +#define PPTT_TYPE0_SCCL_FLAG 0
>> +#define PPTT_TYPE0_CLUSTER_FLAG 0
>> +#define PPTT_TYPE0_CORE_FLAG PPTT_TYPE0_PROCESSORID_VALID
>> +
>> +#define PPTT_TYPE1_ALLOCATION_WRITE 0x1
>> +#define PPTT_TYPE1_ALLOCATION_READ_WRITE 0x2
>
> Its more clear for these two, they should be in the acpi header file. While your at it the write policy and cache type should also probably be defined and used in your init routing.
>
>
I plan to move these two macro to Acpi62.h.
While your at it the write policy and cache type should also probably be defined and used in your init routing
I don't really understand the mean above.
>> +
>> +typedef union {
>> + struct {
>> + UINT32 InD :1;
>> + UINT32 Level :3;
>> + UINT32 Reserved :28;
>> + } Bits;
>> + UINT32 Data;
>> +} CSSELR_DATA;
>> +
>> +typedef union {
>> + struct {
>> + UINT32 LineSize :3;
>> + UINT32 Associativity :10;
>> + UINT32 NumSets :15;
>> + UINT32 Wa :1;
>> + UINT32 Ra :1;
>> + UINT32 Wb :1;
>> + UINT32 Wt :1;
>> + } Bits;
>> + UINT32 Data;
>> +} CCSIDR_DATA;
>
> This feels like it belongs in a diffrent header file closer to the ReadCCISDR() function (ArmLibPrivate.h).
>
I compare those macro of the ArmLibPrivae.h and these two struct. Those macro are not equivalent to
these two struct, like offset of Associativity is 3 in CCSIDR_DATA (as DDI0487A_h_armv8_arm.pdf),
but 15 in ArmLibPrivae.h, and miss NumSets in ArmLibPrivae.h, and so on.
>> +
>> +//
>> +// Processor Hierarchy Node Structure
>> +//
>> +typedef struct {
>> + UINT8 Type;
>> + UINT8 Length;
>> + UINT8 Reserved[2];
>> + UINT32 Flags;
>> + UINT32 Parent;
>> + UINT32 AcpiProcessorId;
>> + UINT32 NumberOfPrivateResources;
>> +} EFI_ACPI_6_2_PPTT_TYPE0;
>
> This belongs in the common ACPI header too.
>
I have replace it with struct in Acpi62.h.
Thanks,
Ming
>> +
>> +#endif // _PPTT_H_
>> +
>> diff --git a/Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf
>> new file mode 100644
>> index 0000000..ff6f772
>> --- /dev/null
>> +++ b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf
>> @@ -0,0 +1,48 @@
>> +/** @file
>> +*
>> +* Copyright (c) 2018, Hisilicon Limited. All rights reserved.
>> +* Copyright (c) 2018, Linaro Limited. All rights reserved.
>> +*
>> +* This program and the accompanying materials
>> +* are licensed and made available under the terms and conditions of the BSD License
>> +* which accompanies this distribution. The full text of the license may be found at
>> +* http://opensource.org/licenses/bsd-license.php
>> +*
>> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +*
>> +* Based on the files under Platform/ARM/JunoPkg/AcpiTables/
>> +*
>> +**/
>> +
>> +[Defines]
>> + INF_VERSION = 0x0001001A
>> + BASE_NAME = AcpiPptt
>> + FILE_GUID = AAB14F90-DC2E-4f33-A594-C7894A5B412D
>> + MODULE_TYPE = DXE_DRIVER
>> + VERSION_STRING = 1.0
>> + ENTRY_POINT = PpttEntryPoint
>> +
>> +[Sources.common]
>> + Pptt.c
>> +
>> +[Packages]
>> + ArmPkg/ArmPkg.dec
>> + MdePkg/MdePkg.dec
>> + Silicon/Hisilicon/HisiPkg.dec
>> +
>> +[LibraryClasses]
>> + ArmLib
>> + BaseMemoryLib
>> + DebugLib
>> + HobLib
>> + UefiDriverEntryPoint
>> + UefiRuntimeServicesTableLib
>> +
>> +[Protocols]
>> + gEfiAcpiSdtProtocolGuid ## PROTOCOL ALWAYS_CONSUMED
>> + gEfiAcpiTableProtocolGuid ## PROTOCOL ALWAYS_CONSUMED
>> +
>> +[Depex]
>> + gEfiAcpiTableProtocolGuid AND gEfiAcpiSdtProtocolGuid
>> +
>>
>
> Ok, so other than the above comments i'm pretty happy with it. IMHO the largest problem is the Type2 id definition which definitly needs to be 'HISI'.
>
> Reveiwed-by: Jeremy Linton <jeremy.linton@arm.com>
>
>
> Generally, I think this is a pretty good way to build the table. Enough so, that the next person to do an arm PPTT implementation should make an effort to move some of your helper functions (InitCacheInfo, Add* routines) into a generic library and tweak them enough that they can be resused across multiple platforms.
>
> Thanks,
>
> .
>
--
Best Regards,
Ming
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH edk2-platforms v2 02/15] Hisilicon/D05: Add PPTT support
2018-02-02 3:42 ` Huangming (Mark)
@ 2018-02-02 16:17 ` Jeremy Linton
0 siblings, 0 replies; 30+ messages in thread
From: Jeremy Linton @ 2018-02-02 16:17 UTC (permalink / raw)
To: Huangming (Mark), Ming Huang, leif.lindholm, linaro-uefi,
edk2-devel, graeme.gregory
Cc: ard.biesheuvel, zhangjinsong2, wanghuiqiang, guoheyi, waip23,
mengfanrong, huangdaode
Hi,
On 02/01/2018 09:42 PM, Huangming (Mark) wrote:
>
>
> On 2018/2/1 9:11, Jeremy Linton wrote:
>> Hi,
>>
>>
>> On 01/26/2018 02:00 AM, Ming Huang wrote:
>>> Add Processor Properties Topology Table, PPTT include
(trimming)
>>> +STATIC
>>> +VOID
>>> +InitCacheInfo (
>>> + VOID
>>> + )
>>> +{
>>> + UINT8 Index;
>>> + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES Type1Attributes;
>>> + CSSELR_DATA CsselrData;
>>> + CCSIDR_DATA CcsidrData;
>>> +
>>> + for (Index = 0; Index < PPTT_CACHE_NO; Index++) {
>>> + CsselrData.Data = 0;
>>> + CcsidrData.Data = 0;
>>> + SetMem (
>>> + &Type1Attributes,
>>> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES),
>>> + 0
>>> + );
>>> +
>>> + if (Index == 0) { //L1I
>>> + CsselrData.Bits.InD = 1;
>>> + CsselrData.Bits.Level = 0;
>>> + Type1Attributes.CacheType = 1;
>>> + } else if (Index == 1) {
>>> + Type1Attributes.CacheType = 0;
>>> + CsselrData.Bits.Level = Index - 1;
>>> + } else {
>>> + Type1Attributes.CacheType = 2;
>>> + CsselrData.Bits.Level = Index - 1;
>>> + }
>>> +
>>> + CcsidrData.Data = ReadCCSIDR (CsselrData.Data);
>>> +
>>> + if (CcsidrData.Bits.Wa == 1) {
>>> + Type1Attributes.AllocationType = PPTT_TYPE1_ALLOCATION_WRITE;
>>> + if (CcsidrData.Bits.Ra == 1) {
>>> + Type1Attributes.AllocationType = PPTT_TYPE1_ALLOCATION_READ_WRITE;
>>> + }
>>> + }
>>> +
>>> + if (CcsidrData.Bits.Wt == 1) {
>>> + Type1Attributes.WritePolicy = 1;
Note a few cases where you have mixed PPTT #define definitions for some
of the fields (AllocateType, WritePolicy, CacheType) with numeric values.
>>> + }
>>> + DEBUG ((DEBUG_INFO,
>>> + "[Acpi PPTT] Level = %x!CcsidrData = %x!\n",
>>> + CsselrData.Bits.Level,
>>> + CcsidrData.Data));
>>> +
>>> + mPpttCacheType1[Index].Type = EFI_ACPI_6_2_PPTT_TYPE_CACHE;
>>> + mPpttCacheType1[Index].Length = sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE);
>>> + mPpttCacheType1[Index].Reserved[0] = 0;
>>> + mPpttCacheType1[Index].Reserved[1] = 0;
>>> + mPpttCacheType1[Index].Flags.SizePropertyValid = 1;
>>> + mPpttCacheType1[Index].Flags.NumberOfSetsValid = 1;
>>> + mPpttCacheType1[Index].Flags.AssociativityValid = 1;
>>> + mPpttCacheType1[Index].Flags.AllocationTypeValid = 1;
>>> + mPpttCacheType1[Index].Flags.CacheTypeValid = 1;
>>> + mPpttCacheType1[Index].Flags.WritePolicyValid = 1;
>>> + mPpttCacheType1[Index].Flags.LineSizeValid = 1;
>>> + mPpttCacheType1[Index].Flags.Reserved = 0;
>>> + mPpttCacheType1[Index].NextLevelOfCache = 0;
>>> +
>>> + if (Index != PPTT_CACHE_NO - 1) {
>>> + mPpttCacheType1[Index].NumberOfSets = (UINT16)CcsidrData.Bits.NumSets + 1;
>>> + mPpttCacheType1[Index].Associativity = (UINT16)CcsidrData.Bits.Associativity + 1;
>>> + mPpttCacheType1[Index].LineSize = (UINT16)( 1 << (CcsidrData.Bits.LineSize + 4));
>>> + mPpttCacheType1[Index].Size = mPpttCacheType1[Index].LineSize * \
>>> + mPpttCacheType1[Index].Associativity * \
>>> + mPpttCacheType1[Index].NumberOfSets;
>>> + CopyMem (
>>> + &mPpttCacheType1[Index].Attributes,
>>> + &Type1Attributes,
>>> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES)
>>> + );
>>> + } else {
>>> + // L3 cache
>>> + mPpttCacheType1[Index].Size = 0x1000000; // 16m
>>> + mPpttCacheType1[Index].NumberOfSets = 0x2000;
>>> + mPpttCacheType1[Index].Associativity = 0x10; // CacheAssociativity16Way
>>> + SetMem (
>>> + &mPpttCacheType1[Index].Attributes,
>>> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES),
>>> + 0x0A
>>> + );
>>> + mPpttCacheType1[Index].LineSize = 0x80; // 128byte
>>> + }
>>> + }
(trimming)
>>> +#define PPTT_TYPE0_SOCKET_FLAG PPTT_TYPE0_PHYSICAL_PKG
>>> +#define PPTT_TYPE0_SCCL_FLAG 0
>>> +#define PPTT_TYPE0_CLUSTER_FLAG 0
>>> +#define PPTT_TYPE0_CORE_FLAG PPTT_TYPE0_PROCESSORID_VALID
>>> +
>>> +#define PPTT_TYPE1_ALLOCATION_WRITE 0x1
>>> +#define PPTT_TYPE1_ALLOCATION_READ_WRITE 0x2
>>
>> Its more clear for these two, they should be in the acpi header file. While your at it the write policy and cache type should also probably be defined and used in your init routing.
>>
>>
>
> I plan to move these two macro to Acpi62.h.
>
> "While your at it the write policy and cache type should also probably be defined and used in your init routing"
> I don't really understand the mean above.
I was simply suggesting that you define/use new #defines to describe
acpi standardized values you place in the policy and type (and any more
you think might be helpful) fields. For example, I found it a bit odd
that you defined PPTT_TYPE1_ALLOCATION_* but not 'PPTT_TYPE1_WRITE_POLICY_*'
Thanks,
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH edk2-platforms v2 00/15] Improve D0x platforms and bug fix
2018-01-29 17:33 ` [PATCH edk2-platforms v2 00/15] Improve D0x platforms and bug fix Leif Lindholm
@ 2018-02-03 7:50 ` Huangming (Mark)
0 siblings, 0 replies; 30+ messages in thread
From: Huangming (Mark) @ 2018-02-03 7:50 UTC (permalink / raw)
To: Leif Lindholm, Ming Huang
Cc: linaro-uefi, edk2-devel, graeme.gregory, ard.biesheuvel, guoheyi,
wanghuiqiang, zhangjinsong2, mengfanrong, huangdaode, waip23,
Jeremy Linton
On 2018/1/30 1:33, Leif Lindholm wrote:
> So, I'm mostly happy with this set, but:
>
> Sender (and hence Author for all patches that do not have a second
> From: statement after Subject: ) for all patches here is
> Ming Huang <heyi.guo@linaro.org>
>
> Can you please address this, either by actually sending from Ming Huang, or
> by adding a From:.
>
I had modify the auther to heyi Guo which is equal to the sender in V3, but
the emails do not have "From: " also, I am puzzle about that.
Maybe a Linaro email account for myself is the best solution.
Thanks,
Ming
> You can add my
> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> to 3-4, 6-12 and 15.
>
> I have a few comments on 5/15, and then I need some input from others
> on the ACPI bits - especially from Jeremy, who should ideally have
> been cc:d on at least the PPTT patch given his comments on v1.
>
> /
> Leif
>
> On Fri, Jan 26, 2018 at 04:00:35PM +0800, Ming Huang wrote:
>> The major features of this patchset include
>> adding PPTT support,
>> switching to Generic BDS driver,
>> adding capsule upgrade support,
>> open-source version for SnpPlatform and SasPlatform
>> changing DmaLib to CoherentDmaLib(this one is omissive in v1).
>>
>> Code can also be found in github: https://github.com/hisilicon/OpenPlatformPkg.git
>> branch: rp-1802-platforms-v2
>>
>>
>> Jason Zhang (3):
>> Hisilicon D03/D05: Add capsule upgrade support
>> Hisilicon D03/D05: Open SasPlatform source code
>> Hisilicon D03/D05: Open SnpPlatform source code
>>
>> Ming Huang (11):
>> Hisilicon/D05: Move Madt definition to head file
>> Hisilicon/D05: Add PPTT support
>> Hisilicon/D0x/BDS: Switch to Generic BDS driver
>> Hisilicon/D0x: Break BMC SetBoot option out into separate library
>> Hilisicon: Change DmaLib to CoherentDmaLib
>> Hisilicon/Smbios: Indicate use of ProcessorFamily2 in type 4 table
>> Hisilicon/D05: Replace SP805Watchdog by WatchdogTimer driver.
>> Hisilicon/D03: Replace SP805Watchdog by WatchdogTimer driver.
>> Hisilicon/D05/ACPI: Add ITS PXM
>> Hisilicon/D05/ACPI: Add Pcie, HNS and SAS PXM
>> Hisilicon D03/D05: Update firmware version to 18.02
>>
>> Yan Zhang (1):
>> Hisilicon/PCIe: Disable PCIe ASPM
>>
>> Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini | 45 ++
>> Platform/Hisilicon/D03/D03.dsc | 42 +-
>> Platform/Hisilicon/D03/D03.fdf | 79 ++-
>> Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc | 81 +++
>> Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 50 ++
>> Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c | 70 +++
>> Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini | 45 ++
>> Platform/Hisilicon/D05/D05.dsc | 47 +-
>> Platform/Hisilicon/D05/D05.fdf | 80 ++-
>> Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc | 81 +++
>> Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 50 ++
>> Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c | 70 +++
>> Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.c | 106 ++++
>> Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf | 45 ++
>> Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c | 4 +-
>> Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.c | 115 ++++
>> Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf | 46 ++
>> Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.c | 2 +-
>> Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.c | 3 +-
>> Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 103 ++++
>> Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 2 +
>> Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc | 10 +
>> Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl | 9 +
>> Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 34 +-
>> Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl | 19 +-
>> Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h | 30 +-
>> Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc | 23 +-
>> Silicon/Hisilicon/Hi1616/Pptt/Pptt.c | 540 ++++++++++++++++
>> Silicon/Hisilicon/Hi1616/Pptt/Pptt.h | 88 +++
>> Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf | 48 ++
>> Silicon/Hisilicon/HisiPkg.dec | 6 +
>> Silicon/Hisilicon/Hisilicon.dsc.inc | 12 +-
>> Silicon/Hisilicon/Hisilicon.fdf.inc | 9 +
>> Silicon/Hisilicon/Include/Library/AcpiNextLib.h | 10 +-
>> Silicon/Hisilicon/Include/Library/BmcConfigBootLib.h | 31 +
>> Silicon/Hisilicon/Include/Library/OemDevicePath.h | 52 ++
>> Silicon/Hisilicon/Include/Protocol/HisiPlatformSasProtocol.h | 30 +
>> Silicon/Hisilicon/Include/Protocol/SnpPlatformProtocol.h | 32 +
>> Silicon/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h | 2 +
>> Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.c | 466 ++++++++++++++
>> Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf | 51 ++
>> Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c | 643 ++++++++++++++++++++
>> Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.h | 31 +
>> Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf | 74 +++
>> Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c | 123 ++++
>> Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf | 51 ++
>> 46 files changed, 3536 insertions(+), 54 deletions(-)
>> create mode 100644 Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
>> create mode 100644 Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
>> create mode 100644 Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
>> create mode 100644 Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c
>> create mode 100644 Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
>> create mode 100644 Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
>> create mode 100644 Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
>> create mode 100644 Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c
>> create mode 100644 Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.c
>> create mode 100644 Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf
>> create mode 100644 Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.c
>> create mode 100644 Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf
>> create mode 100644 Silicon/Hisilicon/Hi1616/Pptt/Pptt.c
>> create mode 100644 Silicon/Hisilicon/Hi1616/Pptt/Pptt.h
>> create mode 100644 Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf
>> create mode 100644 Silicon/Hisilicon/Include/Library/BmcConfigBootLib.h
>> create mode 100644 Silicon/Hisilicon/Include/Library/OemDevicePath.h
>> create mode 100644 Silicon/Hisilicon/Include/Protocol/HisiPlatformSasProtocol.h
>> create mode 100644 Silicon/Hisilicon/Include/Protocol/SnpPlatformProtocol.h
>> create mode 100644 Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.c
>> create mode 100644 Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf
>> create mode 100644 Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c
>> create mode 100644 Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.h
>> create mode 100644 Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
>> create mode 100644 Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c
>> create mode 100644 Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf
>>
>> --
>> 1.9.1
>>
>
> .
>
--
Best Regards,
Ming
^ permalink raw reply [flat|nested] 30+ messages in thread
end of thread, other threads:[~2018-02-03 7:45 UTC | newest]
Thread overview: 30+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-01-26 8:00 [PATCH edk2-platforms v2 00/15] Improve D0x platforms and bug fix Ming Huang
2018-01-26 8:00 ` [PATCH edk2-platforms v2 01/15] Hisilicon/D05: Move Madt definition to head file Ming Huang
2018-01-30 14:27 ` graeme.gregory
2018-01-26 8:00 ` [PATCH edk2-platforms v2 02/15] Hisilicon/D05: Add PPTT support Ming Huang
2018-01-30 14:28 ` graeme.gregory
2018-02-01 1:11 ` Jeremy Linton
2018-02-02 3:42 ` Huangming (Mark)
2018-02-02 16:17 ` Jeremy Linton
2018-01-26 8:00 ` [PATCH edk2-platforms v2 03/15] Hisilicon/D0x/BDS: Switch to Generic BDS driver Ming Huang
2018-01-26 8:00 ` [PATCH edk2-platforms v2 04/15] Hisilicon/D0x: Break BMC SetBoot option out into separate library Ming Huang
2018-01-26 8:00 ` [PATCH edk2-platforms v2 05/15] Hisilicon D03/D05: Add capsule upgrade support Ming Huang
2018-01-29 19:58 ` Leif Lindholm
2018-01-30 12:48 ` Huangming (Mark)
2018-01-30 13:21 ` Leif Lindholm
2018-01-31 1:14 ` Huangming (Mark)
2018-01-30 12:47 ` Ard Biesheuvel
2018-01-26 8:00 ` [PATCH edk2-platforms v2 06/15] Hisilicon D03/D05: Open SasPlatform source code Ming Huang
2018-01-26 8:00 ` [PATCH edk2-platforms v2 07/15] Hisilicon D03/D05: Open SnpPlatform " Ming Huang
2018-01-26 8:00 ` [PATCH edk2-platforms v2 08/15] Hilisicon: Change DmaLib to CoherentDmaLib Ming Huang
2018-01-26 8:00 ` [PATCH edk2-platforms v2 09/15] Hisilicon/Smbios: Indicate use of ProcessorFamily2 in type 4 table Ming Huang
2018-01-26 8:00 ` [PATCH edk2-platforms v2 10/15] Hisilicon/PCIe: Disable PCIe ASPM Ming Huang
2018-01-26 8:00 ` [PATCH edk2-platforms v2 11/15] Hisilicon/D05: Replace SP805Watchdog by WatchdogTimer driver Ming Huang
2018-01-26 8:00 ` [PATCH edk2-platforms v2 12/15] Hisilicon/D03: " Ming Huang
2018-01-26 8:00 ` [PATCH edk2-platforms v2 13/15] Hisilicon/D05/ACPI: Add ITS PXM Ming Huang
2018-01-30 14:30 ` graeme.gregory
2018-01-26 8:00 ` [PATCH edk2-platforms v2 14/15] Hisilicon/D05/ACPI: Add Pcie, HNS and SAS PXM Ming Huang
2018-01-30 14:31 ` graeme.gregory
2018-01-26 8:00 ` [PATCH edk2-platforms v2 15/15] Hisilicon D03/D05: Update firmware version to 18.02 Ming Huang
2018-01-29 17:33 ` [PATCH edk2-platforms v2 00/15] Improve D0x platforms and bug fix Leif Lindholm
2018-02-03 7:50 ` Huangming (Mark)
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