From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c00::241; helo=mail-pf0-x241.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf0-x241.google.com (mail-pf0-x241.google.com [IPv6:2607:f8b0:400e:c00::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CE393223AF81A for ; Fri, 2 Feb 2018 04:00:44 -0800 (PST) Received: by mail-pf0-x241.google.com with SMTP id a14so3494681pfi.7 for ; Fri, 02 Feb 2018 04:06:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=yoVVwN/uzRWucY9XI1V3sx6klaNIUWZHRjNwPhGIbGs=; b=LoWbQkRvKGYninFMrY0az9YvU5wOyiMGkXoeuKUp48fSAeXTCtlOJbwkHmX1lvuz6Q yCiObxQqyaz4+LkKxwZb28yhHXkDXsWbM90MnO/Y0L5qB/Rmx52lYdRu9xb0UGXULgJ3 3o3PUd1Y61QWpRYyuPHCl2RQa2yTt8D2GKSLo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=yoVVwN/uzRWucY9XI1V3sx6klaNIUWZHRjNwPhGIbGs=; b=Wgzr7ymMEAtvlDcbgKvORmz/WKvqb0pNk9evooeuMOPcbloO8t7RpG4Eie+28PqyTb CBchrXHRtWyPginVZZEYzGM/T33X2Z/KHnOnMzP3ihihFOjoJ9Mcsc7pNrULnXX12OIn LQ6WIlgnl19onL2RHiTvAbAFa+z9TBQpIhCDTdtoRLALO3RQASyDnC16fRhkehIZ9zkR ZJ+Y+1eSRMLzOVJrhfKJJyVv1xsSBSb8OLlsZWVmARO25uRbjcMztp56DCODYZZg+IbM fThmYwcd32q6Ib88UTZ/q/H/OXp1L8JTAoBA8inxD7NzkGqxSkIdvSgZl0RDSQErjbXM Mvww== X-Gm-Message-State: AKwxytcRcnhNs7sg8LK5V8GAakxNi1qEI+cWfpsRqNJmmJGAlXY4CUZH dbKdHWvi/CaUyZhbOpECEDPsSA== X-Google-Smtp-Source: AH8x227N2bLc1JVN1jMGI4Q7WnLSZ8AWq0smoD0IJptcPt1jRvLmo88DcBEhKZvu3eh0V7S/nPo9KQ== X-Received: by 10.98.133.193 with SMTP id m62mr40573125pfk.18.1517573182919; Fri, 02 Feb 2018 04:06:22 -0800 (PST) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id b8sm3673047pff.31.2018.02.02.04.06.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 02 Feb 2018 04:06:22 -0800 (PST) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Cc: ard.biesheuvel@linaro.org, guoheyi@huawei.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, mengfanrong@huawei.com, huangdaode@hisilicon.com, john.garry@huawei.com, waip23@126.com, Heyi Guo , Yan Zhang Date: Fri, 2 Feb 2018 20:05:38 +0800 Message-Id: <1517573143-11451-11-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517573143-11451-1-git-send-email-heyi.guo@linaro.org> References: <1517573143-11451-1-git-send-email-heyi.guo@linaro.org> Subject: [PATCH edk2-platforms v3 10/15] Hisilicon/PCIe: Disable PCIe ASPM X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 02 Feb 2018 12:00:45 -0000 In order to replace command line parameter pcie_aspm=off, BIOS needs to disable Pcie Aspm support during Pcie initilization. D03 and D05 do not support PCIe ASPM, so we disable it in BIOS. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo Signed-off-by: Yan Zhang Reviewed-by: Leif Lindholm Reviewed-by: Ard Biesheuvel --- Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 103 ++++++++++++++++++++ Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 2 + Silicon/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h | 2 + 3 files changed, 107 insertions(+) diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index f420c91..c1c3fbb 100644 --- a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -1033,6 +1033,106 @@ DisableRcOptionRom ( return; } +STATIC +VOID +PcieDbiCs2Enable ( + IN UINT32 HostBridgeNum, + IN UINT32 Port, + IN BOOLEAN Val + ) +{ + UINT32 RegVal; + + RegRead ( + PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE_SYS_CTRL21, + RegVal + ); + if (Val) { + RegVal = RegVal | BIT2; + /* BIT2: DBI Chip Select indicator. 0 indicates CS, 1 indicates CS2.*/ + } else { + RegVal = RegVal & (~BIT2); + } + RegWrite ( + PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE_SYS_CTRL21, + RegVal + ); +} + +STATIC +BOOLEAN +PcieDBIReadOnlyWriteEnable ( + IN UINT32 HostBridgeNum, + IN UINT32 Port + ) +{ + UINT32 Val; + + RegRead ( + PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_DBI_READ_ONLY_WRITE_ENABLE, + Val + ); + if (Val == 0x1) { + return TRUE; + } else { + RegWrite ( + PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_DBI_READ_ONLY_WRITE_ENABLE, + 0x1 + ); + /* Delay 10us to make sure the PCIE device have enouph time to response. */ + MicroSecondDelay(10); + RegRead ( + PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_DBI_READ_ONLY_WRITE_ENABLE, + Val + ); + if (Val == 0x1) { + return TRUE; + } + } + DEBUG ((DEBUG_ERROR,"PcieDBIReadOnlyWriteEnable Fail!!!\n")); + return FALSE; +} + +STATIC +VOID +SwitchPcieASPMSupport ( + IN UINT32 HostBridgeNum, + IN UINT32 Port, + IN UINT8 Val + ) +{ + PCIE_EP_PCIE_CAP3_U PcieCap3; + + if (Port >= PCIE_MAX_ROOTBRIDGE) { + DEBUG ((DEBUG_ERROR, "Port is not valid\n")); + return; + } + if (!PcieDBIReadOnlyWriteEnable (HostBridgeNum, Port)) { + DEBUG ((DEBUG_INFO, "PcieDBI ReadOnly Reg do not Enable!!!\n")); + return; + } + PcieDbiCs2Enable (HostBridgeNum, Port, FALSE); + + RegRead ( + PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_EP_PCIE_CAP3_REG, + PcieCap3.UInt32 + ); + PcieCap3.Bits.active_state_power_management = Val; + RegWrite ( + PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_EP_PCIE_CAP3_REG, + PcieCap3.UInt32 + ); + RegRead ( + PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_EP_PCIE_CAP3_REG, + PcieCap3.UInt32 + ); + DEBUG ((DEBUG_INFO, + "ASPI active state power management: %d\n", + PcieCap3.Bits.active_state_power_management)); + + PcieDbiCs2Enable (HostBridgeNum, Port, TRUE); +} + EFI_STATUS EFIAPI PciePortInit ( @@ -1090,6 +1190,9 @@ PciePortInit ( /* disable link up interrupt */ (VOID)PcieMaskLinkUpInit(soctype, HostBridgeNum, PortIndex); + /* disable ASPM */ + SwitchPcieASPMSupport (HostBridgeNum, PortIndex, PCIE_ASPM_DISABLE); + /* Pcie Equalization*/ (VOID)PcieEqualization(soctype ,HostBridgeNum, PortIndex); diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h index 9a0f636..e96c53c 100644 --- a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h +++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h @@ -77,6 +77,8 @@ #define RegWrite(addr,data) MmioWrite32((addr), (data)) #define RegRead(addr,data) ((data) = MmioRead32 (addr)) +#define PCIE_ASPM_DISABLE 0x0 +#define PCIE_ASPM_ENABLE 0x1 typedef struct tagPcieDebugInfo { diff --git a/Silicon/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h b/Silicon/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h index bf57652..c8b9781 100644 --- a/Silicon/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h +++ b/Silicon/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h @@ -135,6 +135,7 @@ #define PCIE_EEP_PORTLOGIC53_REG (0x888) #define PCIE_EEP_GEN3_CONTRL_REG (0x890) #define PCIE_EEP_PIPE_LOOPBACK_REG (0x8B8) +#define PCIE_DBI_READ_ONLY_WRITE_ENABLE (0x8BC) #define PCIE_EEP_PORTLOGIC54_REG (0x900) #define PCIE_EEP_PORTLOGIC55_REG (0x904) #define PCIE_EEP_PORTLOGIC56_REG (0x908) @@ -12556,6 +12557,7 @@ typedef union tagPortlogic93 #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG (PCIE_SUBCTRL_BASE + 0x1018) #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG (PCIE_SUBCTRL_BASE + 0x101C) #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY7_REG (PCIE_SUBCTRL_BASE + 0x1020) +#define PCIE_SUBCTRL_SC_PCIE_SYS_CTRL21 (PCIE_SUBCTRL_BASE + 0x1024) #define PCIE_SUBCTRL_SC_DISPATCH_RETRY_CONTROL_REG (PCIE_SUBCTRL_BASE + 0x1030) #define PCIE_SUBCTRL_SC_DISPATCH_INTMASK_REG (PCIE_SUBCTRL_BASE + 0x1100) #define PCIE_SUBCTRL_SC_DISPATCH_RAWINT_REG (PCIE_SUBCTRL_BASE + 0x1104) -- 1.9.1