From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c05::242; helo=mail-pg0-x242.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pg0-x242.google.com (mail-pg0-x242.google.com [IPv6:2607:f8b0:400e:c05::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 122E6223972C4 for ; Wed, 7 Feb 2018 00:17:23 -0800 (PST) Received: by mail-pg0-x242.google.com with SMTP id l18so14355pgc.5 for ; Wed, 07 Feb 2018 00:23:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=lDJLaVehxYCCSstnxs8JHBeaKsLXcZIRefPcXFKeUic=; b=Z3Ex2A12/SuyDRSOhGZRx2NojPp8wZmGip2xzX5BeaG5mrtlXlPzTI/q4bEiHazyRQ tAhl//yeZ2nAJhJdleYPjp9txQGDgp6XqAdI2yFRSSIu+8VIshubpjsOcTWxdW+w0Zrk 63bvMifWlJkeW3c9YCNu54ql+sR3F6F/STMpo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=lDJLaVehxYCCSstnxs8JHBeaKsLXcZIRefPcXFKeUic=; b=Biizzd92lwSs5S1Vh4HQHjE+r9dxparWn/SRTykrDS5GWzECp2+42mW+eh4XmWlQx+ iK6DPtpfeMOOTEVTpn2ZGQk5t0CMCsae0z4DNaeVADYvpB/Lc+2GJ/F2W1YgJ8x55889 UpJzOflFofQEHL1zl5UCTIKpPJbwHUuXSi+30vgmbs4K8RHL/d9p9EEFhXHYVYrD6sa7 A1aTglmIasQTzgEMVsCqsiFfcyIiupCIFYqBtjTNGW446qk8CgmJY+OyagjNsVGioloB 2bbsIZQ7CzGinX9XdtCWd+Of8j4KnYaDQfcSbRv8SvqzXml8299AfxY7yaRshjeoxEFx gxHw== X-Gm-Message-State: APf1xPAq6xIxVtDZkZMvanEVoa8aveenme8eDJQInq5k8vazu/AXxRFK +INx4CuQ0LI8ZCYYNOG2WJBlCw== X-Google-Smtp-Source: AH8x226e0s5Cdkzu99pwjWZHWQsziG40HSx63KPSZ3DcyDbyGA+1/jOtQ8b4o47ZBJ8Skgje1AuBeQ== X-Received: by 10.99.113.67 with SMTP id b3mr4340189pgn.134.1517991787063; Wed, 07 Feb 2018 00:23:07 -0800 (PST) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id k127sm1984999pga.92.2018.02.07.00.22.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 07 Feb 2018 00:23:06 -0800 (PST) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Cc: ard.biesheuvel@linaro.org, guoheyi@huawei.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, mengfanrong@huawei.com, huangdaode@hisilicon.com, john.garry@huawei.com, waip23@126.com, Heyi Guo Date: Wed, 7 Feb 2018 16:22:34 +0800 Message-Id: <1517991769-5485-1-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 Subject: [PATCH edk2-platforms v4 00/15] Improve D0x platforms and bug fix X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 07 Feb 2018 08:17:24 -0000 The major features of this patchset include adding PPTT support, switching to Generic BDS driver, adding capsule upgrade support, open-source version for SnpPlatform and SasPlatform changing DmaLib to CoherentDmaLib. Comparison of V3: 1 Modify PPTT as the edk2 patch "MdePkg ACPI: Add some macros for PPTT".(hash:c4e7557) 2 Correct the email of Graeme Gregory. Code can also be found in github: https://github.com/hisilicon/OpenPlatformPkg.git branch: rp-1802-platforms-v4 Heyi Guo (15): Hisilicon/D05: Move Madt definition to head file Hisilicon/D05: Add PPTT support Hisilicon/D0x/BDS: Switch to Generic BDS driver Hisilicon/D0x: Break BMC SetBoot option out into separate library Hisilicon D03/D05: Add capsule upgrade support Hisilicon D03/D05: Open SasPlatform source code Hisilicon D03/D05: Open SnpPlatform source code Hilisicon: Change DmaLib to CoherentDmaLib Hisilicon/Smbios: Indicate use of ProcessorFamily2 in type 4 table Hisilicon/PCIe: Disable PCIe ASPM Hisilicon/D05: Replace SP805Watchdog by WatchdogTimer driver. Hisilicon/D03: Replace SP805Watchdog by WatchdogTimer driver. Hisilicon/D05/ACPI: Add ITS PXM Hisilicon/D05/ACPI: Add Pcie, HNS and SAS PXM Hisilicon D03/D05: Update firmware version to 18.02 Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini | 45 ++ Platform/Hisilicon/D03/D03.dsc | 42 +- Platform/Hisilicon/D03/D03.fdf | 79 ++- Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc | 81 +++ Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 50 ++ Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c | 70 +++ Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini | 45 ++ Platform/Hisilicon/D05/D05.dsc | 47 +- Platform/Hisilicon/D05/D05.fdf | 80 ++- Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc | 81 +++ Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 50 ++ Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c | 70 +++ Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.c | 106 ++++ Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf | 45 ++ Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c | 4 +- Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.c | 115 ++++ Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf | 46 ++ Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.c | 2 +- Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.c | 3 +- Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 103 ++++ Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 2 + Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc | 10 + Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl | 9 + Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 34 +- Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl | 19 +- Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h | 30 +- Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc | 23 +- Silicon/Hisilicon/Hi1616/Pptt/Pptt.c | 529 ++++++++++++++++ Silicon/Hisilicon/Hi1616/Pptt/Pptt.h | 67 ++ Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf | 48 ++ Silicon/Hisilicon/HisiPkg.dec | 6 + Silicon/Hisilicon/Hisilicon.dsc.inc | 12 +- Silicon/Hisilicon/Hisilicon.fdf.inc | 9 + Silicon/Hisilicon/Include/Library/AcpiNextLib.h | 10 +- Silicon/Hisilicon/Include/Library/BmcConfigBootLib.h | 31 + Silicon/Hisilicon/Include/Library/OemDevicePath.h | 52 ++ Silicon/Hisilicon/Include/Protocol/HisiPlatformSasProtocol.h | 30 + Silicon/Hisilicon/Include/Protocol/SnpPlatformProtocol.h | 32 + Silicon/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h | 2 + Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.c | 466 ++++++++++++++ Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf | 51 ++ Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c | 643 ++++++++++++++++++++ Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.h | 31 + Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf | 74 +++ Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c | 123 ++++ Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf | 51 ++ 46 files changed, 3504 insertions(+), 54 deletions(-) create mode 100644 Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini create mode 100644 Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc create mode 100644 Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf create mode 100644 Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c create mode 100644 Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini create mode 100644 Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc create mode 100644 Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf create mode 100644 Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c create mode 100644 Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.c create mode 100644 Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf create mode 100644 Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.c create mode 100644 Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf create mode 100644 Silicon/Hisilicon/Hi1616/Pptt/Pptt.c create mode 100644 Silicon/Hisilicon/Hi1616/Pptt/Pptt.h create mode 100644 Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf create mode 100644 Silicon/Hisilicon/Include/Library/BmcConfigBootLib.h create mode 100644 Silicon/Hisilicon/Include/Library/OemDevicePath.h create mode 100644 Silicon/Hisilicon/Include/Protocol/HisiPlatformSasProtocol.h create mode 100644 Silicon/Hisilicon/Include/Protocol/SnpPlatformProtocol.h create mode 100644 Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.c create mode 100644 Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf create mode 100644 Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c create mode 100644 Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.h create mode 100644 Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf create mode 100644 Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c create mode 100644 Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf -- 1.9.1