From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=dandan.bi@intel.com; receiver=edk2-devel@lists.01.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C13F221FD73D4 for ; Tue, 6 Mar 2018 21:47:35 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Mar 2018 21:53:50 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.47,434,1515484800"; d="scan'208";a="22375585" Received: from shwdeopenpsi114.ccr.corp.intel.com ([10.239.157.135]) by fmsmga007.fm.intel.com with ESMTP; 06 Mar 2018 21:53:49 -0800 From: Dandan Bi To: edk2-devel@lists.01.org Cc: Eric Dong , Laszlo Ersek , Ruiyu Ni Date: Wed, 7 Mar 2018 13:53:37 +0800 Message-Id: <1520402018-7012-1-git-send-email-dandan.bi@intel.com> X-Mailer: git-send-email 1.9.5.msysgit.1 Subject: [patch] UefiCpuPkg/CpuCommonFeaturesLib: Fix coding style issue X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 07 Mar 2018 05:47:36 -0000 Boolean values do not need to use explicit comparisons to TRUE or FALSE. Cc: Eric Dong Cc: Laszlo Ersek Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Dandan Bi --- UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c index cc64dbb..27ca911 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c @@ -138,11 +138,11 @@ McaInitialize ( ) { MSR_IA32_MCG_CAP_REGISTER McgCap; UINT32 BankIndex; - if (State == TRUE) { + if (State) { McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP); for (BankIndex = 0; BankIndex < (UINT32) McgCap.Bits.Count; BankIndex++) { CPU_REGISTER_TABLE_WRITE64 ( ProcessorNumber, Msr, -- 1.9.5.msysgit.1