From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c00::231; helo=mail-pf0-x231.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf0-x231.google.com (mail-pf0-x231.google.com [IPv6:2607:f8b0:400e:c00::231]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 29C80225892D3 for ; Wed, 14 Mar 2018 20:54:30 -0700 (PDT) Received: by mail-pf0-x231.google.com with SMTP id j2so2354515pff.10 for ; Wed, 14 Mar 2018 21:00:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BwZx+quN1GrEF+Tkz0rgusbFNo/t8Ot0pZFC3n8/xF4=; b=QiALn0Pf7KQMEZ/0BRU0KLRitmnjIEGihiLAg/x78WPUVIbb1JnSwCDIGZM2O3Hsrb kWj/7YT9xcRaueQvkZoHme88AeQt8wMN5NB5GsEA+hE51vAqz9cQSGwFCfOOMww5y/Mr z9XLwDfe4z5P8euTmRl8PANA5l8WTx3iyQcEU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BwZx+quN1GrEF+Tkz0rgusbFNo/t8Ot0pZFC3n8/xF4=; b=d+YKEHLKgbvJMxECSh/qaMMF/I6PvNVfQ3bCR1WAAENlfkZahEFCWoxPcXcOIBv82G 7ltnyFw68EGIex2OQISFX/gQh+R7L9MWbeko8YEn5q55NEJ+Wsyw1fRWve5bKlvjzcE6 EJTTpG73pLxSzenqs5PYC+Ms1fWukjFjJ2HS8PCTnPkkfnBDhBPRSL8CaAWDWnAWr7+3 huBGw2O/eFeeFHzjHswAT6Ixb8gaiQAEqVDEtb07E7SWzf2qq/5kaL7OhJpgQ/DJWxzO BOBMu2pr4QYdHZHgFOsGGtXWfocSwLGWcLJgYv5GrxRHKXAk7/s77GKMb6xEGeEMkVyo WX/g== X-Gm-Message-State: AElRT7HcHZvR6aZZVqwIWKKF5Ai6jwso5rzGTnq8PUlQRkYdY2RqBs1b 9aSedjIFzYbjNkBRdAnV8W42AiuY4+4= X-Google-Smtp-Source: AG47ELu9mLCsvBgGTglyIVCmi0LCpAVA1fdPl0zwIN/GIEuZBs4k9W4+nDHisZpYhInzalveoehmog== X-Received: by 10.98.133.193 with SMTP id m62mr6478706pfk.74.1521086453927; Wed, 14 Mar 2018 21:00:53 -0700 (PDT) Received: from localhost.localdomain ([45.56.152.100]) by smtp.gmail.com with ESMTPSA id e4sm8107785pfa.166.2018.03.14.21.00.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Mar 2018 21:00:53 -0700 (PDT) From: Heyi Guo To: edk2-devel@lists.01.org Cc: Heyi Guo , Yi Li , Maurice Ma , Prince Agyeman , Benjamin You , Ruiyu Ni , Laszlo Ersek , Ard Biesheuvel Date: Thu, 15 Mar 2018 12:00:19 +0800 Message-Id: <1521086424-113954-2-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1521086424-113954-1-git-send-email-heyi.guo@linaro.org> References: <1521086424-113954-1-git-send-email-heyi.guo@linaro.org> Subject: [PATCH v6 1/6] CorebootPayloadPkg/PciHostBridgeLib: clear aperture vars for (re)init X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 15 Mar 2018 03:54:31 -0000 Use ZeroMem() to initialize (or re-initialize) all fields in temporary PCI_ROOT_BRIDGE_APERTURE variables to zero. This is not mandatory but helpful for future extension: when we add new fields to PCI_ROOT_BRIDGE_APERTURE and the default value of these fields can safely be zero, this code will not suffer from an additional change. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Heyi Guo Signed-off-by: Yi Li Cc: Maurice Ma Cc: Prince Agyeman Cc: Benjamin You Cc: Ruiyu Ni Cc: Laszlo Ersek Cc: Ard Biesheuvel --- Notes: v6: - Move ZeroMem() into the loop just as Laszlo commented on OvmfPkg [Laszlo] - Minor changes in commit message CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c index 6d94ff72c956..18dcbafdf0c6 100644 --- a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c +++ b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c @@ -328,8 +328,13 @@ ScanForRootBridges ( for (PrimaryBus = 0; PrimaryBus <= PCI_MAX_BUS; PrimaryBus = SubBus + 1) { SubBus = PrimaryBus; Attributes = 0; + + ZeroMem (&Io, sizeof (Io)); + ZeroMem (&Mem, sizeof (Mem)); + ZeroMem (&MemAbove4G, sizeof (MemAbove4G)); + ZeroMem (&PMem, sizeof (PMem)); + ZeroMem (&PMemAbove4G, sizeof (PMemAbove4G)); Io.Base = Mem.Base = MemAbove4G.Base = PMem.Base = PMemAbove4G.Base = MAX_UINT64; - Io.Limit = Mem.Limit = MemAbove4G.Limit = PMem.Limit = PMemAbove4G.Limit = 0; // // Scan all the PCI devices on the primary bus of the PCI root bridge // -- 2.7.4