[PATCH v7 0/6] Add translation support to generic PciHostBridge

[PATCH v7 0/6] Add translation support to generic PciHostBridge

[Heyi Guo]

Code can also be found here:
https://github.com/iwishguo/edk2/tree/patch-pci-host-bridge-v7

v7:
- Patch 4: implement 1 comments from Ray.

v6:
- Patch 1, 2: implement 3 comments from Laszlo.
- Patch 4: implement 3 comments from Ray.

Patch v5 inherits the code from RFC v4; we don't restart the version number for
RFC to PATCH change.

v5:
- Patch 4/6: Modify the code according to the comments from Ray.
- Patch 1/6 and 2/6 are totally new. They add initialization for all fields of
  PCI_ROOT_BRIDGE_APERTURE temporary variables in PciHostBridgeLib instances, so
  that they will not suffer from extension of PCI_ROOT_BRIDGE_APERTURE
  structure.
- Generate a separate patch (3/6) for PciHostBridgeLib.h change. Though it is a
  prerequisite for patch 4/6, it does not change the code in PciHostBridge
  driver and won't cause any build failure or functional issue.


v4:
- Modify the code according to the comments from Ray, Laszlo and Ard (Please see
  the notes of Patch 1/3)
- Ignore translation of bus in CreateRootBridge.


v3:
- Keep definition of Translation consistent in EDKII code: Translation = device
  address - host address.
- Patch 2/2 is split into 2 patches (2/3 and 3/3).
- Refine comments and commit messages to make the code easier to understand.


v2:
Changs are made according to the discussion on the mailing list, including:

- PciRootBridgeIo->Configuration should return CPU view address, as well as
  PciIo->GetBarAttributes, and Translation Offset should be equal to PCI view
  address - CPU view address.
- Add translation offset to PCI_ROOT_BRIDGE_APERTURE structure definition.
- PciHostBridge driver internally used Base Address is still based on PCI view
  address, and translation offset = CPU view - PCI view, which follows the
  definition in ACPI, and not the same as that in UEFI spec.

Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Prince Agyeman <prince.agyeman@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Anthony Perard <anthony.perard@citrix.com>
Cc: Julien Grall <julien.grall@linaro.org>


Heyi Guo (6):
  CorebootPayloadPkg/PciHostBridgeLib: clear aperture vars for (re)init
  OvmfPkg/PciHostBridgeLib: clear PCI aperture vars for (re)init
  MdeModulePkg/PciHostBridgeLib.h: add address Translation
  MdeModulePkg/PciHostBridgeDxe: Add support for address translation
  MdeModulePkg/PciBus: convert host address to device address
  MdeModulePkg/PciBus: return CPU address for GetBarAttributes

 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.h              |  21 +++
 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostResource.h            |   3 +
 MdeModulePkg/Include/Library/PciHostBridgeLib.h                    |  19 +++
 CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c |   7 +-
 MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c                             |  12 +-
 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c              | 129 ++++++++++++++++---
 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c            | 135 ++++++++++++++++++--
 OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c                |   4 +
 OvmfPkg/Library/PciHostBridgeLib/XenSupport.c                      |   7 +-
 9 files changed, 306 insertions(+), 31 deletions(-)

-- 
2.7.4

[PATCH v7 1/6] CorebootPayloadPkg/PciHostBridgeLib: clear aperture vars for (re)init

[Heyi Guo]

Use ZeroMem() to initialize (or re-initialize) all fields in temporary
PCI_ROOT_BRIDGE_APERTURE variables to zero. This is not mandatory but
helpful for future extension: when we add new fields to
PCI_ROOT_BRIDGE_APERTURE and the default value of these fields can
safely be zero, this code will not suffer from an additional change.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Signed-off-by: Yi Li <phoenix.liyi@huawei.com>
Reviewed-by: Ni Ruiyu <ruiyu.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Prince Agyeman <prince.agyeman@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---

Notes:
    v6:
    - Move ZeroMem() into the loop just as Laszlo commented on OvmfPkg
      [Laszlo]
    - Minor changes in commit message

 CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
index 6d94ff72c956..18dcbafdf0c6 100644
--- a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
+++ b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
@@ -328,8 +328,13 @@ ScanForRootBridges (
   for (PrimaryBus = 0; PrimaryBus <= PCI_MAX_BUS; PrimaryBus = SubBus + 1) {
     SubBus = PrimaryBus;
     Attributes = 0;
+
+    ZeroMem (&Io, sizeof (Io));
+    ZeroMem (&Mem, sizeof (Mem));
+    ZeroMem (&MemAbove4G, sizeof (MemAbove4G));
+    ZeroMem (&PMem, sizeof (PMem));
+    ZeroMem (&PMemAbove4G, sizeof (PMemAbove4G));
     Io.Base = Mem.Base = MemAbove4G.Base = PMem.Base = PMemAbove4G.Base = MAX_UINT64;
-    Io.Limit = Mem.Limit = MemAbove4G.Limit = PMem.Limit = PMemAbove4G.Limit = 0;
     //
     // Scan all the PCI devices on the primary bus of the PCI root bridge
     //
-- 
2.7.4

Re: [PATCH v7 1/6] CorebootPayloadPkg/PciHostBridgeLib: clear aperture vars for (re)init

[You, Benjamin]

Reviewed-by: Benjamin You <benjamin.you@intel.com>

> -----Original Message-----
> From: Heyi Guo [mailto:heyi.guo@linaro.org]
> Sent: Thursday, March 15, 2018 2:04 PM
> To: edk2-devel@lists.01.org
> Cc: Heyi Guo <heyi.guo@linaro.org>; Yi Li <phoenix.liyi@huawei.com>; Ma,
> Maurice <maurice.ma@intel.com>; Agyeman, Prince
> <prince.agyeman@intel.com>; You, Benjamin <benjamin.you@intel.com>; Ni,
> Ruiyu <ruiyu.ni@intel.com>; Laszlo Ersek <lersek@redhat.com>; Ard Biesheuvel
> <ard.biesheuvel@linaro.org>
> Subject: [PATCH v7 1/6] CorebootPayloadPkg/PciHostBridgeLib: clear aperture
> vars for (re)init
> 
> Use ZeroMem() to initialize (or re-initialize) all fields in temporary
> PCI_ROOT_BRIDGE_APERTURE variables to zero. This is not mandatory but
> helpful for future extension: when we add new fields to
> PCI_ROOT_BRIDGE_APERTURE and the default value of these fields can
> safely be zero, this code will not suffer from an additional change.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
> Signed-off-by: Yi Li <phoenix.liyi@huawei.com>
> Reviewed-by: Ni Ruiyu <ruiyu.ni@intel.com>
> Cc: Maurice Ma <maurice.ma@intel.com>
> Cc: Prince Agyeman <prince.agyeman@intel.com>
> Cc: Benjamin You <benjamin.you@intel.com>
> Cc: Ruiyu Ni <ruiyu.ni@intel.com>
> Cc: Laszlo Ersek <lersek@redhat.com>
> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
> 
> Notes:
>     v6:
>     - Move ZeroMem() into the loop just as Laszlo commented on OvmfPkg
>       [Laszlo]
>     - Minor changes in commit message
> 
>  CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c | 7
> ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git
> a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
> b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
> index 6d94ff72c956..18dcbafdf0c6 100644
> --- a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
> +++ b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
> @@ -328,8 +328,13 @@ ScanForRootBridges (
>    for (PrimaryBus = 0; PrimaryBus <= PCI_MAX_BUS; PrimaryBus = SubBus + 1) {
>      SubBus = PrimaryBus;
>      Attributes = 0;
> +
> +    ZeroMem (&Io, sizeof (Io));
> +    ZeroMem (&Mem, sizeof (Mem));
> +    ZeroMem (&MemAbove4G, sizeof (MemAbove4G));
> +    ZeroMem (&PMem, sizeof (PMem));
> +    ZeroMem (&PMemAbove4G, sizeof (PMemAbove4G));
>      Io.Base = Mem.Base = MemAbove4G.Base = PMem.Base =
> PMemAbove4G.Base = MAX_UINT64;
> -    Io.Limit = Mem.Limit = MemAbove4G.Limit = PMem.Limit =
> PMemAbove4G.Limit = 0;
>      //
>      // Scan all the PCI devices on the primary bus of the PCI root bridge
>      //
> --
> 2.7.4

[PATCH v7 2/6] OvmfPkg/PciHostBridgeLib: clear PCI aperture vars for (re)init

[Heyi Guo]

Use ZeroMem() to initialize (or re-initialize) all fields in temporary
PCI_ROOT_BRIDGE_APERTURE variables to zero. This is not mandatory but
is helpful for future extension: when we add new fields to
PCI_ROOT_BRIDGE_APERTURE and the default value of these fields can
safely be zero, this code will not suffer from an additional
change.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Signed-off-by: Yi Li <phoenix.liyi@huawei.com>
Reviewed-by: Ni Ruiyu <ruiyu.ni@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Anthony Perard <anthony.perard@citrix.com>
Cc: Julien Grall <julien.grall@linaro.org>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---

Notes:
    v6:
    - Move ZeroMem() into the loop [Laszlo]
    - Move ZeroMem() after checking PcdPciDisableBusEnumeration [Laszlo]
    - Commit title change (However 74 characters will cause PatchCheck
      warning, so I tried to reduce the length to eliminate the warning) [laszlo]
    - Minor changes in commit message

 OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c | 4 ++++
 OvmfPkg/Library/PciHostBridgeLib/XenSupport.c       | 7 ++++++-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c b/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
index ff837035caff..65d0ef9252c5 100644
--- a/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
+++ b/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
@@ -221,6 +221,10 @@ PciHostBridgeGetRootBridges (
     return ScanForRootBridges (Count);
   }
 
+  ZeroMem (&Io, sizeof (Io));
+  ZeroMem (&Mem, sizeof (Mem));
+  ZeroMem (&MemAbove4G, sizeof (MemAbove4G));
+
   Attributes = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO |
     EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO |
     EFI_PCI_ATTRIBUTE_ISA_IO_16 |
diff --git a/OvmfPkg/Library/PciHostBridgeLib/XenSupport.c b/OvmfPkg/Library/PciHostBridgeLib/XenSupport.c
index 31c63ae19e0a..920417950ad9 100644
--- a/OvmfPkg/Library/PciHostBridgeLib/XenSupport.c
+++ b/OvmfPkg/Library/PciHostBridgeLib/XenSupport.c
@@ -202,8 +202,13 @@ ScanForRootBridges (
   for (PrimaryBus = 0; PrimaryBus <= PCI_MAX_BUS; PrimaryBus = SubBus + 1) {
     SubBus = PrimaryBus;
     Attributes = 0;
+
+    ZeroMem (&Io, sizeof (Io));
+    ZeroMem (&Mem, sizeof (Mem));
+    ZeroMem (&MemAbove4G, sizeof (MemAbove4G));
+    ZeroMem (&PMem, sizeof (PMem));
+    ZeroMem (&PMemAbove4G, sizeof (PMemAbove4G));
     Io.Base = Mem.Base = MemAbove4G.Base = PMem.Base = PMemAbove4G.Base = MAX_UINT64;
-    Io.Limit = Mem.Limit = MemAbove4G.Limit = PMem.Limit = PMemAbove4G.Limit = 0;
     //
     // Scan all the PCI devices on the primary bus of the PCI root bridge
     //
-- 
2.7.4

[PATCH v7 3/6] MdeModulePkg/PciHostBridgeLib.h: add address Translation

[Heyi Guo]

Add Translation field to PCI_ROOT_BRIDGE_APERTURE. Translation is used
to represent the difference between device address and host address,
if they are not the same on some platforms.

In UEFI 2.7, "Address Translation Offset" is "Offset to apply to the
Starting address to convert it to a PCI address".  This means:

  Translation = device address - host address

So we also use the above calculation for this Translation field to
keep consistent.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Signed-off-by: Yi Li <phoenix.liyi@huawei.com>
Reviewed-by: Ni Ruiyu <ruiyu.ni@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
---
 MdeModulePkg/Include/Library/PciHostBridgeLib.h | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/MdeModulePkg/Include/Library/PciHostBridgeLib.h b/MdeModulePkg/Include/Library/PciHostBridgeLib.h
index d42e9ecdd763..18963a0d3821 100644
--- a/MdeModulePkg/Include/Library/PciHostBridgeLib.h
+++ b/MdeModulePkg/Include/Library/PciHostBridgeLib.h
@@ -20,8 +20,27 @@
 // (Base > Limit) indicates an aperture is not available.
 //
 typedef struct {
+  //
+  // Base and Limit are the device address instead of host address when
+  // Translation is not zero
+  //
   UINT64 Base;
   UINT64 Limit;
+  //
+  // According to UEFI 2.7, Device Address = Host Address + Translation,
+  // so Translation = Device Address - Host Address.
+  // On platforms where Translation is not zero, the subtraction is probably to
+  // be performed with UINT64 wrap-around semantics, for we may translate an
+  // above-4G host address into a below-4G device address for legacy PCIe device
+  // compatibility.
+  //
+  // NOTE: The alignment of Translation is required to be larger than any BAR
+  // alignment in the same root bridge, so that the same alignment can be
+  // applied to both device address and host address, which simplifies the
+  // situation and makes the current resource allocation code in generic PCI
+  // host bridge driver still work.
+  //
+  UINT64 Translation;
 } PCI_ROOT_BRIDGE_APERTURE;
 
 typedef struct {
-- 
2.7.4

[PATCH v7 4/6] MdeModulePkg/PciHostBridgeDxe: Add support for address translation

[Heyi Guo]

PCI address translation is necessary for some non-x86 platforms. On
such platforms, address value (denoted as "device address" or "address
in PCI view") set to PCI BAR registers in configuration space might be
different from the address which is used by CPU to access the
registers in memory BAR or IO BAR spaces (denoted as "host address" or
"address in CPU view"). The difference between the two addresses is
called "Address Translation Offset" or simply "translation", and can
be represented by "Address Translation Offset" in ACPI QWORD Address
Space Descriptor (Offset 0x1E). However UEFI and ACPI differs on the
definitions of QWORD Address Space Descriptor, and we will follow UEFI
definition on UEFI protocols, such as PCI root bridge IO protocol and
PCI IO protocol. In UEFI 2.7, "Address Translation Offset" is "Offset
to apply to the Starting address to convert it to a PCI address". This
means:

1. Translation = device address - host address.

2. PciRootBridgeIo->Configuration should return CPU view address, as
well as PciIo->GetBarAttributes.

Summary of addresses used in protocol interfaces and internal
implementations:

1. *Only* the following protocol interfaces assume Address is Device
   Address:
(1). PciHostBridgeResourceAllocation.GetProposedResources()
     Otherwise PCI bus driver cannot set correct address into PCI
     BARs.
(2). PciRootBridgeIo.Mem.Read() and PciRootBridgeIo.Mem.Write()
(3). PciRootBridgeIo.CopyMem()
UEFI and PI spec have clear statements for all other protocol
interfaces about the address type.

2. Library interfaces and internal implementation:
(1). Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device address.
     It is easy to check whether the address is below 4G or above 4G.
(2). Addresses in PCI_ROOT_BRIDGE_INSTANCE.ResAllocNode are host
     address, for they are allocated from GCD.
(3). Address passed to PciHostBridgeResourceConflict is host address,
     for it comes from PCI_ROOT_BRIDGE_INSTANCE.ResAllocNode.

RESTRICTION: to simplify the situation, we require the alignment of
Translation must be larger than any BAR alignment in the same root
bridge, so that resource allocation alignment can be applied to both
device address and host address.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Signed-off-by: Yi Li <phoenix.liyi@huawei.com>
Reviewed-by: Ni Ruiyu <ruiyu.ni@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
---

Notes:
    v7:
    - Move ASSERT into if-check to print error details before assertion
      [Ray]
    
    v6:
    - Change ASSERT(FALSE) to ASSERT ((Translation & Alignment) == 0) and
      move ASSERT before if-check [Ray]
    - Print translation of bus and then assert [Ray]
    - Add function header for RootBridgeIoGetMemTranslationByAddress()
      [Ray]
    
    v5:
    - Add check for the alignment of Translation against the BAR alignment
      [Ray]
    - Keep coding style of comments consistent with the context [Ray]
    - Comment change for Base in PCI_RES_NODE [Ray]
    - Add macros of TO_HOST_ADDRESS and TO_DEVICE_ADDRESS for address type
      conversion (After that we can also simply the comments about the
      calculation [Ray]
    - Add check for bus translation offset in CreateRootBridge(), making
      sure it is zero, and unify code logic for all types of resource
      after that [Ray]
    - Use GetTranslationByResourceType() to simplify the code in
      RootBridgeIoConfiguration() (also fix a bug in previous patch
      version of missing a break after case TypePMem64) [Ray]
    - Commit message refinement [Ray]
    
    v4:
    - Add ASSERT (FALSE) to default branch in GetTranslationByResourceType
      [Laszlo]
    - Fix bug when passing BaseAddress to gDS->AllocateIoSpace and
      gDS->AllocateMemorySpace [Laszlo]
    - Add comment for applying alignment to both device address and host
      address, and add NOTE for the alignment requirement of Translation,
      as well as in commit message [Laszlo][Ray]
    - Improve indention for the code in CreateRootBridge [Laszlo]
    - Improve comment for Translation in PCI_ROOT_BRIDGE_APERTURE
      definition [Laszlo]
    - Ignore translation of bus in CreateRootBridge
    
    v4:
    - Add ASSERT (FALSE) to default branch in GetTranslationByResourceType
      [Laszlo]
    - Fix bug when passing BaseAddress to gDS->AllocateIoSpace and
      gDS->AllocateMemorySpace [Laszlo]
    - Add comment for applying alignment to both device address and host
      address, and add NOTE for the alignment requirement of Translation,
      as well as in commit message [Laszlo][Ray]
    - Improve indention for the code in CreateRootBridge [Laszlo]
    - Improve comment for Translation in PCI_ROOT_BRIDGE_APERTURE
      definition [Laszlo]
    - Ignore translation of bus in CreateRootBridge

 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.h   |  21 +++
 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostResource.h |   3 +
 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c   | 129 ++++++++++++++++---
 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 135 ++++++++++++++++++--
 4 files changed, 261 insertions(+), 27 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.h b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.h
index 9a8ca21f4819..c2791ea5c2a4 100644
--- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.h
+++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.h
@@ -38,6 +38,13 @@ typedef struct {
 #define PCI_HOST_BRIDGE_FROM_THIS(a) CR (a, PCI_HOST_BRIDGE_INSTANCE, ResAlloc, PCI_HOST_BRIDGE_SIGNATURE)
 
 //
+// Macros to translate device address to host address and vice versa. According
+// to UEFI 2.7, device address = host address + translation offset.
+//
+#define TO_HOST_ADDRESS(DeviceAddress,TranslationOffset) ((DeviceAddress) - (TranslationOffset))
+#define TO_DEVICE_ADDRESS(HostAddress,TranslationOffset) ((HostAddress) + (TranslationOffset))
+
+//
 // Driver Entry Point
 //
 /**
@@ -247,6 +254,20 @@ ResourceConflict (
   IN  PCI_HOST_BRIDGE_INSTANCE *HostBridge
   );
 
+/**
+  This routine gets translation offset from a root bridge instance by resource type.
+
+  @param RootBridge The Root Bridge Instance for the resources.
+  @param ResourceType The Resource Type of the translation offset.
+
+  @retval The Translation Offset of the specified resource.
+**/
+UINT64
+GetTranslationByResourceType (
+  IN  PCI_ROOT_BRIDGE_INSTANCE     *RootBridge,
+  IN  PCI_RESOURCE_TYPE            ResourceType
+  );
+
 extern EFI_METRONOME_ARCH_PROTOCOL *mMetronome;
 extern EFI_CPU_IO2_PROTOCOL        *mCpuIo;
 #endif
diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostResource.h b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostResource.h
index 8612c0c3251b..a6c3739db368 100644
--- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostResource.h
+++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostResource.h
@@ -38,6 +38,9 @@ typedef enum {
 
 typedef struct {
   PCI_RESOURCE_TYPE Type;
+  //
+  // Base is a host address
+  //
   UINT64            Base;
   UINT64            Length;
   UINT64            Alignment;
diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c
index 1494848c3e8c..8b71363ea4e5 100644
--- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c
+++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c
@@ -33,6 +33,39 @@ EFI_EVENT                   mIoMmuEvent;
 VOID                        *mIoMmuRegistration;
 
 /**
+  This routine gets translation offset from a root bridge instance by resource type.
+
+  @param RootBridge The Root Bridge Instance for the resources.
+  @param ResourceType The Resource Type of the translation offset.
+
+  @retval The Translation Offset of the specified resource.
+**/
+UINT64
+GetTranslationByResourceType (
+  IN  PCI_ROOT_BRIDGE_INSTANCE     *RootBridge,
+  IN  PCI_RESOURCE_TYPE            ResourceType
+  )
+{
+  switch (ResourceType) {
+    case TypeIo:
+      return RootBridge->Io.Translation;
+    case TypeMem32:
+      return RootBridge->Mem.Translation;
+    case TypePMem32:
+      return RootBridge->PMem.Translation;
+    case TypeMem64:
+      return RootBridge->MemAbove4G.Translation;
+    case TypePMem64:
+      return RootBridge->PMemAbove4G.Translation;
+    case TypeBus:
+      return RootBridge->Bus.Translation;
+    default:
+      ASSERT (FALSE);
+      return 0;
+  }
+}
+
+/**
   Ensure the compatibility of an IO space descriptor with the IO aperture.
 
   The IO space descriptor can come from the GCD IO space map, or it can
@@ -366,6 +399,7 @@ InitializePciHostBridge (
   UINTN                       MemApertureIndex;
   BOOLEAN                     ResourceAssigned;
   LIST_ENTRY                  *Link;
+  UINT64                      HostAddress;
 
   RootBridges = PciHostBridgeGetRootBridges (&RootBridgeCount);
   if ((RootBridges == NULL) || (RootBridgeCount == 0)) {
@@ -411,8 +445,15 @@ InitializePciHostBridge (
     }
 
     if (RootBridges[Index].Io.Base <= RootBridges[Index].Io.Limit) {
+      //
+      // Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device address.
+      // For GCD resource manipulation, we need to use host address.
+      //
+      HostAddress = TO_HOST_ADDRESS (RootBridges[Index].Io.Base,
+        RootBridges[Index].Io.Translation);
+
       Status = AddIoSpace (
-                 RootBridges[Index].Io.Base,
+                 HostAddress,
                  RootBridges[Index].Io.Limit - RootBridges[Index].Io.Base + 1
                  );
       ASSERT_EFI_ERROR (Status);
@@ -422,7 +463,7 @@ InitializePciHostBridge (
                         EfiGcdIoTypeIo,
                         0,
                         RootBridges[Index].Io.Limit - RootBridges[Index].Io.Base + 1,
-                        &RootBridges[Index].Io.Base,
+                        &HostAddress,
                         gImageHandle,
                         NULL
                         );
@@ -443,14 +484,20 @@ InitializePciHostBridge (
 
     for (MemApertureIndex = 0; MemApertureIndex < ARRAY_SIZE (MemApertures); MemApertureIndex++) {
       if (MemApertures[MemApertureIndex]->Base <= MemApertures[MemApertureIndex]->Limit) {
+        //
+        // Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device address.
+        // For GCD resource manipulation, we need to use host address.
+        //
+        HostAddress = TO_HOST_ADDRESS (MemApertures[MemApertureIndex]->Base,
+          MemApertures[MemApertureIndex]->Translation);
         Status = AddMemoryMappedIoSpace (
-                   MemApertures[MemApertureIndex]->Base,
+                   HostAddress,
                    MemApertures[MemApertureIndex]->Limit - MemApertures[MemApertureIndex]->Base + 1,
                    EFI_MEMORY_UC
                    );
         ASSERT_EFI_ERROR (Status);
         Status = gDS->SetMemorySpaceAttributes (
-                        MemApertures[MemApertureIndex]->Base,
+                        HostAddress,
                         MemApertures[MemApertureIndex]->Limit - MemApertures[MemApertureIndex]->Base + 1,
                         EFI_MEMORY_UC
                         );
@@ -463,7 +510,7 @@ InitializePciHostBridge (
                           EfiGcdMemoryTypeMemoryMappedIo,
                           0,
                           MemApertures[MemApertureIndex]->Limit - MemApertures[MemApertureIndex]->Base + 1,
-                          &MemApertures[MemApertureIndex]->Base,
+                          &HostAddress,
                           gImageHandle,
                           NULL
                           );
@@ -654,6 +701,11 @@ AllocateResource (
   if (BaseAddress < Limit) {
     //
     // Have to make sure Aligment is handled since we are doing direct address allocation
+    // Strictly speaking, alignment requirement should be applied to device
+    // address instead of host address which is used in GCD manipulation below,
+    // but as we restrict the alignment of Translation to be larger than any BAR
+    // alignment in the root bridge, we can simplify the situation and consider
+    // the same alignment requirement is also applied to host address.
     //
     BaseAddress = ALIGN_VALUE (BaseAddress, LShiftU64 (1, BitsOfAlignment));
 
@@ -721,6 +773,7 @@ NotifyPhase (
   PCI_RESOURCE_TYPE                     Index2;
   BOOLEAN                               ResNodeHandled[TypeMax];
   UINT64                                MaxAlignment;
+  UINT64                                Translation;
 
   HostBridge = PCI_HOST_BRIDGE_FROM_THIS (This);
 
@@ -822,14 +875,43 @@ NotifyPhase (
           BitsOfAlignment = LowBitSet64 (Alignment + 1);
           BaseAddress = MAX_UINT64;
 
+          //
+          // RESTRICTION: To simplify the situation, we require the alignment of
+          // Translation must be larger than any BAR alignment in the same root
+          // bridge, so that resource allocation alignment can be applied to
+          // both device address and host address.
+          //
+          Translation = GetTranslationByResourceType (RootBridge, Index);
+          if ((Translation & Alignment) != 0) {
+            DEBUG ((DEBUG_ERROR, "[%a:%d] Translation %lx is not aligned to %lx!\n",
+              __FUNCTION__, __LINE__, Translation, Alignment
+              ));
+            ASSERT ((Translation & Alignment) == 0);
+            //
+            // This may be caused by too large alignment or too small
+            // Translation; pick the 1st possibility and return out of resource,
+            // which can also go thru the same process for out of resource
+            // outside the loop.
+            //
+            ReturnStatus = EFI_OUT_OF_RESOURCES;
+            continue;
+          }
+
           switch (Index) {
           case TypeIo:
+            //
+            // Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device address.
+            // For AllocateResource is manipulating GCD resource, we need to use
+            // host address here.
+            //
             BaseAddress = AllocateResource (
                             FALSE,
                             RootBridge->ResAllocNode[Index].Length,
                             MIN (15, BitsOfAlignment),
-                            ALIGN_VALUE (RootBridge->Io.Base, Alignment + 1),
-                            RootBridge->Io.Limit
+                            TO_HOST_ADDRESS (ALIGN_VALUE (RootBridge->Io.Base, Alignment + 1),
+                              RootBridge->Io.Translation),
+                            TO_HOST_ADDRESS (RootBridge->Io.Limit,
+                              RootBridge->Io.Translation)
                             );
             break;
 
@@ -838,8 +920,10 @@ NotifyPhase (
                             TRUE,
                             RootBridge->ResAllocNode[Index].Length,
                             MIN (63, BitsOfAlignment),
-                            ALIGN_VALUE (RootBridge->MemAbove4G.Base, Alignment + 1),
-                            RootBridge->MemAbove4G.Limit
+                            TO_HOST_ADDRESS (ALIGN_VALUE (RootBridge->MemAbove4G.Base, Alignment + 1),
+                              RootBridge->MemAbove4G.Translation),
+                            TO_HOST_ADDRESS (RootBridge->MemAbove4G.Limit,
+                              RootBridge->MemAbove4G.Translation)
                             );
             if (BaseAddress != MAX_UINT64) {
               break;
@@ -853,8 +937,10 @@ NotifyPhase (
                             TRUE,
                             RootBridge->ResAllocNode[Index].Length,
                             MIN (31, BitsOfAlignment),
-                            ALIGN_VALUE (RootBridge->Mem.Base, Alignment + 1),
-                            RootBridge->Mem.Limit
+                            TO_HOST_ADDRESS (ALIGN_VALUE (RootBridge->Mem.Base, Alignment + 1),
+                              RootBridge->Mem.Translation),
+                            TO_HOST_ADDRESS (RootBridge->Mem.Limit,
+                              RootBridge->Mem.Translation)
                             );
             break;
 
@@ -863,8 +949,10 @@ NotifyPhase (
                             TRUE,
                             RootBridge->ResAllocNode[Index].Length,
                             MIN (63, BitsOfAlignment),
-                            ALIGN_VALUE (RootBridge->PMemAbove4G.Base, Alignment + 1),
-                            RootBridge->PMemAbove4G.Limit
+                            TO_HOST_ADDRESS (ALIGN_VALUE (RootBridge->PMemAbove4G.Base, Alignment + 1),
+                              RootBridge->PMemAbove4G.Translation),
+                            TO_HOST_ADDRESS (RootBridge->PMemAbove4G.Limit,
+                              RootBridge->PMemAbove4G.Translation)
                             );
             if (BaseAddress != MAX_UINT64) {
               break;
@@ -877,8 +965,10 @@ NotifyPhase (
                             TRUE,
                             RootBridge->ResAllocNode[Index].Length,
                             MIN (31, BitsOfAlignment),
-                            ALIGN_VALUE (RootBridge->PMem.Base, Alignment + 1),
-                            RootBridge->PMem.Limit
+                            TO_HOST_ADDRESS (ALIGN_VALUE (RootBridge->PMem.Base, Alignment + 1),
+                              RootBridge->PMem.Translation),
+                            TO_HOST_ADDRESS (RootBridge->PMem.Limit,
+                              RootBridge->PMem.Translation)
                             );
             break;
 
@@ -1421,7 +1511,14 @@ GetProposedResources (
           Descriptor->Desc                  = ACPI_ADDRESS_SPACE_DESCRIPTOR;
           Descriptor->Len                   = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;;
           Descriptor->GenFlag               = 0;
-          Descriptor->AddrRangeMin          = RootBridge->ResAllocNode[Index].Base;
+          //
+          // AddrRangeMin in Resource Descriptor here should be device address
+          // instead of host address, or else PCI bus driver cannot set correct
+          // address into PCI BAR registers.
+          // Base in ResAllocNode is a host address, so conversion is needed.
+          //
+          Descriptor->AddrRangeMin          = TO_DEVICE_ADDRESS (RootBridge->ResAllocNode[Index].Base,
+            GetTranslationByResourceType (RootBridge, Index));
           Descriptor->AddrRangeMax          = 0;
           Descriptor->AddrTranslationOffset = (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : PCI_RESOURCE_LESS;
           Descriptor->AddrLen               = RootBridge->ResAllocNode[Index].Length;
diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
index dc06c16dc038..5764c2f49f92 100644
--- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
+++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -86,12 +86,38 @@ CreateRootBridge (
           (Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0 ? L"CombineMemPMem " : L"",
           (Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE) != 0 ? L"Mem64Decode" : L""
           ));
-  DEBUG ((EFI_D_INFO, "           Bus: %lx - %lx\n", Bridge->Bus.Base, Bridge->Bus.Limit));
-  DEBUG ((EFI_D_INFO, "            Io: %lx - %lx\n", Bridge->Io.Base, Bridge->Io.Limit));
-  DEBUG ((EFI_D_INFO, "           Mem: %lx - %lx\n", Bridge->Mem.Base, Bridge->Mem.Limit));
-  DEBUG ((EFI_D_INFO, "    MemAbove4G: %lx - %lx\n", Bridge->MemAbove4G.Base, Bridge->MemAbove4G.Limit));
-  DEBUG ((EFI_D_INFO, "          PMem: %lx - %lx\n", Bridge->PMem.Base, Bridge->PMem.Limit));
-  DEBUG ((EFI_D_INFO, "   PMemAbove4G: %lx - %lx\n", Bridge->PMemAbove4G.Base, Bridge->PMemAbove4G.Limit));
+  DEBUG ((
+    EFI_D_INFO, "           Bus: %lx - %lx Translation=%lx\n",
+    Bridge->Bus.Base, Bridge->Bus.Limit, Bridge->Bus.Translation
+    ));
+  //
+  // Translation for bus is not supported.
+  //
+  ASSERT (Bridge->Bus.Translation == 0);
+  if (Bridge->Bus.Translation != 0) {
+    return NULL;
+  }
+
+  DEBUG ((
+    DEBUG_INFO, "            Io: %lx - %lx Translation=%lx\n",
+    Bridge->Io.Base, Bridge->Io.Limit, Bridge->Io.Translation
+    ));
+  DEBUG ((
+    DEBUG_INFO, "           Mem: %lx - %lx Translation=%lx\n",
+    Bridge->Mem.Base, Bridge->Mem.Limit, Bridge->Mem.Translation
+    ));
+  DEBUG ((
+    DEBUG_INFO, "    MemAbove4G: %lx - %lx Translation=%lx\n",
+    Bridge->MemAbove4G.Base, Bridge->MemAbove4G.Limit, Bridge->MemAbove4G.Translation
+    ));
+  DEBUG ((
+    DEBUG_INFO, "          PMem: %lx - %lx Translation=%lx\n",
+    Bridge->PMem.Base, Bridge->PMem.Limit, Bridge->PMem.Translation
+    ));
+  DEBUG ((
+    DEBUG_INFO, "   PMemAbove4G: %lx - %lx Translation=%lx\n",
+    Bridge->PMemAbove4G.Base, Bridge->PMemAbove4G.Limit, Bridge->PMemAbove4G.Translation
+    ));
 
   //
   // Make sure Mem and MemAbove4G apertures are valid
@@ -206,7 +232,12 @@ CreateRootBridge (
     }
     RootBridge->ResAllocNode[Index].Type     = Index;
     if (Bridge->ResourceAssigned && (Aperture->Limit >= Aperture->Base)) {
-      RootBridge->ResAllocNode[Index].Base   = Aperture->Base;
+      //
+      // Base in ResAllocNode is a host address, while Base in Aperture is a
+      // device address.
+      //
+      RootBridge->ResAllocNode[Index].Base   = TO_HOST_ADDRESS (Aperture->Base,
+        Aperture->Translation);
       RootBridge->ResAllocNode[Index].Length = Aperture->Limit - Aperture->Base + 1;
       RootBridge->ResAllocNode[Index].Status = ResAllocated;
     } else {
@@ -404,6 +435,40 @@ RootBridgeIoCheckParameter (
 }
 
 /**
+  Use address to match apertures of memory type and then get the corresponding
+  translation.
+
+  @param RootBridge              The root bridge instance.
+  @param Address                 The address used to match aperture.
+  @param Translation             Pointer containing the output translation.
+
+  @return EFI_SUCCESS            Get translation successfully.
+  @return EFI_INVALID_PARAMETER  No matched memory aperture; the input Address
+                                 must be invalid.
+**/
+EFI_STATUS
+RootBridgeIoGetMemTranslationByAddress (
+  IN PCI_ROOT_BRIDGE_INSTANCE               *RootBridge,
+  IN UINT64                                 Address,
+  IN OUT UINT64                             *Translation
+  )
+{
+  if (Address >= RootBridge->Mem.Base && Address <= RootBridge->Mem.Limit) {
+    *Translation = RootBridge->Mem.Translation;
+  } else if (Address >= RootBridge->PMem.Base && Address <= RootBridge->PMem.Limit) {
+    *Translation = RootBridge->PMem.Translation;
+  } else if (Address >= RootBridge->MemAbove4G.Base && Address <= RootBridge->MemAbove4G.Limit) {
+    *Translation = RootBridge->MemAbove4G.Translation;
+  } else if (Address >= RootBridge->PMemAbove4G.Base && Address <= RootBridge->PMemAbove4G.Limit) {
+    *Translation = RootBridge->PMemAbove4G.Translation;
+  } else {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
   Polls an address in memory mapped I/O space until an exit condition is met,
   or a timeout occurs.
 
@@ -658,13 +723,25 @@ RootBridgeIoMemRead (
   )
 {
   EFI_STATUS                             Status;
+  PCI_ROOT_BRIDGE_INSTANCE               *RootBridge;
+  UINT64                                 Translation;
 
   Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address,
                                        Count, Buffer);
   if (EFI_ERROR (Status)) {
     return Status;
   }
-  return mCpuIo->Mem.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Address, Count, Buffer);
+
+  RootBridge = ROOT_BRIDGE_FROM_THIS (This);
+  Status = RootBridgeIoGetMemTranslationByAddress (RootBridge, Address, &Translation);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  // Address passed to CpuIo->Mem.Read needs to be a host address instead of
+  // device address.
+  return mCpuIo->Mem.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width,
+      TO_HOST_ADDRESS (Address, Translation), Count, Buffer);
 }
 
 /**
@@ -705,13 +782,25 @@ RootBridgeIoMemWrite (
   )
 {
   EFI_STATUS                             Status;
+  PCI_ROOT_BRIDGE_INSTANCE               *RootBridge;
+  UINT64                                 Translation;
 
   Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address,
                                        Count, Buffer);
   if (EFI_ERROR (Status)) {
     return Status;
   }
-  return mCpuIo->Mem.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Address, Count, Buffer);
+
+  RootBridge = ROOT_BRIDGE_FROM_THIS (This);
+  Status = RootBridgeIoGetMemTranslationByAddress (RootBridge, Address, &Translation);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  // Address passed to CpuIo->Mem.Write needs to be a host address instead of
+  // device address.
+  return mCpuIo->Mem.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width,
+      TO_HOST_ADDRESS (Address, Translation), Count, Buffer);
 }
 
 /**
@@ -746,6 +835,8 @@ RootBridgeIoIoRead (
   )
 {
   EFI_STATUS                                    Status;
+  PCI_ROOT_BRIDGE_INSTANCE                      *RootBridge;
+
   Status = RootBridgeIoCheckParameter (
              This, IoOperation, Width,
              Address, Count, Buffer
@@ -753,7 +844,13 @@ RootBridgeIoIoRead (
   if (EFI_ERROR (Status)) {
     return Status;
   }
-  return mCpuIo->Io.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Address, Count, Buffer);
+
+  RootBridge = ROOT_BRIDGE_FROM_THIS (This);
+
+  // Address passed to CpuIo->Io.Read needs to be a host address instead of
+  // device address.
+  return mCpuIo->Io.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width,
+      TO_HOST_ADDRESS (Address, RootBridge->Io.Translation), Count, Buffer);
 }
 
 /**
@@ -788,6 +885,8 @@ RootBridgeIoIoWrite (
   )
 {
   EFI_STATUS                                    Status;
+  PCI_ROOT_BRIDGE_INSTANCE                      *RootBridge;
+
   Status = RootBridgeIoCheckParameter (
              This, IoOperation, Width,
              Address, Count, Buffer
@@ -795,7 +894,13 @@ RootBridgeIoIoWrite (
   if (EFI_ERROR (Status)) {
     return Status;
   }
-  return mCpuIo->Io.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Address, Count, Buffer);
+
+  RootBridge = ROOT_BRIDGE_FROM_THIS (This);
+
+  // Address passed to CpuIo->Io.Write needs to be a host address instead of
+  // device address.
+  return mCpuIo->Io.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width,
+      TO_HOST_ADDRESS (Address, RootBridge->Io.Translation), Count, Buffer);
 }
 
 /**
@@ -1615,9 +1720,17 @@ RootBridgeIoConfiguration (
 
     Descriptor->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
     Descriptor->Len  = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
+    // According to UEFI 2.7, RootBridgeIo->Configuration should return address
+    // range in CPU view (host address), and ResAllocNode->Base is already a CPU
+    // view address (host address).
     Descriptor->AddrRangeMin  = ResAllocNode->Base;
     Descriptor->AddrRangeMax  = ResAllocNode->Base + ResAllocNode->Length - 1;
     Descriptor->AddrLen       = ResAllocNode->Length;
+    Descriptor->AddrTranslationOffset = GetTranslationByResourceType (
+      RootBridge,
+      ResAllocNode->Type
+      );
+
     switch (ResAllocNode->Type) {
 
     case TypeIo:
-- 
2.7.4

[PATCH v7 5/6] MdeModulePkg/PciBus: convert host address to device address

[Heyi Guo]

According to UEFI spec 2.7, PciRootBridgeIo->Configuration() should
return host address (CPU view ddress) rather than device address
(PCI view address), so in function GetMmioAddressTranslationOffset we
need to convert the range to device address before comparing.

And device address = host address + translation offset.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Signed-off-by: Yi Li <phoenix.liyi@huawei.com>
Reviewed-by: Ni Ruiyu <ruiyu.ni@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
---
 MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c
index 190f4b0dc7ed..fef3eceb7f62 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c
@@ -1812,10 +1812,14 @@ GetMmioAddressTranslationOffset (
     return (UINT64) -1;
   }
 
+  // According to UEFI 2.7, EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL::Configuration()
+  // returns host address instead of device address, while AddrTranslationOffset
+  // is not zero, and device address = host address + AddrTranslationOffset, so
+  // we convert host address to device address for range compare.
   while (Configuration->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
     if ((Configuration->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) &&
-        (Configuration->AddrRangeMin <= AddrRangeMin) &&
-        (Configuration->AddrRangeMin + Configuration->AddrLen >= AddrRangeMin + AddrLen)
+        (Configuration->AddrRangeMin + Configuration->AddrTranslationOffset <= AddrRangeMin) &&
+        (Configuration->AddrRangeMin + Configuration->AddrLen + Configuration->AddrTranslationOffset >= AddrRangeMin + AddrLen)
         ) {
       return Configuration->AddrTranslationOffset;
     }
-- 
2.7.4

[PATCH v7 6/6] MdeModulePkg/PciBus: return CPU address for GetBarAttributes

[Heyi Guo]

According to UEFI spec 2.7, PciIo->GetBarAttributes should return host
address (CPU view ddress) rather than device address (PCI view
address), and
device address = host address + address translation offset,
so we subtract translation from device address before returning.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Signed-off-by: Yi Li <phoenix.liyi@huawei.com>
Reviewed-by: Ni Ruiyu <ruiyu.ni@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
---
 MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c
index fef3eceb7f62..62179eb44bbd 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c
@@ -1972,6 +1972,10 @@ PciIoGetBarAttributes (
         return EFI_UNSUPPORTED;
       }
     }
+
+    // According to UEFI spec 2.7, we need return host address for
+    // PciIo->GetBarAttributes, and host address = device address - translation.
+    Descriptor->AddrRangeMin -= Descriptor->AddrTranslationOffset;
   }
 
   return EFI_SUCCESS;
-- 
2.7.4

Re: [PATCH v7 0/6] Add translation support to generic PciHostBridge

[Ard Biesheuvel]

On 15 March 2018 at 06:03, Heyi Guo <heyi.guo@linaro.org> wrote:
> Code can also be found here:
> https://github.com/iwishguo/edk2/tree/patch-pci-host-bridge-v7
>
> v7:
> - Patch 4: implement 1 comments from Ray.
>


Thanks Heyi.

I will merge this v7 by the end of today unless anyone objects.

Maurice, Prince, Benjamin: you have had ample time to respond to the
Coreboot changes. I am going to assume that you have no objections
unless you raise them today.

Thanks all,
Ard.



> v6:
> - Patch 1, 2: implement 3 comments from Laszlo.
> - Patch 4: implement 3 comments from Ray.
>
> Patch v5 inherits the code from RFC v4; we don't restart the version number for
> RFC to PATCH change.
>
> v5:
> - Patch 4/6: Modify the code according to the comments from Ray.
> - Patch 1/6 and 2/6 are totally new. They add initialization for all fields of
>   PCI_ROOT_BRIDGE_APERTURE temporary variables in PciHostBridgeLib instances, so
>   that they will not suffer from extension of PCI_ROOT_BRIDGE_APERTURE
>   structure.
> - Generate a separate patch (3/6) for PciHostBridgeLib.h change. Though it is a
>   prerequisite for patch 4/6, it does not change the code in PciHostBridge
>   driver and won't cause any build failure or functional issue.
>
>
> v4:
> - Modify the code according to the comments from Ray, Laszlo and Ard (Please see
>   the notes of Patch 1/3)
> - Ignore translation of bus in CreateRootBridge.
>
>
> v3:
> - Keep definition of Translation consistent in EDKII code: Translation = device
>   address - host address.
> - Patch 2/2 is split into 2 patches (2/3 and 3/3).
> - Refine comments and commit messages to make the code easier to understand.
>
>
> v2:
> Changs are made according to the discussion on the mailing list, including:
>
> - PciRootBridgeIo->Configuration should return CPU view address, as well as
>   PciIo->GetBarAttributes, and Translation Offset should be equal to PCI view
>   address - CPU view address.
> - Add translation offset to PCI_ROOT_BRIDGE_APERTURE structure definition.
> - PciHostBridge driver internally used Base Address is still based on PCI view
>   address, and translation offset = CPU view - PCI view, which follows the
>   definition in ACPI, and not the same as that in UEFI spec.
>
> Cc: Ruiyu Ni <ruiyu.ni@intel.com>
> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> Cc: Star Zeng <star.zeng@intel.com>
> Cc: Eric Dong <eric.dong@intel.com>
> Cc: Laszlo Ersek <lersek@redhat.com>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Maurice Ma <maurice.ma@intel.com>
> Cc: Prince Agyeman <prince.agyeman@intel.com>
> Cc: Benjamin You <benjamin.you@intel.com>
> Cc: Jordan Justen <jordan.l.justen@intel.com>
> Cc: Anthony Perard <anthony.perard@citrix.com>
> Cc: Julien Grall <julien.grall@linaro.org>
>
>
> Heyi Guo (6):
>   CorebootPayloadPkg/PciHostBridgeLib: clear aperture vars for (re)init
>   OvmfPkg/PciHostBridgeLib: clear PCI aperture vars for (re)init
>   MdeModulePkg/PciHostBridgeLib.h: add address Translation
>   MdeModulePkg/PciHostBridgeDxe: Add support for address translation
>   MdeModulePkg/PciBus: convert host address to device address
>   MdeModulePkg/PciBus: return CPU address for GetBarAttributes
>
>  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.h              |  21 +++
>  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostResource.h            |   3 +
>  MdeModulePkg/Include/Library/PciHostBridgeLib.h                    |  19 +++
>  CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c |   7 +-
>  MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c                             |  12 +-
>  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c              | 129 ++++++++++++++++---
>  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c            | 135 ++++++++++++++++++--
>  OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c                |   4 +
>  OvmfPkg/Library/PciHostBridgeLib/XenSupport.c                      |   7 +-
>  9 files changed, 306 insertions(+), 31 deletions(-)
>
> --
> 2.7.4
>

Re: [PATCH v7 0/6] Add translation support to generic PciHostBridge

[You, Benjamin]

Hi,

I consulted Ray. I have no objection to the patch for CorebootPayloadPkg.

Thanks,

-  ben

> -----Original Message-----
> From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org]
> Sent: Thursday, March 15, 2018 4:05 PM
> To: Heyi Guo <heyi.guo@linaro.org>; Ni, Ruiyu <ruiyu.ni@intel.com>; Ma,
> Maurice <maurice.ma@intel.com>; You, Benjamin <benjamin.you@intel.com>;
> Agyeman, Prince <prince.agyeman@intel.com>
> Cc: edk2-devel@lists.01.org; Zeng, Star <star.zeng@intel.com>; Dong, Eric
> <eric.dong@intel.com>; Laszlo Ersek <lersek@redhat.com>; Kinney, Michael D
> <michael.d.kinney@intel.com>; Justen, Jordan L <jordan.l.justen@intel.com>;
> Anthony Perard <anthony.perard@citrix.com>; Julien Grall
> <julien.grall@linaro.org>
> Subject: Re: [PATCH v7 0/6] Add translation support to generic PciHostBridge
> 
> On 15 March 2018 at 06:03, Heyi Guo <heyi.guo@linaro.org> wrote:
> > Code can also be found here:
> > https://github.com/iwishguo/edk2/tree/patch-pci-host-bridge-v7
> >
> > v7:
> > - Patch 4: implement 1 comments from Ray.
> >
> 
> 
> Thanks Heyi.
> 
> I will merge this v7 by the end of today unless anyone objects.
> 
> Maurice, Prince, Benjamin: you have had ample time to respond to the
> Coreboot changes. I am going to assume that you have no objections
> unless you raise them today.
> 


> Thanks all,
> Ard.
> 
> 
> 
> > v6:
> > - Patch 1, 2: implement 3 comments from Laszlo.
> > - Patch 4: implement 3 comments from Ray.
> >
> > Patch v5 inherits the code from RFC v4; we don't restart the version number
> for
> > RFC to PATCH change.
> >
> > v5:
> > - Patch 4/6: Modify the code according to the comments from Ray.
> > - Patch 1/6 and 2/6 are totally new. They add initialization for all fields of
> >   PCI_ROOT_BRIDGE_APERTURE temporary variables in PciHostBridgeLib
> instances, so
> >   that they will not suffer from extension of PCI_ROOT_BRIDGE_APERTURE
> >   structure.
> > - Generate a separate patch (3/6) for PciHostBridgeLib.h change. Though it is a
> >   prerequisite for patch 4/6, it does not change the code in PciHostBridge
> >   driver and won't cause any build failure or functional issue.
> >
> >
> > v4:
> > - Modify the code according to the comments from Ray, Laszlo and Ard
> (Please see
> >   the notes of Patch 1/3)
> > - Ignore translation of bus in CreateRootBridge.
> >
> >
> > v3:
> > - Keep definition of Translation consistent in EDKII code: Translation = device
> >   address - host address.
> > - Patch 2/2 is split into 2 patches (2/3 and 3/3).
> > - Refine comments and commit messages to make the code easier to
> understand.
> >
> >
> > v2:
> > Changs are made according to the discussion on the mailing list, including:
> >
> > - PciRootBridgeIo->Configuration should return CPU view address, as well as
> >   PciIo->GetBarAttributes, and Translation Offset should be equal to PCI view
> >   address - CPU view address.
> > - Add translation offset to PCI_ROOT_BRIDGE_APERTURE structure definition.
> > - PciHostBridge driver internally used Base Address is still based on PCI view
> >   address, and translation offset = CPU view - PCI view, which follows the
> >   definition in ACPI, and not the same as that in UEFI spec.
> >
> > Cc: Ruiyu Ni <ruiyu.ni@intel.com>
> > Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> > Cc: Star Zeng <star.zeng@intel.com>
> > Cc: Eric Dong <eric.dong@intel.com>
> > Cc: Laszlo Ersek <lersek@redhat.com>
> > Cc: Michael D Kinney <michael.d.kinney@intel.com>
> > Cc: Maurice Ma <maurice.ma@intel.com>
> > Cc: Prince Agyeman <prince.agyeman@intel.com>
> > Cc: Benjamin You <benjamin.you@intel.com>
> > Cc: Jordan Justen <jordan.l.justen@intel.com>
> > Cc: Anthony Perard <anthony.perard@citrix.com>
> > Cc: Julien Grall <julien.grall@linaro.org>
> >
> >
> > Heyi Guo (6):
> >   CorebootPayloadPkg/PciHostBridgeLib: clear aperture vars for (re)init
> >   OvmfPkg/PciHostBridgeLib: clear PCI aperture vars for (re)init
> >   MdeModulePkg/PciHostBridgeLib.h: add address Translation
> >   MdeModulePkg/PciHostBridgeDxe: Add support for address translation
> >   MdeModulePkg/PciBus: convert host address to device address
> >   MdeModulePkg/PciBus: return CPU address for GetBarAttributes
> >
> >  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.h              |  21 +++
> >  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostResource.h            |   3 +
> >  MdeModulePkg/Include/Library/PciHostBridgeLib.h                    |  19 +++
> >  CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c |   7
> +-
> >  MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c                             |  12 +-
> >  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c              | 129
> ++++++++++++++++---
> >  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c            | 135
> ++++++++++++++++++--
> >  OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c                |   4 +
> >  OvmfPkg/Library/PciHostBridgeLib/XenSupport.c                      |   7 +-
> >  9 files changed, 306 insertions(+), 31 deletions(-)
> >
> > --
> > 2.7.4
> >

Re: [PATCH v7 0/6] Add translation support to generic PciHostBridge

[Ard Biesheuvel]

On 15 March 2018 at 08:17, You, Benjamin <benjamin.you@intel.com> wrote:
> Hi,
>
> I consulted Ray. I have no objection to the patch for CorebootPayloadPkg.
>
> Thanks,
>
> -  ben
>
>> -----Original Message-----
>> From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org]
>> Sent: Thursday, March 15, 2018 4:05 PM
>> To: Heyi Guo <heyi.guo@linaro.org>; Ni, Ruiyu <ruiyu.ni@intel.com>; Ma,
>> Maurice <maurice.ma@intel.com>; You, Benjamin <benjamin.you@intel.com>;
>> Agyeman, Prince <prince.agyeman@intel.com>
>> Cc: edk2-devel@lists.01.org; Zeng, Star <star.zeng@intel.com>; Dong, Eric
>> <eric.dong@intel.com>; Laszlo Ersek <lersek@redhat.com>; Kinney, Michael D
>> <michael.d.kinney@intel.com>; Justen, Jordan L <jordan.l.justen@intel.com>;
>> Anthony Perard <anthony.perard@citrix.com>; Julien Grall
>> <julien.grall@linaro.org>
>> Subject: Re: [PATCH v7 0/6] Add translation support to generic PciHostBridge
>>
>> On 15 March 2018 at 06:03, Heyi Guo <heyi.guo@linaro.org> wrote:
>> > Code can also be found here:
>> > https://github.com/iwishguo/edk2/tree/patch-pci-host-bridge-v7
>> >
>> > v7:
>> > - Patch 4: implement 1 comments from Ray.
>> >
>>
>>
>> Thanks Heyi.
>>
>> I will merge this v7 by the end of today unless anyone objects.
>>
>> Maurice, Prince, Benjamin: you have had ample time to respond to the
>> Coreboot changes. I am going to assume that you have no objections
>> unless you raise them today.
>>


Series pushed as ac9b530e6b47..dc080d3b61e5

Thanks everyone,
Ard.

Re: [PATCH v7 0/6] Add translation support to generic PciHostBridge

[Laszlo Ersek]

On 03/15/18 17:02, Ard Biesheuvel wrote:
> On 15 March 2018 at 08:17, You, Benjamin <benjamin.you@intel.com> wrote:
>> Hi,
>>
>> I consulted Ray. I have no objection to the patch for CorebootPayloadPkg.
>>
>> Thanks,
>>
>> -  ben
>>
>>> -----Original Message-----
>>> From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org]
>>> Sent: Thursday, March 15, 2018 4:05 PM
>>> To: Heyi Guo <heyi.guo@linaro.org>; Ni, Ruiyu <ruiyu.ni@intel.com>; Ma,
>>> Maurice <maurice.ma@intel.com>; You, Benjamin <benjamin.you@intel.com>;
>>> Agyeman, Prince <prince.agyeman@intel.com>
>>> Cc: edk2-devel@lists.01.org; Zeng, Star <star.zeng@intel.com>; Dong, Eric
>>> <eric.dong@intel.com>; Laszlo Ersek <lersek@redhat.com>; Kinney, Michael D
>>> <michael.d.kinney@intel.com>; Justen, Jordan L <jordan.l.justen@intel.com>;
>>> Anthony Perard <anthony.perard@citrix.com>; Julien Grall
>>> <julien.grall@linaro.org>
>>> Subject: Re: [PATCH v7 0/6] Add translation support to generic PciHostBridge
>>>
>>> On 15 March 2018 at 06:03, Heyi Guo <heyi.guo@linaro.org> wrote:
>>>> Code can also be found here:
>>>> https://github.com/iwishguo/edk2/tree/patch-pci-host-bridge-v7
>>>>
>>>> v7:
>>>> - Patch 4: implement 1 comments from Ray.
>>>>
>>>
>>>
>>> Thanks Heyi.
>>>
>>> I will merge this v7 by the end of today unless anyone objects.
>>>
>>> Maurice, Prince, Benjamin: you have had ample time to respond to the
>>> Coreboot changes. I am going to assume that you have no objections
>>> unless you raise them today.
>>>
> 
> 
> Series pushed as ac9b530e6b47..dc080d3b61e5

I see you added your R-b to the OvmfPkg commit (e33305ea6c6a), so
everything is OK from my side. (The patch is good as well.)

Thanks!
Laszlo