From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.93; helo=mga11.intel.com; envelope-from=star.zeng@intel.com; receiver=edk2-devel@lists.01.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B781C2258AF09 for ; Mon, 19 Mar 2018 05:39:17 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 19 Mar 2018 05:45:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,330,1517904000"; d="scan'208";a="184070613" Received: from shwdeopenpsi068.ccr.corp.intel.com ([10.239.158.46]) by orsmga004.jf.intel.com with ESMTP; 19 Mar 2018 05:45:44 -0700 From: Star Zeng To: edk2-devel@lists.01.org Cc: Star Zeng , Ruiyu Ni , Hao Wu Date: Mon, 19 Mar 2018 20:45:42 +0800 Message-Id: <1521463542-135668-1-git-send-email-star.zeng@intel.com> X-Mailer: git-send-email 2.7.0.windows.1 Subject: [PATCH] SourceLevelDebugPkg DebugCommUsb3: Return error when debug cap is reset X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 19 Mar 2018 12:39:18 -0000 When source level debug is enabled, but debug cable is not connected, XhcResetHC() in XhciReg.c will reset the host controller, the debug capability registers will be also reset. After the code in InitializeUsbDebugHardware() sets DCE bit and LSE bit to "1" in DCCTRL, there will be DMA on 0 (the value of some debug capability registers for data transfer is 0) address buffer, fault info like below will appear when IOMMU based on VTd is enabled. VER_REG - 0x00000010 CAP_REG - 0x00D2008C40660462 ECAP_REG - 0x0000000000F050DA GSTS_REG - 0xC0000000 RTADDR_REG - 0x0000000086512000 CCMD_REG - 0x2800000000000000 FSTS_REG - 0x00000002 FECTL_REG - 0xC0000000 FEDATA_REG - 0x00000000 FEADDR_REG - 0x00000000 FEUADDR_REG - 0x00000000 FRCD_REG[0] - 0xC0000006000000A0 0000000000000000 Fault Info - 0x0000000000000000 Source - B00 D14 F00 Type - 1 (read) Reason - 6 IVA_REG - 0x0000000000000000 IOTLB_REG - 0x1200000000000000 This patch is to return error for the case. Cc: Ruiyu Ni Cc: Hao Wu Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng --- .../DebugCommunicationLibUsb3/DebugCommunicationLibUsb3Common.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/SourceLevelDebugPkg/Library/DebugCommunicationLibUsb3/DebugCommunicationLibUsb3Common.c b/SourceLevelDebugPkg/Library/DebugCommunicationLibUsb3/DebugCommunicationLibUsb3Common.c index fb9ca84fc7bc..86ecc2f9dbc7 100644 --- a/SourceLevelDebugPkg/Library/DebugCommunicationLibUsb3/DebugCommunicationLibUsb3Common.c +++ b/SourceLevelDebugPkg/Library/DebugCommunicationLibUsb3/DebugCommunicationLibUsb3Common.c @@ -673,11 +673,19 @@ InitializeUsbDebugHardware ( UINTN Index; UINT8 TotalUsb3Port; EFI_PHYSICAL_ADDRESS XhciOpRegister; + UINT32 Dcddi1; XhciOpRegister = Handle->XhciOpRegister; TotalUsb3Port = MmioRead32 (((UINTN) Handle->XhciMmioBase + XHC_HCSPARAMS1_OFFSET)) >> 24; if (Handle->Initialized == USB3DBG_NOT_ENABLED) { + Dcddi1 = XhcReadDebugReg (Handle,XHC_DC_DCDDI1); + if (Dcddi1 != (UINT32)((XHCI_DEBUG_DEVICE_VENDOR_ID << 16) | XHCI_DEBUG_DEVICE_PROTOCOL)) { + // + // The debug capability has been reset by other code, return device error. + // + return EFI_DEVICE_ERROR; + } // // If XHCI supports debug capability, hardware resource has been allocated, // but it has not been enabled, try to enable again. -- 2.7.0.windows.1