From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c05::242; helo=mail-pg0-x242.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pg0-x242.google.com (mail-pg0-x242.google.com [IPv6:2607:f8b0:400e:c05::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A5E23224BBC5E for ; Tue, 20 Mar 2018 17:57:25 -0700 (PDT) Received: by mail-pg0-x242.google.com with SMTP id s13so1340348pgn.12 for ; Tue, 20 Mar 2018 18:03:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=hwJoVDVYwkdaocm/YzWKmBcWfsOcw/EiOv8Qpdmlhr8=; b=UjqMuhWexU5/va+t4hj6+ikmx8C/0AxForQzcgqmnheHi4us6i4kQ3o9J3D1rKHHSF 8jLLut/C6bmNWDmIz+iQNoui2GOzk/GcpIKIn+Hn/enS2W1vd1XSl6o4n7QZCHaEm5fW t4vOFyUgbnPLr1VfxhRpI8DA+16XnyMEcc9sU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=hwJoVDVYwkdaocm/YzWKmBcWfsOcw/EiOv8Qpdmlhr8=; b=j09pc2+sTW6ifVgjHNeAGTm8uoz6gN6cY46etS7ayBpMaQz9TAfjuuvUBmMdr+Byxu x3k481TuxR73xF8WNHyrdL4KCfpHPOjNbtNrkyIN0UbTf/92EVc0+AxVDa0SbUwrIa5N EueUVqtw1NgrkrR/4BQH0wfUCZ3b3/U6S1yFU8Y7H/SqS/43hXT72eeVSeBOPP7SYAna dQZn1R2t4ECKxh8jq0zQCl3T/QEZvd9+SmFX35iUcqN4ZXQMqdeafWU0Yr5xvijLd8fU AcQzimfe4X0WHav5MPkWBog6q31RrPUPMNs4zUAHpT20bIqxCYz/+iYyRrOLynccBwLY HU1Q== X-Gm-Message-State: AElRT7EoNJhfwlt8HuWj47+HXvVo87isB8KbIwJzH9oOZmQGfwUvAwPI 5nPSB/sO8R6JS3Xu349UqP4o9Npp/14= X-Google-Smtp-Source: AG47ELvMeywM2Mj/W13lmfYptdR7Aa9QLXf1XRkBfxYkJsjl91JNbftzwfxJiRXBek/gBaa0EFC+xA== X-Received: by 10.98.74.143 with SMTP id c15mr15329607pfj.83.1521594235308; Tue, 20 Mar 2018 18:03:55 -0700 (PDT) Received: from localhost.localdomain ([45.56.152.100]) by smtp.gmail.com with ESMTPSA id 184sm5702491pfg.124.2018.03.20.18.03.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 20 Mar 2018 18:03:54 -0700 (PDT) From: Heyi Guo To: edk2-devel@lists.01.org Cc: Heyi Guo , Ard Biesheuvel , Leif Lindholm , Michael D Kinney , Haojian Zhuang Date: Wed, 21 Mar 2018 09:03:06 +0800 Message-Id: <1521594198-52523-1-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 2.7.4 Subject: [PATCH edk2-platforms 00/12] Hisilicon/D0x: Switch to generic PciHostBridge X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 21 Mar 2018 00:57:26 -0000 For BAR address translation support was added to edk2 generic PciHostBridge by commit 74d0a33, now we can also use it for D03/D05 platforms. This series of patches include 3 parts of change: - Preparation for the switch, moving platform specific code out of PciHostBridge driver. - Add depending libraries and protocol implementations, like PciHostBridgeLib, PciSegmentLib and CpuIo2 Protocol. - Other enhancement and refinement. Cc: Ard Biesheuvel Cc: Leif Lindholm Cc: Michael D Kinney Cc: Haojian Zhuang Heyi Guo (12): Hisilicon: Enable WARN and INFO debug message Hisilicon/D05/PlatformPciLib: fix misuse of macro Hisilicon/Pci: move ATU configuration to PcieInitDxe Hisilicon/Pci: Merge PciPlatform into PcieInit Driver Hisilicon/Pci: Move EnlargeAtuConfig0() to PcieInitDxe Hisilicon/PlatformPciLib: add segment for each root bridge Hisilicon: add PciHostBridgeLib Hisilicon: add PciCpuIo2Dxe Hisilicon: add PciSegmentLib for Hi161x Hisilicon/D0x: Switch to generic PciHostBridge driver Hisilicon: remove platform specific PciHostBridge Hisilicon/PlatformPciLib: clear redundant felds in RESOURCE_APPETURE Silicon/Hisilicon/Hisilicon.dsc.inc | 8 +- Platform/Hisilicon/D03/D03.dsc | 7 +- Platform/Hisilicon/D05/D05.dsc | 7 +- Platform/Hisilicon/D03/D03.fdf | 4 +- Platform/Hisilicon/D05/D05.fdf | 4 +- Platform/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf | 53 - Platform/Hisilicon/Library/PciHostBridgeLib/PciHostBridgeLib.inf | 51 + Silicon/Hisilicon/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf | 48 + Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf | 74 - Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf | 9 +- Silicon/Hisilicon/Hi1610/Library/Hi161xPciSegmentLib/Hi161xPciSegmentLib.inf | 36 + Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h | 528 ----- {Platform/Hisilicon/D03/Drivers/PciPlatform => Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610}/PciPlatform.h | 0 Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 13 + Silicon/Hisilicon/Include/Library/PlatformPciLib.h | 3 +- Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c | 24 +- Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c | 66 +- Platform/Hisilicon/Library/PciHostBridgeLib/PciHostBridgeLib.c | 304 +++ Silicon/Hisilicon/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.c | 557 +++++ Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c | 1659 -------------- Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 2404 -------------------- {Platform/Hisilicon/D03/Drivers/PciPlatform => Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610}/PciPlatform.c | 12 + Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.c | 7 +- Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitAtu.c | 309 +++ Silicon/Hisilicon/Hi1610/Library/Hi161xPciSegmentLib/PciSegmentLib.c | 1503 ++++++++++++ 25 files changed, 2897 insertions(+), 4793 deletions(-) delete mode 100644 Platform/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf create mode 100644 Platform/Hisilicon/Library/PciHostBridgeLib/PciHostBridgeLib.inf create mode 100644 Silicon/Hisilicon/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf delete mode 100644 Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf create mode 100644 Silicon/Hisilicon/Hi1610/Library/Hi161xPciSegmentLib/Hi161xPciSegmentLib.inf delete mode 100644 Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h rename {Platform/Hisilicon/D03/Drivers/PciPlatform => Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610}/PciPlatform.h (100%) create mode 100644 Platform/Hisilicon/Library/PciHostBridgeLib/PciHostBridgeLib.c create mode 100644 Silicon/Hisilicon/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.c delete mode 100644 Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c delete mode 100644 Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c rename {Platform/Hisilicon/D03/Drivers/PciPlatform => Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610}/PciPlatform.c (93%) create mode 100644 Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitAtu.c create mode 100644 Silicon/Hisilicon/Hi1610/Library/Hi161xPciSegmentLib/PciSegmentLib.c -- 2.7.4