From: Heyi Guo <heyi.guo@linaro.org>
To: edk2-devel@lists.01.org
Cc: Heyi Guo <heyi.guo@linaro.org>,
Ard Biesheuvel <ard.biesheuvel@linaro.org>,
Leif Lindholm <leif.lindholm@linaro.org>,
Michael D Kinney <michael.d.kinney@intel.com>
Subject: [PATCH edk2-platforms 03/12] Hisilicon/Pci: move ATU configuration to PcieInitDxe
Date: Wed, 21 Mar 2018 09:03:09 +0800 [thread overview]
Message-ID: <1521594198-52523-4-git-send-email-heyi.guo@linaro.org> (raw)
In-Reply-To: <1521594198-52523-1-git-send-email-heyi.guo@linaro.org>
This is to prepare for switching to generic PciHostBridge driver, so
we move all platform specific code to platform specific drivers, not
in PciHostBridge driver.
This patch moves ATU initialization to PcieInitDxe driver.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
---
Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf | 1 +
Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 2 +
Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 106 ---------------
Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.c | 3 +
Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitAtu.c | 141 ++++++++++++++++++++
5 files changed, 147 insertions(+), 106 deletions(-)
diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf
index 61b091f659b3..cb0a63f9a84e 100644
--- a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf
+++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf
@@ -25,6 +25,7 @@ [Defines]
[Sources]
PcieInit.c
PcieInitLib.c
+ PcieInitAtu.c
[Packages]
MdePkg/MdePkg.dec
diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h
index e96c53c4fe4e..87700ae8b9aa 100644
--- a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h
+++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h
@@ -246,4 +246,6 @@ EFI_STATUS PcieWaitLinkUp(UINT32 Port);
EFI_STATUS PcieSetDBICS2Enable(UINT32 HostBridgeNum, UINT32 Port, UINT32 Enable);
+VOID InitAtu (PCI_ROOT_BRIDGE_RESOURCE_APPETURE *Private);
+
#endif
diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
index 55b80aa4e49a..273a322ee48f 100644
--- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
+++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -633,111 +633,6 @@ UINT64 GetPcieCfgAddress (
}
-void SetAtuConfig0RW (
- PCI_ROOT_BRIDGE_INSTANCE *Private,
- UINT32 Index
- )
-{
- UINTN RbPciBase = Private->RbPciBar;
- UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 1, 1, 0, 0) - 1;
-
-
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Private->Ecam));
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(Private->Ecam) >> 32));
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit);
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0);
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0);
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_CONFIG0);
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_SHIIF_MODE);
-
- {
- UINTN i;
- for (i=0; i<0x20; i+=4) {
- DEBUG ((EFI_D_ERROR, "[%a:%d] - Base=%p value=%x\n", __FUNCTION__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i)));
- }
- }
-}
-
-void SetAtuConfig1RW (
- PCI_ROOT_BRIDGE_INSTANCE *Private,
- UINT32 Index
- )
-{
- UINTN RbPciBase = Private->RbPciBar;
- UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusLimit + 1, 0, 0, 0) - 1;
-
-
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_CONFIG1);
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Private->Ecam));
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(Private->Ecam) >> 32));
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit);
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0);
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0);
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_SHIIF_MODE);
-
- {
- UINTN i;
- for (i=0; i<0x20; i+=4) {
- DEBUG ((EFI_D_ERROR, "[%a:%d] - Base=%p value=%x\n", __FUNCTION__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i)));
- }
- }
-}
-
-void SetAtuIoRW(UINT64 RbPciBase,UINT64 IoBase,UINT64 CpuIoRegionLimit, UINT64 CpuIoRegionBase, UINT32 Index)
-{
-
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_IO);
-
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(CpuIoRegionBase));
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)CpuIoRegionBase >> 32));
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32)(CpuIoRegionLimit));
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, (UINT32)(IoBase));
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, (UINT32)((UINT64)(IoBase) >> 32));
-
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_NORMAL_MODE);
-
- {
- UINTN i;
- for (i=0; i<0x20; i+=4) {
- DEBUG ((EFI_D_ERROR, "[%a:%d] - Base=%p value=%x\n", __FUNCTION__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i)));
- }
- }
-}
-
-void SetAtuMemRW(UINT64 RbPciBase,UINT64 MemBase,UINT64 CpuMemRegionLimit, UINT64 CpuMemRegionBase, UINT32 Index)
-{
-
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_MEM);
-
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(CpuMemRegionBase));
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(CpuMemRegionBase) >> 32));
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32)(CpuMemRegionLimit));
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, (UINT32)(MemBase));
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, (UINT32)((UINT64)(MemBase) >> 32));
-
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_NORMAL_MODE);
-
- {
- UINTN i;
- for (i=0; i<0x20; i+=4) {
- DEBUG ((EFI_D_ERROR, "[%a:%d] - Base=%p value=%x\n", __FUNCTION__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i)));
- }
- }
-}
-
-VOID InitAtu (PCI_ROOT_BRIDGE_INSTANCE *Private)
-{
- SetAtuMemRW (Private->RbPciBar, Private->PciRegionBase, Private->PciRegionLimit, Private->CpuMemRegionBase, 0);
- SetAtuConfig0RW (Private, 1);
- SetAtuConfig1RW (Private, 2);
- SetAtuIoRW (Private->RbPciBar, Private->IoBase, Private->IoLimit, Private->CpuIoRegionBase, 3);
-}
-
-
BOOLEAN PcieIsLinkUp (UINT32 SocType, UINTN RbPciBar, UINTN Port)
{
UINT32 Value = 0;
@@ -860,7 +755,6 @@ RootBridgeConstructor (
Protocol->SegmentNumber = Seg;
- InitAtu (PrivateData);
Status = gBS->LocateProtocol (&gEfiMetronomeArchProtocolGuid, NULL, (VOID **)&mMetronome);
if (EFI_ERROR(Status))
diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.c b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.c
index 5fc0ead5c1d5..de297e67e2e1 100644
--- a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.c
+++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.c
@@ -17,6 +17,7 @@
#include <Library/UefiBootServicesTableLib.h>
#include <Library/PcdLib.h>
#include <Library/OemMiscLib.h>
+#include <Library/PciExpressLib.h>
#include <Library/PlatformPciLib.h>
@@ -154,6 +155,8 @@ PcieInitEntry (
DEBUG((EFI_D_ERROR, "HostBridge %d, Pcie Port %d Init Failed! \n", HostBridgeNum, Port));
}
+ InitAtu (&mResAppeture[HostBridgeNum][Port]);
+
}
}
diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitAtu.c b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitAtu.c
new file mode 100644
index 000000000000..9eb3451f7402
--- /dev/null
+++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitAtu.c
@@ -0,0 +1,141 @@
+/** @file
+*
+* Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2018, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/OemMiscLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PciExpressLib.h>
+#include <Library/PlatformPciLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include "PcieInit.h"
+
+STATIC
+UINT64
+GetPcieCfgAddress (
+ UINT64 Ecam,
+ UINTN Bus,
+ UINTN Device,
+ UINTN Function,
+ UINTN Reg
+ )
+{
+ return Ecam + PCI_EXPRESS_LIB_ADDRESS (Bus, Device, Function, Reg);
+}
+
+STATIC
+VOID
+SetAtuConfig0RW (
+ PCI_ROOT_BRIDGE_RESOURCE_APPETURE *Private,
+ UINT32 Index
+ )
+{
+ UINTN RbPciBase = Private->RbPciBar;
+ UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 1, 1, 0, 0) - 1;
+
+
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Private->Ecam));
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(Private->Ecam) >> 32));
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_CONFIG0);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_SHIIF_MODE);
+
+ {
+ UINTN i;
+ for (i=0; i<0x20; i+=4) {
+ DEBUG ((DEBUG_ERROR, "[%a:%d] - Base=%p value=%x\n", __FUNCTION__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i)));
+ }
+ }
+}
+
+void SetAtuConfig1RW (
+ PCI_ROOT_BRIDGE_RESOURCE_APPETURE *Private,
+ UINT32 Index
+ )
+{
+ UINTN RbPciBase = Private->RbPciBar;
+ UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusLimit + 1, 0, 0, 0) - 1;
+
+
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_CONFIG1);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Private->Ecam));
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(Private->Ecam) >> 32));
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_SHIIF_MODE);
+
+ {
+ UINTN i;
+ for (i=0; i<0x20; i+=4) {
+ DEBUG ((DEBUG_ERROR, "[%a:%d] - Base=%p value=%x\n", __FUNCTION__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i)));
+ }
+ }
+}
+
+void SetAtuIoRW(UINT64 RbPciBase,UINT64 IoBase,UINT64 CpuIoRegionLimit, UINT64 CpuIoRegionBase, UINT32 Index)
+{
+
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_IO);
+
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(CpuIoRegionBase));
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)CpuIoRegionBase >> 32));
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32)(CpuIoRegionLimit));
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, (UINT32)(IoBase));
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, (UINT32)((UINT64)(IoBase) >> 32));
+
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_NORMAL_MODE);
+
+ {
+ UINTN i;
+ for (i=0; i<0x20; i+=4) {
+ DEBUG ((DEBUG_ERROR, "[%a:%d] - Base=%p value=%x\n", __FUNCTION__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i)));
+ }
+ }
+}
+
+void SetAtuMemRW(UINT64 RbPciBase,UINT64 MemBase,UINT64 CpuMemRegionLimit, UINT64 CpuMemRegionBase, UINT32 Index)
+{
+
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_MEM);
+
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(CpuMemRegionBase));
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(CpuMemRegionBase) >> 32));
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32)(CpuMemRegionLimit));
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, (UINT32)(MemBase));
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, (UINT32)((UINT64)(MemBase) >> 32));
+
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_NORMAL_MODE);
+
+ {
+ UINTN i;
+ for (i=0; i<0x20; i+=4) {
+ DEBUG ((DEBUG_ERROR, "[%a:%d] - Base=%p value=%x\n", __FUNCTION__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i)));
+ }
+ }
+}
+
+VOID InitAtu (PCI_ROOT_BRIDGE_RESOURCE_APPETURE *Private)
+{
+ SetAtuMemRW (Private->RbPciBar, Private->PciRegionBase, Private->PciRegionLimit, Private->CpuMemRegionBase, 0);
+ SetAtuConfig0RW (Private, 1);
+ SetAtuConfig1RW (Private, 2);
+ SetAtuIoRW (Private->RbPciBar, Private->IoBase, Private->IoLimit, Private->CpuIoRegionBase, 3);
+}
+
--
2.7.4
next prev parent reply other threads:[~2018-03-21 0:57 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-21 1:03 [PATCH edk2-platforms 00/12] Hisilicon/D0x: Switch to generic PciHostBridge Heyi Guo
2018-03-21 1:03 ` [PATCH edk2-platforms 01/12] Hisilicon: Enable WARN and INFO debug message Heyi Guo
2018-03-21 1:03 ` [PATCH edk2-platforms 02/12] Hisilicon/D05/PlatformPciLib: fix misuse of macro Heyi Guo
2018-03-21 1:03 ` Heyi Guo [this message]
2018-03-30 15:19 ` [PATCH edk2-platforms 03/12] Hisilicon/Pci: move ATU configuration to PcieInitDxe Ard Biesheuvel
2018-03-21 1:03 ` [PATCH edk2-platforms 04/12] Hisilicon/Pci: Merge PciPlatform into PcieInit Driver Heyi Guo
2018-03-21 1:03 ` [PATCH edk2-platforms 05/12] Hisilicon/Pci: Move EnlargeAtuConfig0() to PcieInitDxe Heyi Guo
2018-03-21 1:03 ` [PATCH edk2-platforms 06/12] Hisilicon/PlatformPciLib: add segment for each root bridge Heyi Guo
2018-03-21 1:03 ` [PATCH edk2-platforms 07/12] Hisilicon: add PciHostBridgeLib Heyi Guo
2018-03-30 15:28 ` Ard Biesheuvel
2018-03-21 1:03 ` [PATCH edk2-platforms 08/12] Hisilicon: add PciCpuIo2Dxe Heyi Guo
2018-03-30 15:30 ` Ard Biesheuvel
2018-03-21 1:03 ` [PATCH edk2-platforms 09/12] Hisilicon: add PciSegmentLib for Hi161x Heyi Guo
2018-03-21 1:03 ` [PATCH edk2-platforms 10/12] Hisilicon/D0x: Switch to generic PciHostBridge driver Heyi Guo
2018-03-30 15:34 ` Ard Biesheuvel
2018-03-21 1:03 ` [PATCH edk2-platforms 11/12] Hisilicon: remove platform specific PciHostBridge Heyi Guo
2018-03-30 15:37 ` Ard Biesheuvel
2018-03-21 1:03 ` [PATCH edk2-platforms 12/12] Hisilicon/PlatformPciLib: clear redundant felds in RESOURCE_APPETURE Heyi Guo
2018-03-28 1:05 ` [PATCH edk2-platforms 00/12] Hisilicon/D0x: Switch to generic PciHostBridge Guo Heyi
2018-03-28 9:43 ` Ard Biesheuvel
2018-03-29 0:20 ` Guo Heyi
2018-03-30 15:40 ` Ard Biesheuvel
2018-03-31 1:37 ` Guo Heyi
2018-04-13 2:05 ` Guo Heyi
2018-04-13 7:19 ` Ard Biesheuvel
2018-04-16 13:57 ` Guo Heyi
2018-04-17 1:20 ` Guo Heyi
2018-04-17 1:44 ` Guo Heyi
2018-05-31 1:02 ` heyi.guo
2018-06-07 11:11 ` Ard Biesheuvel
2018-06-22 12:58 ` gary guo
2018-06-22 14:08 ` Ard Biesheuvel
2018-06-24 11:22 ` Ard Biesheuvel
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