From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c05::242; helo=mail-pg0-x242.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pg0-x242.google.com (mail-pg0-x242.google.com [IPv6:2607:f8b0:400e:c05::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 28B84225B02A4 for ; Tue, 20 Mar 2018 17:57:36 -0700 (PDT) Received: by mail-pg0-x242.google.com with SMTP id s13so1340506pgn.12 for ; Tue, 20 Mar 2018 18:04:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uiI84FaBRwWt7gvPtfuf46m3+13NwFTQtDE28cIEwic=; b=Yd9kp/myIoTSthAUfSNOqJ6riCmFN6hqqsX5YcnvFkzo8s/iIS5CgeniQVQl+rYPvs dS3dPW3luLbv0INVRrfMro4Ztnnn0kLic1992ijWrXzAmyJ8eX3kg3ceDZ0bs6+uxL/c fg17ih216GJaD7u/N4ZT5xYtc+jGg3hahL4Bk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uiI84FaBRwWt7gvPtfuf46m3+13NwFTQtDE28cIEwic=; b=lg+NRDo06uxvzFSfHy29Jfw2/fHmoZvHIiDqGk53+PB0lYz9mFNz26jPmNiwt07c9I oaCGXmjk6LNAwfoi/sTURW1n3446lMSLqMuASJ3uR9s704e/yLcFP491Jrscvkd+P90k 0/o7Ogg8R289vVeGQ9yBZC0q3SH8utg3dYYbYZntzIKnyb6fjagC/blFCl9nRfi2RV6e dAEwuT0oR+sSYhjrk8Afi8cil1EdTtK1drneqi77Dv47d6ksymRczOf4sBQ8kU8o4hKD Co0NfwUiHxCSPBd97IpZ5CNnM/SiIy7DjjL2/CJGcXfogt1JvCtDXZSEG017a1ioxLWu Qy0A== X-Gm-Message-State: AElRT7EmeUJPYltBv5IF4oWThCZOrCGEzWsSvSuz4fb/dLtIv+Je2QMQ icV7hQ+nEAhlNzXpDCgz1OpXt42CbVA= X-Google-Smtp-Source: AG47ELv2Ldf+c59iaQEtiJwoec+LsPaeCNP8aI5usaT/LRu0OqzvIvuKOQdpeRNywFXLASfRqTm2rA== X-Received: by 10.98.95.70 with SMTP id t67mr9309710pfb.200.1521594245892; Tue, 20 Mar 2018 18:04:05 -0700 (PDT) Received: from localhost.localdomain ([45.56.152.100]) by smtp.gmail.com with ESMTPSA id 184sm5702491pfg.124.2018.03.20.18.04.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 20 Mar 2018 18:04:05 -0700 (PDT) From: Heyi Guo To: edk2-devel@lists.01.org Cc: Heyi Guo Date: Wed, 21 Mar 2018 09:03:12 +0800 Message-Id: <1521594198-52523-7-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1521594198-52523-1-git-send-email-heyi.guo@linaro.org> References: <1521594198-52523-1-git-send-email-heyi.guo@linaro.org> Subject: [PATCH edk2-platforms 06/12] Hisilicon/PlatformPciLib: add segment for each root bridge X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 21 Mar 2018 00:57:36 -0000 This is to prepare for switching to generic PciHostBridge driver. We are going to create a PciHostBridgeLib instance for D0x and fetch PCI root bridge informance from PlatformPciLib, so we add Segment to PCI_ROOT_BRIDGE_RESOURCE_APPETURE along with other PCI resource information. Segment numbers are kept the same as ACPI MCFG. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Heyi Guo --- Silicon/Hisilicon/Include/Library/PlatformPciLib.h | 1 + Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c | 8 ++++++++ Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c | 16 ++++++++++++++++ 3 files changed, 25 insertions(+) diff --git a/Silicon/Hisilicon/Include/Library/PlatformPciLib.h b/Silicon/Hisilicon/Include/Library/PlatformPciLib.h index 9d28fec37546..6725a547d54f 100644 --- a/Silicon/Hisilicon/Include/Library/PlatformPciLib.h +++ b/Silicon/Hisilicon/Include/Library/PlatformPciLib.h @@ -190,6 +190,7 @@ extern UINT64 PCIE_ITS_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE]; typedef struct { + UINT32 Segment; UINT64 Ecam; UINT64 BusBase; UINT64 BusLimit; diff --git a/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c b/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c index c58118fe5e7a..3a770d17bb3d 100644 --- a/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c +++ b/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c @@ -28,6 +28,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO {// HostBridge 0 /* Port 0 */ { + 0, //Segment PCI_HB0RB0_ECAM_BASE, //ecam 0, //BusBase 31, //BusLimit @@ -44,6 +45,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO }, /* Port 1 */ { + 1, //Segment PCI_HB0RB1_ECAM_BASE,//ecam 224, //BusBase 254, //BusLimit @@ -59,6 +61,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO }, /* Port 2 */ { + 2, //Segment PCI_HB0RB2_ECAM_BASE, 128, //BusBase 159, //BusLimit @@ -75,6 +78,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO /* Port 3 */ { + 3, //Segment PCI_HB0RB3_ECAM_BASE, 96, //BusBase 127, //BusLimit @@ -92,6 +96,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO {// HostBridge 1 /* Port 0 */ { + 4, //Segment PCI_HB1RB0_ECAM_BASE, 128, //BusBase 159, //BusLimit @@ -107,6 +112,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO }, /* Port 1 */ { + 5, //Segment PCI_HB1RB1_ECAM_BASE, 160, //BusBase 191, //BusLimit @@ -122,6 +128,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO }, /* Port 2 */ { + 6, //Segment PCI_HB1RB2_ECAM_BASE, 192, //BusBase 223, //BusLimit @@ -138,6 +145,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO /* Port 3 */ { + 7, //Segment PCI_HB1RB3_ECAM_BASE, 224, //BusBase 255, //BusLimit diff --git a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c index c8e20356f818..c511a0ecbb52 100644 --- a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c +++ b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c @@ -29,6 +29,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO {// HostBridge 0 /* Port 0 */ { + 0, //Segment PCI_HB0RB0_ECAM_BASE, //ecam 0x80, //BusBase 0x87, //BusLimit @@ -44,6 +45,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO }, /* Port 1 */ { + 1, //Segment PCI_HB0RB1_ECAM_BASE,//ecam 0x90, //BusBase 0x97, //BusLimit @@ -59,6 +61,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO }, /* Port 2 */ { + 2, //Segment PCI_HB0RB2_ECAM_BASE, 0x80, //BusBase 0x87, //BusLimit @@ -75,6 +78,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO /* Port 3 */ { + 3, //Segment PCI_HB0RB3_ECAM_BASE, 0xb0, //BusBase 0xb7, //BusLimit @@ -90,6 +94,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO }, /* Port 4 */ { + 4, //Segment PCI_HB0RB4_ECAM_BASE, //ecam 0x88, //BusBase 0x8f, //BusLimit @@ -105,6 +110,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO }, /* Port 5 */ { + 5, //Segment PCI_HB0RB5_ECAM_BASE,//ecam 0x0, //BusBase 0x7, //BusLimit @@ -120,6 +126,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO }, /* Port 6 */ { + 6, //Segment PCI_HB0RB6_ECAM_BASE, 0xC0, //BusBase 0xC7, //BusLimit @@ -136,6 +143,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO /* Port 7 */ { + 7, //Segment PCI_HB0RB7_ECAM_BASE, 0x90, //BusBase 0x97, //BusLimit @@ -153,6 +161,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO {// HostBridge 1 /* Port 0 */ { + 8, //Segment PCI_HB1RB0_ECAM_BASE, 0x80, //BusBase 0x87, //BusLimit @@ -168,6 +177,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO }, /* Port 1 */ { + 9, //Segment PCI_HB1RB1_ECAM_BASE, 0x90, //BusBase 0x97, //BusLimit @@ -183,6 +193,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO }, /* Port 2 */ { + 0xa, //Segment PCI_HB1RB2_ECAM_BASE, 0x10, //BusBase 0x1f, //BusLimit @@ -199,6 +210,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO /* Port 3 */ { + 0xb, //Segment PCI_HB1RB3_ECAM_BASE, 0xb0, //BusBase 0xb7, //BusLimit @@ -214,6 +226,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO }, /* Port 4 */ { + 0xc, //Segment PCI_HB1RB4_ECAM_BASE, 0x20, //BusBase 0x2f, //BusLimit @@ -229,6 +242,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO }, /* Port 5 */ { + 0xd, //Segment PCI_HB1RB5_ECAM_BASE, 0x30, //BusBase 0x3f, //BusLimit @@ -244,6 +258,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO }, /* Port 6 */ { + 0xe, //Segment PCI_HB1RB6_ECAM_BASE, 0xa8, //BusBase 0xaf, //BusLimit @@ -260,6 +275,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO /* Port 7 */ { + 0xf, //Segment PCI_HB1RB7_ECAM_BASE, 0xb8, //BusBase 0xbf, //BusLimit -- 2.7.4