* [platforms PATCH v2 1/4] Marvell/Armada7k8k: Remove Intel BDS dependency
2018-05-09 13:51 [platforms PATCH v2 0/4] Armada7k8k x4/x2 PCIE fix and misc improvements Marcin Wojtas
@ 2018-05-09 13:51 ` Marcin Wojtas
2018-05-09 13:51 ` [platforms PATCH v2 2/4] Marvell/Armada70x0Db: Use more generic output fd file name Marcin Wojtas
` (2 subsequent siblings)
3 siblings, 0 replies; 10+ messages in thread
From: Marcin Wojtas @ 2018-05-09 13:51 UTC (permalink / raw)
To: edk2-devel; +Cc: leif.lindholm, ard.biesheuvel, mw, jsd, jinghua, jaz
gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile is no
longer needed due to usage of generic BDS and its
presence results in build error. Remove it.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 1 -
1 file changed, 1 deletion(-)
diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
index cd58107..a147b6e 100644
--- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
+++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
@@ -236,7 +236,6 @@
# Required for Intel BDS
gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
- gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }
# ARM Generic Interrupt Controller
gArmTokenSpaceGuid.PcdGicDistributorBase|0xF0210000
--
2.7.4
^ permalink raw reply related [flat|nested] 10+ messages in thread* [platforms PATCH v2 2/4] Marvell/Armada70x0Db: Use more generic output fd file name
2018-05-09 13:51 [platforms PATCH v2 0/4] Armada7k8k x4/x2 PCIE fix and misc improvements Marcin Wojtas
2018-05-09 13:51 ` [platforms PATCH v2 1/4] Marvell/Armada7k8k: Remove Intel BDS dependency Marcin Wojtas
@ 2018-05-09 13:51 ` Marcin Wojtas
2018-05-09 16:40 ` Leif Lindholm
2018-05-09 13:51 ` [platforms PATCH v2 3/4] Marvell/Armada7k8k: Add basic sample at reset library Marcin Wojtas
2018-05-09 13:51 ` [platforms PATCH v2 4/4] Marvell/Library: ComPhyLib: Fix configuration for PCIE x4 and x2 Marcin Wojtas
3 siblings, 1 reply; 10+ messages in thread
From: Marcin Wojtas @ 2018-05-09 13:51 UTC (permalink / raw)
To: edk2-devel; +Cc: leif.lindholm, ard.biesheuvel, mw, jsd, jinghua, jaz
Unification of output file name will ease handling build scripts
(e.g. for CI purpose) when multiple board support will be added.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf b/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf
index befb107..e165d90 100644
--- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf
+++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf
@@ -24,7 +24,7 @@
#
################################################################################
-[FD.Armada70x0Db_EFI]
+[FD.Armada_EFI]
BaseAddress = 0x00000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.
Size = 0x00400000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device
ErasePolarity = 1
--
2.7.4
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [platforms PATCH v2 2/4] Marvell/Armada70x0Db: Use more generic output fd file name
2018-05-09 13:51 ` [platforms PATCH v2 2/4] Marvell/Armada70x0Db: Use more generic output fd file name Marcin Wojtas
@ 2018-05-09 16:40 ` Leif Lindholm
0 siblings, 0 replies; 10+ messages in thread
From: Leif Lindholm @ 2018-05-09 16:40 UTC (permalink / raw)
To: Marcin Wojtas; +Cc: edk2-devel, ard.biesheuvel, jsd, jinghua, jaz
On Wed, May 09, 2018 at 03:51:09PM +0200, Marcin Wojtas wrote:
> Unification of output file name will ease handling build scripts
> (e.g. for CI purpose) when multiple board support will be added.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
I have no objections to this patch, but please repost it with the set
that adds multiple board support. When you do, you can add
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf b/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf
> index befb107..e165d90 100644
> --- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf
> +++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf
> @@ -24,7 +24,7 @@
> #
> ################################################################################
>
> -[FD.Armada70x0Db_EFI]
> +[FD.Armada_EFI]
> BaseAddress = 0x00000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.
> Size = 0x00400000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device
> ErasePolarity = 1
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [platforms PATCH v2 3/4] Marvell/Armada7k8k: Add basic sample at reset library
2018-05-09 13:51 [platforms PATCH v2 0/4] Armada7k8k x4/x2 PCIE fix and misc improvements Marcin Wojtas
2018-05-09 13:51 ` [platforms PATCH v2 1/4] Marvell/Armada7k8k: Remove Intel BDS dependency Marcin Wojtas
2018-05-09 13:51 ` [platforms PATCH v2 2/4] Marvell/Armada70x0Db: Use more generic output fd file name Marcin Wojtas
@ 2018-05-09 13:51 ` Marcin Wojtas
2018-05-09 13:51 ` [platforms PATCH v2 4/4] Marvell/Library: ComPhyLib: Fix configuration for PCIE x4 and x2 Marcin Wojtas
3 siblings, 0 replies; 10+ messages in thread
From: Marcin Wojtas @ 2018-05-09 13:51 UTC (permalink / raw)
To: edk2-devel
Cc: leif.lindholm, ard.biesheuvel, mw, jsd, jinghua, jaz,
Igal Liberman
From: Igal Liberman <igall@marvell.com>
The sample at reset library adds the following functionalities:
- MvSARGetCpuFreq - Get the CPU frequency
- MvSARGetDramFreq - Get the DRAM frequency
- MvSARGetPcieClkDirection - Determine the PCIe clock direction
for two types specified in CP110 HW block. It will be needed
for proper configuration during the PCIE SerDes training.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.c | 111 ++++++++++++++++++++
Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.h | 109 +++++++++++++++++++
Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.inf | 54 ++++++++++
Silicon/Marvell/Include/Library/SampleAtResetLib.h | 57 ++++++++++
Silicon/Marvell/Marvell.dec | 3 +
5 files changed, 334 insertions(+)
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.c
new file mode 100644
index 0000000..3ebff56
--- /dev/null
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.c
@@ -0,0 +1,111 @@
+/********************************************************************************
+Copyright (C) 2018 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must Retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+* Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+Glossary - abbreviations used in Marvell SampleAtReset library implementation:
+AP - Application Processor hardware block (Armada 7k8k incorporates AP806)
+CP - South Bridge hardware blocks (Armada 7k8k incorporates CP110)
+SAR - Sample At Reset
+
+*******************************************************************************/
+
+#include <Uefi.h>
+
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/SampleAtResetLib.h>
+
+#include "Armada7k8kSampleAtResetLib.h"
+
+UINT32
+EFIAPI
+SampleAtResetGetCpuFrequency (
+ VOID
+ )
+{
+ CONST PLL_FREQUENCY_DESCRIPTION *PllFrequencies;
+ UINT32 ClockValue;
+ UINT32 Index;
+
+ ClockValue = MmioAnd32 (AP806_SAR_BASE, SAR_CLOCK_FREQUENCY_MODE_MASK);
+
+ PllFrequencies = PllFrequencyTable;
+
+ for (Index = 0; Index < SAR_MAX_OPTIONS; Index++, PllFrequencies++) {
+ if (PllFrequencies->ClockingOption == ClockValue) {
+ break;
+ }
+ }
+
+ return PllFrequencies->CpuFrequency;
+}
+
+UINT32
+EFIAPI
+SampleAtResetGetDramFrequency (
+ VOID
+ )
+{
+ CONST PLL_FREQUENCY_DESCRIPTION *PllFrequencies;
+ UINT32 ClockValue;
+ UINT32 Index;
+
+ ClockValue = MmioAnd32 (AP806_SAR_BASE, SAR_CLOCK_FREQUENCY_MODE_MASK);
+
+ PllFrequencies = PllFrequencyTable;
+
+ for (Index = 0; Index < SAR_MAX_OPTIONS; Index++, PllFrequencies++) {
+ if (PllFrequencies->ClockingOption == ClockValue) {
+ break;
+ }
+ }
+
+ return PllFrequencies->DdrFrequency;
+}
+
+UINT32
+EFIAPI
+SampleAtResetGetPcieClockDirection (
+ IN UINT32 CpIndex,
+ IN UINT32 PcieIndex
+ )
+{
+ UINT32 ClockDirection;
+
+ ASSERT (CpIndex < MAX_CP_COUNT);
+ ASSERT (PcieIndex < MAX_PCIE_CLK_TYPE_COUNT);
+
+ ClockDirection = MmioAnd32 (CP110_SAR_BASE (CpIndex),
+ PcieClockMask[CpIndex][PcieIndex] >>
+ PcieClockOffset[CpIndex][PcieIndex]);
+
+ return ClockDirection;
+}
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.h
new file mode 100644
index 0000000..323399f
--- /dev/null
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.h
@@ -0,0 +1,109 @@
+/********************************************************************************
+Copyright (C) 2018 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must Retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+* Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+Glossary - abbreviations used in Marvell SampleAtReset library implementation:
+AP - Application Processor hardware block (Armada 7k8k incorporates AP806)
+CP - South Bridge hardware blocks (Armada 7k8k incorporates CP110)
+SAR - Sample At Reset
+
+*******************************************************************************/
+
+#define SAR_MAX_OPTIONS 16
+
+#define AP806_SAR_BASE 0xf06f8200
+#define SAR_CLOCK_FREQUENCY_MODE_MASK 0x1f
+
+#define CP110_SAR_BASE(_CpIndex) (0xf2000000 + (0x2000000 * (_CpIndex)) + 0x400200)
+
+#define MAX_CP_COUNT 2
+#define MAX_PCIE_CLK_TYPE_COUNT 2
+
+#define CP0_PCIE0_CLK_OFFSET 2
+#define CP0_PCIE1_CLK_OFFSET 3
+#define CP1_PCIE0_CLK_OFFSET 0
+#define CP1_PCIE1_CLK_OFFSET 1
+#define CP0_PCIE0_CLK_MASK (1 << CP0_PCIE0_CLK_OFFSET)
+#define CP0_PCIE1_CLK_MASK (1 << CP0_PCIE1_CLK_OFFSET)
+#define CP1_PCIE0_CLK_MASK (1 << CP1_PCIE0_CLK_OFFSET)
+#define CP1_PCIE1_CLK_MASK (1 << CP1_PCIE1_CLK_OFFSET)
+
+typedef enum {
+ CPU_2000_DDR_1200_RCLK_1200 = 0x0,
+ CPU_2000_DDR_1050_RCLK_1050 = 0x1,
+ CPU_1600_DDR_800_RCLK_800 = 0x4,
+ CPU_1800_DDR_1200_RCLK_1200 = 0x6,
+ CPU_1800_DDR_1050_RCLK_1050 = 0x7,
+ CPU_1600_DDR_1050_RCLK_1050 = 0x0d,
+ CPU_1000_DDR_650_RCLK_650 = 0x13,
+ CPU_1300_DDR_800_RCLK_800 = 0x14,
+ CPU_1300_DDR_650_RCLK_650 = 0x17,
+ CPU_1200_DDR_800_RCLK_800 = 0x19,
+ CPU_1400_DDR_800_RCLK_800 = 0x1a,
+ CPU_600_DDR_800_RCLK_800 = 0x1b,
+ CPU_800_DDR_800_RCLK_800 = 0x1c,
+ CPU_1000_DDR_800_RCLK_800 = 0x1d,
+} CLOCKING_OPTIONS;
+
+typedef struct {
+ UINT32 CpuFrequency;
+ UINT32 DdrFrequency;
+ UINT32 RingFrequency;
+ CLOCKING_OPTIONS ClockingOption;
+} PLL_FREQUENCY_DESCRIPTION;
+
+STATIC CONST PLL_FREQUENCY_DESCRIPTION PllFrequencyTable[SAR_MAX_OPTIONS] = {
+ /* CPU DDR Ring [MHz] */
+ {2000, 1200, 1200, CPU_2000_DDR_1200_RCLK_1200},
+ {2000, 1050, 1050, CPU_2000_DDR_1050_RCLK_1050},
+ {1800, 1200, 1200, CPU_1800_DDR_1200_RCLK_1200},
+ {1800, 1050, 1050, CPU_1800_DDR_1050_RCLK_1050},
+ {1600, 1050, 1050, CPU_1600_DDR_1050_RCLK_1050},
+ {1300, 800 , 800 , CPU_1300_DDR_800_RCLK_800},
+ {1300, 650 , 650 , CPU_1300_DDR_650_RCLK_650},
+ {1600, 800 , 800 , CPU_1600_DDR_800_RCLK_800},
+ {1000, 650 , 650 , CPU_1000_DDR_650_RCLK_650},
+ {1200, 800 , 800 , CPU_1200_DDR_800_RCLK_800},
+ {1400, 800 , 800 , CPU_1400_DDR_800_RCLK_800},
+ {600 , 800 , 800 , CPU_600_DDR_800_RCLK_800},
+ {800 , 800 , 800 , CPU_800_DDR_800_RCLK_800},
+ {1000, 800 , 800 , CPU_1000_DDR_800_RCLK_800}
+};
+
+STATIC CONST UINT32 PcieClockMask[MAX_CP_COUNT][MAX_PCIE_CLK_TYPE_COUNT] = {
+ {CP0_PCIE0_CLK_MASK, CP0_PCIE1_CLK_MASK},
+ {CP1_PCIE0_CLK_MASK, CP1_PCIE1_CLK_MASK}
+};
+
+STATIC CONST UINT32 PcieClockOffset[MAX_CP_COUNT][MAX_PCIE_CLK_TYPE_COUNT] = {
+ {CP0_PCIE0_CLK_OFFSET, CP0_PCIE1_CLK_OFFSET},
+ {CP1_PCIE0_CLK_OFFSET, CP1_PCIE1_CLK_OFFSET}
+};
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.inf
new file mode 100644
index 0000000..5a21cde
--- /dev/null
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.inf
@@ -0,0 +1,54 @@
+# Copyright (C) 2018 Marvell International Ltd.
+#
+# Marvell BSD License Option
+#
+# If you received this File from Marvell, you may opt to use, redistribute and/or
+# modify this File under the following licensing terms.
+# Redistribution and use in source and binary forms, with or without modification,
+# are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Marvell nor the names of its contributors may be
+# used to endorse or promote products derived from this software without
+# specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+[Defines]
+ INF_VERSION = 0x00010019
+ BASE_NAME = Armada7k8kSampleAtResetLib
+ FILE_GUID = 03e022c7-9bd7-4608-aa21-379deaac2430
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SampleAtResetLib
+
+[Sources]
+ Armada7k8kSampleAtResetLib.c
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Marvell/Marvell.dec
+
+[LibraryClasses]
+ DebugLib
+ IoLib
+
+[Depex]
+ TRUE
diff --git a/Silicon/Marvell/Include/Library/SampleAtResetLib.h b/Silicon/Marvell/Include/Library/SampleAtResetLib.h
new file mode 100644
index 0000000..1be3a6a
--- /dev/null
+++ b/Silicon/Marvell/Include/Library/SampleAtResetLib.h
@@ -0,0 +1,57 @@
+/********************************************************************************
+Copyright (C) 2018 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must Retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+* Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __SAMPLE_AT_RESET_LIB_H__
+#define __SAMPLE_AT_RESET_LIB_H__
+
+UINT32
+EFIAPI
+SampleAtResetGetCpuFrequency (
+ VOID
+ );
+
+UINT32
+EFIAPI
+SampleAtResetGetDramFrequency (
+ VOID
+ );
+
+UINT32
+EFIAPI
+SampleAtResetGetPcieClockDirection (
+ IN UINT32 CpIndex,
+ IN UINT32 PcieIndex
+ );
+
+#endif /* __SAMPLE_AT_RESET_LIB_H__ */
diff --git a/Silicon/Marvell/Marvell.dec b/Silicon/Marvell/Marvell.dec
index 2eb6238..be74b4e 100644
--- a/Silicon/Marvell/Marvell.dec
+++ b/Silicon/Marvell/Marvell.dec
@@ -59,6 +59,9 @@
gMarvellFvbDxeGuid = { 0x42903750, 0x7e61, 0x4aaf, { 0x83, 0x29, 0xbf, 0x42, 0x36, 0x4e, 0x24, 0x85 } }
gMarvellSpiFlashDxeGuid = { 0x49d7fb74, 0x306d, 0x42bd, { 0x94, 0xc8, 0xc0, 0xc5, 0x4b, 0x18, 0x1d, 0xd7 } }
+[LibraryClasses]
+ SampleAtResetLib|Include/Library/SampleAtResetLib.h
+
[Protocols]
# installed as a protocol by PlatInitDxe to force ordering between DXE drivers
# that depend on the lowlevel platform initialization having been completed
--
2.7.4
^ permalink raw reply related [flat|nested] 10+ messages in thread* [platforms PATCH v2 4/4] Marvell/Library: ComPhyLib: Fix configuration for PCIE x4 and x2
2018-05-09 13:51 [platforms PATCH v2 0/4] Armada7k8k x4/x2 PCIE fix and misc improvements Marcin Wojtas
` (2 preceding siblings ...)
2018-05-09 13:51 ` [platforms PATCH v2 3/4] Marvell/Armada7k8k: Add basic sample at reset library Marcin Wojtas
@ 2018-05-09 13:51 ` Marcin Wojtas
2018-05-09 16:49 ` Leif Lindholm
3 siblings, 1 reply; 10+ messages in thread
From: Marcin Wojtas @ 2018-05-09 13:51 UTC (permalink / raw)
To: edk2-devel
Cc: leif.lindholm, ard.biesheuvel, mw, jsd, jinghua, jaz, Evan Wang
From: Evan Wang <xswang@marvell.com>
PCIE clock direction (input/output) has implications on comphy settings.
There are 2 PCIe clocks in CP110:
- Ref clock 0 for lanes 1,2 and 3
- Ref clock 1 for lanes 4 and 5
A proper handling of above had to be added, using newly introduced
sample at reset library class for Marvell SoCs.
Other than that, update HPIPE settings and the reset sequence,
which differ from one used in x1 link.
This patch fixes PCIE x4 and x2 configuration, which helps
to overcome link establishing issue for multi-lane end points.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Evan Wang <xswang@marvell.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 1 +
Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c | 216 +++++++++++++++-----
Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c | 1 +
Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h | 36 ++++
Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf | 1 +
5 files changed, 203 insertions(+), 52 deletions(-)
diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
index a147b6e..4129742 100644
--- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
+++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
@@ -36,6 +36,7 @@
ComPhyLib|Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf
MppLib|Silicon/Marvell/Library/MppLib/MppLib.inf
NorFlashInfoLib|EmbeddedPkg/Library/NorFlashInfoLib/NorFlashInfoLib.inf
+ SampleAtResetLib|Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.inf
UtmiPhyLib|Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf
DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
index 40a7b99..5c7e769 100755
--- a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
+++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
@@ -34,6 +34,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#include "ComPhyLib.h"
#include <Library/MvHwDescLib.h>
+#include <Library/SampleAtResetLib.h>
#define SD_LANE_ADDR_WIDTH 0x1000
#define HPIPE_ADDR_OFFSET 0x800
@@ -42,6 +43,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#define HPIPE_ADDR(base, Lane) (SD_ADDR(base, Lane) + HPIPE_ADDR_OFFSET)
#define COMPHY_ADDR(base, Lane) (base + COMPHY_ADDR_LANE_WIDTH * Lane)
+#define CP110_PCIE_REF_CLK_TYPE0 0
+#define CP110_PCIE_REF_CLK_TYPE12 1
+
DECLARE_A7K8K_NONDISCOVERABLE_TEMPLATE;
/*
@@ -99,11 +103,26 @@ COMPHY_MUX_DATA Cp110ComPhyPipeMuxData[] = {
STATIC
VOID
ComPhyPcieRFUConfiguration (
+ IN UINT32 Lane,
+ IN UINT32 PcieWidth,
IN EFI_PHYSICAL_ADDRESS ComPhyAddr
)
{
UINT32 Mask, Data;
+ /* Enable PCIe by4 and by2 */
+ if (Lane == 0) {
+ if (PcieWidth == 4) {
+ RegSet (ComPhyAddr + COMMON_PHY_SD_CTRL1,
+ COMMON_PHY_SD_CTRL1_PCIE_X4_EN,
+ COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK);
+ } else if (PcieWidth == 2) {
+ RegSet (ComPhyAddr + COMMON_PHY_SD_CTRL1,
+ COMMON_PHY_SD_CTRL1_PCIE_X2_EN,
+ COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK);
+ }
+ }
+
/* RFU configurations - hard reset ComPhy */
Mask = COMMON_PHY_CFG1_PWR_UP_MASK;
Data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
@@ -132,11 +151,14 @@ ComPhyPcieRFUConfiguration (
STATIC
VOID
ComPhyPciePhyConfiguration (
+ IN UINT32 Lane,
+ IN UINT32 PcieWidth,
+ IN UINT32 PcieClk,
IN EFI_PHYSICAL_ADDRESS ComPhyAddr,
IN EFI_PHYSICAL_ADDRESS HpipeAddr
)
{
- UINT32 Mask, Data, PcieClk = 0;
+ UINT32 Mask, Data;
/* Set PIPE soft reset */
Mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK;
@@ -156,13 +178,31 @@ ComPhyPciePhyConfiguration (
RegSet (HpipeAddr + HPIPE_RST_CLK_CTRL_REG, Data, Mask);
/* Set PLL ready delay for 0x2 */
- RegSet (HpipeAddr + HPIPE_CLK_SRC_LO_REG,
- 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET,
- HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK);
+ Data = HPIPE_CLK_SRC_LO_PLL_RDY_DL_DEFAULT;
+ Mask = HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK;
+ if (PcieWidth != 1) {
+ Data |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_DEFAULT |
+ HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_DEFAULT;
+ Mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK |
+ HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK;
+ }
+ RegSet (HpipeAddr + HPIPE_CLK_SRC_LO_REG, Data, Mask);
/* Set PIPE mode interface to PCIe3 - 0x1 */
- RegSet (HpipeAddr + HPIPE_CLK_SRC_HI_REG,
- 0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET, HPIPE_CLK_SRC_HI_MODE_PIPE_MASK);
+ Data = HPIPE_CLK_SRC_HI_MODE_PIPE_EN;
+ Mask = HPIPE_CLK_SRC_HI_MODE_PIPE_MASK;
+ if (PcieWidth != 1) {
+ Mask |= HPIPE_CLK_SRC_HI_LANE_STRT_MASK |
+ HPIPE_CLK_SRC_HI_LANE_MASTER_MASK |
+ HPIPE_CLK_SRC_HI_LANE_BREAK_MASK;
+ if (Lane == 0) {
+ Data |= HPIPE_CLK_SRC_HI_LANE_STRT_EN |
+ HPIPE_CLK_SRC_HI_LANE_MASTER_EN;
+ } else if (Lane == (PcieWidth - 1)) {
+ Data |= HPIPE_CLK_SRC_HI_LANE_BREAK_EN;
+ }
+ }
+ RegSet (HpipeAddr + HPIPE_CLK_SRC_HI_REG, Data, Mask);
/* Config update polarity equalization */
RegSet (HpipeAddr + HPIPE_LANE_EQ_CFG1_REG,
@@ -172,19 +212,21 @@ ComPhyPciePhyConfiguration (
RegSet (HpipeAddr + HPIPE_DFE_CTRL_28_REG,
0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET, HPIPE_DFE_CTRL_28_PIPE4_MASK);
- /* Enable PIN clock 100M_125M */
- Mask = HPIPE_MISC_CLK100M_125M_MASK;
- Data = 0x1 << HPIPE_MISC_CLK100M_125M_OFFSET;
-
/* Set PIN_TXDCLK_2X Clock Frequency Selection for outputs 500MHz clock */
- Mask |= HPIPE_MISC_TXDCLK_2X_MASK;
- Data |= 0x0 << HPIPE_MISC_TXDCLK_2X_OFFSET;
+ Mask = HPIPE_MISC_TXDCLK_2X_MASK;
+ Data = HPIPE_MISC_TXDCLK_2X_500MHZ;
/* Enable 500MHz Clock */
Mask |= HPIPE_MISC_CLK500_EN_MASK;
Data |= 0x1 << HPIPE_MISC_CLK500_EN_OFFSET;
if (PcieClk) {
+ /*
+ * Enable PIN clock 100M_125M
+ * Only if clock is output, configure the clock-source mux
+ */
+ Mask |= HPIPE_MISC_CLK100M_125M_MASK;
+ Data |= HPIPE_MISC_CLK100M_125M_EN;
/* Set reference clock comes from group 1 */
Mask |= HPIPE_MISC_REFCLK_SEL_MASK;
Data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET;
@@ -214,6 +256,13 @@ ComPhyPciePhyConfiguration (
Data |= 0x3 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
RegSet (HpipeAddr + HPIPE_PWR_PLL_REG, Data, Mask);
+ /* Ref clock alignment */
+ if (PcieWidth != 1) {
+ RegSet (HpipeAddr + HPIPE_LANE_ALIGN_REG,
+ HPIPE_LANE_ALIGN_OFF,
+ HPIPE_LANE_ALIGN_OFF_MASK);
+ }
+
/*
* Set the amount of time spent in the LoZ state - set
* for 0x7 only if the PCIe clock is output
@@ -396,7 +445,7 @@ ComPhyPcieSetAnalogParameters (
HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK;
Data = (0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET) |
(0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET) |
- (0x2 << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET);
+ (HPIPE_LANE_CFG_FOM_PRESET_VECTOR_DEFAULT);
MmioAndThenOr32 (HpipeAddr + HPIPE_LANE_EQ_REMOTE_SETTING_REG, ~Mask, Data);
/* Set phy in root complex mode */
@@ -404,37 +453,82 @@ ComPhyPcieSetAnalogParameters (
}
STATIC
-VOID
-ComPhyPciePhyPowerUp (
- IN EFI_PHYSICAL_ADDRESS HpipeAddr
-)
-{
- /* Release from PIPE soft reset */
- RegSet (HpipeAddr + HPIPE_RST_CLK_CTRL_REG,
- 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET,
- HPIPE_RST_CLK_CTRL_PIPE_RST_MASK);
-
- /* Wait 15ms - for ComPhy calibration done */
- MicroSecondDelay (15000);
- MemoryFence ();
-}
-
-STATIC
EFI_STATUS
-ComPhyPcieCheckPll (
- IN EFI_PHYSICAL_ADDRESS HpipeAddr
+ComPhyPciePhyPowerUp (
+ IN UINT32 Lane,
+ IN UINT32 PcieWidth,
+ IN EFI_PHYSICAL_ADDRESS ComPhyBase,
+ IN EFI_PHYSICAL_ADDRESS HpipeBase
)
{
EFI_STATUS Status = EFI_SUCCESS;
+ UINT8 StartLane, EndLane, Loop;
UINT32 Data;
- /* Read Lane status */
- Data = MmioRead32 (HpipeAddr + HPIPE_LANE_STATUS0_REG);
- if ((Data & HPIPE_LANE_STATUS0_PCLK_EN_MASK) == 0) {
- DEBUG((DEBUG_INFO, "ComPhy: Read from reg = %p - value = 0x%x\n",
- HpipeAddr + HPIPE_LANE_STATUS0_REG, Data));
- DEBUG((DEBUG_INFO, "ComPhy: HPIPE_LANE_STATUS0_PCLK_EN_MASK is 0\n"));
- Status = EFI_D_ERROR;
+ /*
+ * For PCIe by4 or by2 - release from reset only after finish to
+ * configure all lanes
+ */
+ if ((PcieWidth == 1) || (Lane == (PcieWidth - 1))) {
+ if (PcieWidth != 1) {
+ /* Allows writing to all lanes in one write */
+ RegSet (ComPhyBase + COMMON_PHY_SD_CTRL1,
+ COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_WR_ENABLE,
+ COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK);
+ StartLane = 0;
+ EndLane = PcieWidth;
+
+ /*
+ * Release from PIPE soft reset
+ * for PCIe by4 or by2 - release from soft reset
+ * all lanes - can't use read modify write
+ */
+ RegSet (HPIPE_ADDR (HpipeBase, 0) + HPIPE_RST_CLK_CTRL_REG,
+ HPIPE_RST_CLK_CTRL_FIXED_PCLK_WIDTH_8 | HPIPE_RST_CLK_CTRL_MODE_REFDIV_4,
+ HPIPE_RST_CLK_CTRL_CLR_ALL_MASK);
+ } else {
+ StartLane = Lane;
+ EndLane = Lane + 1;
+
+ /*
+ * Release from PIPE soft reset
+ * for PCIe by4 or by2 - release from soft reset
+ * all lanes
+ */
+ RegSet (HPIPE_ADDR (HpipeBase, Lane) + HPIPE_RST_CLK_CTRL_REG,
+ HPIPE_RST_CLK_CTRL_PIPE_RST_DISABLE,
+ HPIPE_RST_CLK_CTRL_PIPE_RST_MASK);
+ }
+
+ if (PcieWidth != 1) {
+ /* Disable writing to all lanes with one write */
+ RegSet (ComPhyBase + COMMON_PHY_SD_CTRL1,
+ COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_WR_DISABLE,
+ COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK);
+ }
+ MemoryFence ();
+
+ /* Wait 20ms until status of all lanes stabilize */
+ MicroSecondDelay (20000);
+
+ /* Make sure all lanes are UP */
+ for (Loop = StartLane; Loop < EndLane; Loop++) {
+ Data = MmioRead32 (HPIPE_ADDR (HpipeBase, Loop) + HPIPE_LANE_STATUS0_REG);
+
+ if ((Data & HPIPE_LANE_STATUS0_PCLK_EN_MASK) == 0) {
+ DEBUG ((DEBUG_ERROR,
+ "%a: Read from lane%d, reg = %p - value = 0x%x\n",
+ __FUNCTION__,
+ Loop,
+ HPIPE_ADDR (HpipeBase, Loop) + HPIPE_LANE_STATUS0_REG,
+ Data));
+ DEBUG ((DEBUG_ERROR,
+ "%a: HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n",
+ __FUNCTION__));
+ Status = EFI_D_ERROR;
+ break;
+ }
+ }
}
return Status;
@@ -443,8 +537,9 @@ ComPhyPcieCheckPll (
STATIC
EFI_STATUS
ComPhyPciePowerUp (
+ IN UINT8 ChipId,
IN UINT32 Lane,
- IN UINT32 PcieBy4,
+ IN UINT32 PcieWidth,
IN EFI_PHYSICAL_ADDRESS HpipeBase,
IN EFI_PHYSICAL_ADDRESS ComPhyBase
)
@@ -452,26 +547,36 @@ ComPhyPciePowerUp (
EFI_STATUS Status = EFI_SUCCESS;
EFI_PHYSICAL_ADDRESS HpipeAddr = HPIPE_ADDR(HpipeBase, Lane);
EFI_PHYSICAL_ADDRESS ComPhyAddr = COMPHY_ADDR(ComPhyBase, Lane);
+ UINT32 PcieClk;
+
+ /*
+ * Obtain clock direction from sample-at-reset configuration.
+ * 4th and 5th SerDes lanes can belong only to PCIE Port1 and
+ * Port2, which use different clock type specifier than Port0.
+ */
+ if (Lane == 4 || Lane == 5) {
+ PcieClk = SampleAtResetGetPcieClockDirection (ChipId, CP110_PCIE_REF_CLK_TYPE12);
+ } else {
+ PcieClk = SampleAtResetGetPcieClockDirection (ChipId, CP110_PCIE_REF_CLK_TYPE0);
+ }
+
+ DEBUG ((DEBUG_INFO, "%a: ChipId: %d PcieClk:%d\n", __FUNCTION__, ChipId, PcieClk));
DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset ComPhy\n"));
- ComPhyPcieRFUConfiguration (ComPhyAddr);
+ ComPhyPcieRFUConfiguration (Lane, PcieWidth, ComPhyAddr);
DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy configuration\n"));
- ComPhyPciePhyConfiguration (ComPhyAddr, HpipeAddr);
+ ComPhyPciePhyConfiguration (Lane, PcieWidth, PcieClk, ComPhyAddr, HpipeAddr);
DEBUG((DEBUG_INFO, "ComPhy: stage: Set analog paramters\n"));
ComPhyPcieSetAnalogParameters (HpipeAddr);
- DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy power up\n"));
+ DEBUG ((DEBUG_INFO, "%a: stage: ComPhy power up and check PLL\n", __FUNCTION__));
- ComPhyPciePhyPowerUp (HpipeAddr);
-
- DEBUG((DEBUG_INFO, "ComPhy: stage: Check PLL\n"));
-
- Status = ComPhyPcieCheckPll (HpipeAddr);
+ Status = ComPhyPciePhyPowerUp (Lane, PcieWidth, ComPhyBase, HpipeBase);
return Status;
}
@@ -1780,28 +1885,35 @@ ComPhyCp110Init (
COMPHY_MAP *PtrComPhyMap, *SerdesMap;
EFI_PHYSICAL_ADDRESS ComPhyBaseAddr, HpipeBaseAddr;
UINT32 ComPhyMaxCount, Lane;
- UINT32 PcieBy4 = 1; // Indicating if first 4 lanes set to PCIE
+ UINT32 PcieWidth = 0;
+ UINT8 ChipId;
ComPhyMaxCount = PtrChipCfg->LanesCount;
ComPhyBaseAddr = PtrChipCfg->ComPhyBaseAddr;
HpipeBaseAddr = PtrChipCfg->Hpipe3BaseAddr;
SerdesMap = PtrChipCfg->MapData;
+ ChipId = PtrChipCfg->ChipId;
/* Config Comphy mux configuration */
ComPhyMuxCp110(PtrChipCfg, SerdesMap);
/* Check if the first 4 Lanes configured as By-4 */
for (Lane = 0, PtrComPhyMap = SerdesMap; Lane < 4; Lane++, PtrComPhyMap++) {
- if (PtrComPhyMap->Type != COMPHY_TYPE_PCIE0) {
- PcieBy4 = 0;
+ if (PtrComPhyMap->Type != COMPHY_TYPE_PCIE0)
break;
- }
+ PcieWidth++;
}
for (Lane = 0, PtrComPhyMap = SerdesMap; Lane < ComPhyMaxCount;
Lane++, PtrComPhyMap++) {
DEBUG((DEBUG_INFO, "ComPhy: Initialize serdes number %d\n", Lane));
DEBUG((DEBUG_INFO, "ComPhy: Serdes Type = 0x%x\n", PtrComPhyMap->Type));
+
+ if (Lane >= 4) {
+ /* PCIe lanes above the first 4 lanes, can be only by1 */
+ PcieWidth = 1;
+ }
+
switch (PtrComPhyMap->Type) {
case COMPHY_TYPE_UNCONNECTED:
continue;
@@ -1810,7 +1922,7 @@ ComPhyCp110Init (
case COMPHY_TYPE_PCIE1:
case COMPHY_TYPE_PCIE2:
case COMPHY_TYPE_PCIE3:
- Status = ComPhyPciePowerUp(Lane, PcieBy4, HpipeBaseAddr, ComPhyBaseAddr);
+ Status = ComPhyPciePowerUp (ChipId, Lane, PcieWidth, HpipeBaseAddr, ComPhyBaseAddr);
break;
case COMPHY_TYPE_SATA0:
case COMPHY_TYPE_SATA1:
diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c
index bf21dca..b03bc35 100644
--- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c
+++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c
@@ -192,6 +192,7 @@ InitComPhyConfig (
ChipConfig->Hpipe3BaseAddr = Desc->ComPhyHpipe3BaseAddresses[Id];
ChipConfig->LanesCount = Desc->ComPhyLaneCount[Id];
ChipConfig->MuxBitCount = Desc->ComPhyMuxBitCount[Id];
+ ChipConfig->ChipId = Id;
/*
* Below macro contains variable name concatenation (used to form PCD's name).
diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
index 5899a4a..c675d74 100644
--- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
+++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
@@ -252,14 +252,17 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#define HPIPE_LANE_ALIGN_REG 0x124
#define HPIPE_LANE_ALIGN_OFF_OFFSET 12
+#define HPIPE_LANE_ALIGN_OFF (0x0 << HPIPE_LANE_ALIGN_OFF_OFFSET)
#define HPIPE_LANE_ALIGN_OFF_MASK (0x1 << HPIPE_LANE_ALIGN_OFF_OFFSET)
#define HPIPE_MISC_REG 0x13C
#define HPIPE_MISC_CLK100M_125M_OFFSET 4
+#define HPIPE_MISC_CLK100M_125M_EN (0x1 << HPIPE_MISC_CLK100M_125M_OFFSET)
#define HPIPE_MISC_CLK100M_125M_MASK (0x1 << HPIPE_MISC_CLK100M_125M_OFFSET)
#define HPIPE_MISC_ICP_FORCE_OFFSET 5
#define HPIPE_MISC_ICP_FORCE_MASK (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET)
#define HPIPE_MISC_TXDCLK_2X_OFFSET 6
+#define HPIPE_MISC_TXDCLK_2X_500MHZ (0x0 << HPIPE_MISC_TXDCLK_2X_OFFSET)
#define HPIPE_MISC_TXDCLK_2X_MASK (0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET)
#define HPIPE_MISC_CLK500_EN_OFFSET 7
#define HPIPE_MISC_CLK500_EN_MASK (0x1 << HPIPE_MISC_CLK500_EN_OFFSET)
@@ -476,30 +479,52 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#define HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET 1
#define HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK (0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET)
#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET 2
+#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_DEFAULT (0x1 << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET)
#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK (0xf << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET)
#define HPIPE_RST_CLK_CTRL_REG 0x704
+#define HPIPE_RST_CLK_CTRL_CLR_ALL_MASK MAX_UINT32
#define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0
+#define HPIPE_RST_CLK_CTRL_PIPE_RST_DISABLE (0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET)
#define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK (0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET)
#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET 2
#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET)
+#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_WIDTH_8 (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET)
+#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_WIDTH_16 (0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET)
#define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET 3
#define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK (0x1 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET)
+#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_OFFSET 4
+#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_MASK (0x3 << HPIPE_RST_CLK_CTRL_MODE_REFDIV_OFFSET)
+#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_1 (0x0 << HPIPE_RST_CLK_CTRL_MODE_REFDIV_OFFSET)
+#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_2 (0x1 << HPIPE_RST_CLK_CTRL_MODE_REFDIV_OFFSET)
+#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_4 (0x2 << HPIPE_RST_CLK_CTRL_MODE_REFDIV_OFFSET)
+#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_8 (0x3 << HPIPE_RST_CLK_CTRL_MODE_REFDIV_OFFSET)
#define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET 9
#define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK (0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET)
#define HPIPE_CLK_SRC_LO_REG 0x70c
+#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET 1
+#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_DEFAULT (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET)
+#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET)
+#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET 2
+#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_DEFAULT (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET)
+#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK (0x3 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET)
#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET 5
+#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_DEFAULT (0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET)
#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK (0x7 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET)
#define HPIPE_CLK_SRC_HI_REG 0x710
#define HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET 0
+#define HPIPE_CLK_SRC_HI_LANE_STRT_EN (0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET)
#define HPIPE_CLK_SRC_HI_LANE_STRT_MASK (0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET)
#define HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET 1
+#define HPIPE_CLK_SRC_HI_LANE_BREAK_EN (0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET)
#define HPIPE_CLK_SRC_HI_LANE_BREAK_MASK (0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET)
#define HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET 2
+#define HPIPE_CLK_SRC_HI_LANE_MASTER_EN (0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET)
#define HPIPE_CLK_SRC_HI_LANE_MASTER_MASK (0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET)
#define HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET 7
+#define HPIPE_CLK_SRC_HI_MODE_PIPE_EN (0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET)
#define HPIPE_CLK_SRC_HI_MODE_PIPE_MASK (0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET)
#define HPIPE_GLOBAL_MISC_CTRL 0x718
@@ -528,6 +553,16 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#define COMMON_SELECTOR_PIPE_OFFSET 0x144
#define COMMON_PHY_SD_CTRL1 0x148
+#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET 0
+#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_WR_ENABLE 0x0
+#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_WR_DISABLE 0x3210
+#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK 0xFFFF
+#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET 24
+#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET)
+#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET)
+#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET 25
+#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET)
+#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET)
#define COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET 26
#define COMMON_PHY_SD_CTRL1_RXAUI1_MASK (0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET)
#define COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET 27
@@ -594,6 +629,7 @@ struct _CHIP_COMPHY_CONFIG {
COMPHY_CHIP_INIT Init;
UINT32 LanesCount;
UINT32 MuxBitCount;
+ UINT8 ChipId;
};
VOID
diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf
index a1584b4..ce0af54 100644
--- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf
+++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf
@@ -50,6 +50,7 @@
DebugLib
MemoryAllocationLib
PcdLib
+ SampleAtResetLib
IoLib
[Sources.common]
--
2.7.4
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [platforms PATCH v2 4/4] Marvell/Library: ComPhyLib: Fix configuration for PCIE x4 and x2
2018-05-09 13:51 ` [platforms PATCH v2 4/4] Marvell/Library: ComPhyLib: Fix configuration for PCIE x4 and x2 Marcin Wojtas
@ 2018-05-09 16:49 ` Leif Lindholm
2018-05-21 10:54 ` Marcin Wojtas
0 siblings, 1 reply; 10+ messages in thread
From: Leif Lindholm @ 2018-05-09 16:49 UTC (permalink / raw)
To: Marcin Wojtas; +Cc: edk2-devel, ard.biesheuvel, jsd, jinghua, jaz, Evan Wang
A couple of minor style comments.
If you don't disagree, I can fix that up before pushing and you can
have Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> for 1,3-4.
On Wed, May 09, 2018 at 03:51:11PM +0200, Marcin Wojtas wrote:
> From: Evan Wang <xswang@marvell.com>
>
> PCIE clock direction (input/output) has implications on comphy settings.
> There are 2 PCIe clocks in CP110:
> - Ref clock 0 for lanes 1,2 and 3
Space after ,.
> - Ref clock 1 for lanes 4 and 5
> A proper handling of above had to be added, using newly introduced
> sample at reset library class for Marvell SoCs.
>
> Other than that, update HPIPE settings and the reset sequence,
> which differ from one used in x1 link.
>
> This patch fixes PCIE x4 and x2 configuration, which helps
> to overcome link establishing issue for multi-lane end points.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Evan Wang <xswang@marvell.com>
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> ---
> Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 1 +
> Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c | 216 +++++++++++++++-----
> Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c | 1 +
> Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h | 36 ++++
> Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf | 1 +
> 5 files changed, 203 insertions(+), 52 deletions(-)
>
> diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
> index a147b6e..4129742 100644
> --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
> +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
> @@ -36,6 +36,7 @@
> ComPhyLib|Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf
> MppLib|Silicon/Marvell/Library/MppLib/MppLib.inf
> NorFlashInfoLib|EmbeddedPkg/Library/NorFlashInfoLib/NorFlashInfoLib.inf
> + SampleAtResetLib|Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.inf
> UtmiPhyLib|Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf
>
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
> diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
> index 40a7b99..5c7e769 100755
> --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
> +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
> @@ -34,6 +34,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
>
> #include "ComPhyLib.h"
> #include <Library/MvHwDescLib.h>
> +#include <Library/SampleAtResetLib.h>
>
> #define SD_LANE_ADDR_WIDTH 0x1000
> #define HPIPE_ADDR_OFFSET 0x800
> @@ -42,6 +43,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> #define HPIPE_ADDR(base, Lane) (SD_ADDR(base, Lane) + HPIPE_ADDR_OFFSET)
> #define COMPHY_ADDR(base, Lane) (base + COMPHY_ADDR_LANE_WIDTH * Lane)
>
> +#define CP110_PCIE_REF_CLK_TYPE0 0
> +#define CP110_PCIE_REF_CLK_TYPE12 1
> +
> DECLARE_A7K8K_NONDISCOVERABLE_TEMPLATE;
>
> /*
> @@ -99,11 +103,26 @@ COMPHY_MUX_DATA Cp110ComPhyPipeMuxData[] = {
> STATIC
> VOID
> ComPhyPcieRFUConfiguration (
> + IN UINT32 Lane,
> + IN UINT32 PcieWidth,
> IN EFI_PHYSICAL_ADDRESS ComPhyAddr
> )
> {
> UINT32 Mask, Data;
>
> + /* Enable PCIe by4 and by2 */
> + if (Lane == 0) {
> + if (PcieWidth == 4) {
> + RegSet (ComPhyAddr + COMMON_PHY_SD_CTRL1,
> + COMMON_PHY_SD_CTRL1_PCIE_X4_EN,
> + COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK);
> + } else if (PcieWidth == 2) {
> + RegSet (ComPhyAddr + COMMON_PHY_SD_CTRL1,
> + COMMON_PHY_SD_CTRL1_PCIE_X2_EN,
> + COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK);
> + }
> + }
> +
> /* RFU configurations - hard reset ComPhy */
> Mask = COMMON_PHY_CFG1_PWR_UP_MASK;
> Data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
> @@ -132,11 +151,14 @@ ComPhyPcieRFUConfiguration (
> STATIC
> VOID
> ComPhyPciePhyConfiguration (
> + IN UINT32 Lane,
> + IN UINT32 PcieWidth,
> + IN UINT32 PcieClk,
> IN EFI_PHYSICAL_ADDRESS ComPhyAddr,
> IN EFI_PHYSICAL_ADDRESS HpipeAddr
> )
> {
> - UINT32 Mask, Data, PcieClk = 0;
> + UINT32 Mask, Data;
>
> /* Set PIPE soft reset */
> Mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK;
> @@ -156,13 +178,31 @@ ComPhyPciePhyConfiguration (
> RegSet (HpipeAddr + HPIPE_RST_CLK_CTRL_REG, Data, Mask);
>
> /* Set PLL ready delay for 0x2 */
> - RegSet (HpipeAddr + HPIPE_CLK_SRC_LO_REG,
> - 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET,
> - HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK);
> + Data = HPIPE_CLK_SRC_LO_PLL_RDY_DL_DEFAULT;
> + Mask = HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK;
> + if (PcieWidth != 1) {
> + Data |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_DEFAULT |
> + HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_DEFAULT;
> + Mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK |
> + HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK;
> + }
> + RegSet (HpipeAddr + HPIPE_CLK_SRC_LO_REG, Data, Mask);
>
> /* Set PIPE mode interface to PCIe3 - 0x1 */
> - RegSet (HpipeAddr + HPIPE_CLK_SRC_HI_REG,
> - 0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET, HPIPE_CLK_SRC_HI_MODE_PIPE_MASK);
> + Data = HPIPE_CLK_SRC_HI_MODE_PIPE_EN;
> + Mask = HPIPE_CLK_SRC_HI_MODE_PIPE_MASK;
> + if (PcieWidth != 1) {
> + Mask |= HPIPE_CLK_SRC_HI_LANE_STRT_MASK |
> + HPIPE_CLK_SRC_HI_LANE_MASTER_MASK |
> + HPIPE_CLK_SRC_HI_LANE_BREAK_MASK;
> + if (Lane == 0) {
> + Data |= HPIPE_CLK_SRC_HI_LANE_STRT_EN |
> + HPIPE_CLK_SRC_HI_LANE_MASTER_EN;
> + } else if (Lane == (PcieWidth - 1)) {
> + Data |= HPIPE_CLK_SRC_HI_LANE_BREAK_EN;
> + }
> + }
> + RegSet (HpipeAddr + HPIPE_CLK_SRC_HI_REG, Data, Mask);
>
> /* Config update polarity equalization */
> RegSet (HpipeAddr + HPIPE_LANE_EQ_CFG1_REG,
> @@ -172,19 +212,21 @@ ComPhyPciePhyConfiguration (
> RegSet (HpipeAddr + HPIPE_DFE_CTRL_28_REG,
> 0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET, HPIPE_DFE_CTRL_28_PIPE4_MASK);
>
> - /* Enable PIN clock 100M_125M */
> - Mask = HPIPE_MISC_CLK100M_125M_MASK;
> - Data = 0x1 << HPIPE_MISC_CLK100M_125M_OFFSET;
> -
> /* Set PIN_TXDCLK_2X Clock Frequency Selection for outputs 500MHz clock */
> - Mask |= HPIPE_MISC_TXDCLK_2X_MASK;
> - Data |= 0x0 << HPIPE_MISC_TXDCLK_2X_OFFSET;
> + Mask = HPIPE_MISC_TXDCLK_2X_MASK;
> + Data = HPIPE_MISC_TXDCLK_2X_500MHZ;
>
> /* Enable 500MHz Clock */
> Mask |= HPIPE_MISC_CLK500_EN_MASK;
> Data |= 0x1 << HPIPE_MISC_CLK500_EN_OFFSET;
>
> if (PcieClk) {
> + /*
> + * Enable PIN clock 100M_125M
> + * Only if clock is output, configure the clock-source mux
> + */
> + Mask |= HPIPE_MISC_CLK100M_125M_MASK;
> + Data |= HPIPE_MISC_CLK100M_125M_EN;
> /* Set reference clock comes from group 1 */
> Mask |= HPIPE_MISC_REFCLK_SEL_MASK;
> Data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET;
> @@ -214,6 +256,13 @@ ComPhyPciePhyConfiguration (
> Data |= 0x3 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
> RegSet (HpipeAddr + HPIPE_PWR_PLL_REG, Data, Mask);
>
> + /* Ref clock alignment */
> + if (PcieWidth != 1) {
> + RegSet (HpipeAddr + HPIPE_LANE_ALIGN_REG,
> + HPIPE_LANE_ALIGN_OFF,
> + HPIPE_LANE_ALIGN_OFF_MASK);
> + }
> +
> /*
> * Set the amount of time spent in the LoZ state - set
> * for 0x7 only if the PCIe clock is output
> @@ -396,7 +445,7 @@ ComPhyPcieSetAnalogParameters (
> HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK;
> Data = (0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET) |
> (0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET) |
> - (0x2 << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET);
> + (HPIPE_LANE_CFG_FOM_PRESET_VECTOR_DEFAULT);
> MmioAndThenOr32 (HpipeAddr + HPIPE_LANE_EQ_REMOTE_SETTING_REG, ~Mask, Data);
>
> /* Set phy in root complex mode */
> @@ -404,37 +453,82 @@ ComPhyPcieSetAnalogParameters (
> }
>
> STATIC
> -VOID
> -ComPhyPciePhyPowerUp (
> - IN EFI_PHYSICAL_ADDRESS HpipeAddr
> -)
> -{
> - /* Release from PIPE soft reset */
> - RegSet (HpipeAddr + HPIPE_RST_CLK_CTRL_REG,
> - 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET,
> - HPIPE_RST_CLK_CTRL_PIPE_RST_MASK);
> -
> - /* Wait 15ms - for ComPhy calibration done */
> - MicroSecondDelay (15000);
> - MemoryFence ();
> -}
> -
> -STATIC
> EFI_STATUS
> -ComPhyPcieCheckPll (
> - IN EFI_PHYSICAL_ADDRESS HpipeAddr
> +ComPhyPciePhyPowerUp (
> + IN UINT32 Lane,
> + IN UINT32 PcieWidth,
> + IN EFI_PHYSICAL_ADDRESS ComPhyBase,
> + IN EFI_PHYSICAL_ADDRESS HpipeBase
> )
> {
> EFI_STATUS Status = EFI_SUCCESS;
> + UINT8 StartLane, EndLane, Loop;
> UINT32 Data;
>
> - /* Read Lane status */
> - Data = MmioRead32 (HpipeAddr + HPIPE_LANE_STATUS0_REG);
> - if ((Data & HPIPE_LANE_STATUS0_PCLK_EN_MASK) == 0) {
> - DEBUG((DEBUG_INFO, "ComPhy: Read from reg = %p - value = 0x%x\n",
> - HpipeAddr + HPIPE_LANE_STATUS0_REG, Data));
> - DEBUG((DEBUG_INFO, "ComPhy: HPIPE_LANE_STATUS0_PCLK_EN_MASK is 0\n"));
> - Status = EFI_D_ERROR;
> + /*
> + * For PCIe by4 or by2 - release from reset only after finish to
> + * configure all lanes
> + */
> + if ((PcieWidth == 1) || (Lane == (PcieWidth - 1))) {
> + if (PcieWidth != 1) {
> + /* Allows writing to all lanes in one write */
> + RegSet (ComPhyBase + COMMON_PHY_SD_CTRL1,
> + COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_WR_ENABLE,
> + COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK);
> + StartLane = 0;
> + EndLane = PcieWidth;
> +
> + /*
> + * Release from PIPE soft reset
> + * for PCIe by4 or by2 - release from soft reset
> + * all lanes - can't use read modify write
> + */
> + RegSet (HPIPE_ADDR (HpipeBase, 0) + HPIPE_RST_CLK_CTRL_REG,
> + HPIPE_RST_CLK_CTRL_FIXED_PCLK_WIDTH_8 | HPIPE_RST_CLK_CTRL_MODE_REFDIV_4,
> + HPIPE_RST_CLK_CTRL_CLR_ALL_MASK);
> + } else {
> + StartLane = Lane;
> + EndLane = Lane + 1;
> +
> + /*
> + * Release from PIPE soft reset
> + * for PCIe by4 or by2 - release from soft reset
> + * all lanes
> + */
> + RegSet (HPIPE_ADDR (HpipeBase, Lane) + HPIPE_RST_CLK_CTRL_REG,
> + HPIPE_RST_CLK_CTRL_PIPE_RST_DISABLE,
> + HPIPE_RST_CLK_CTRL_PIPE_RST_MASK);
> + }
> +
> + if (PcieWidth != 1) {
> + /* Disable writing to all lanes with one write */
> + RegSet (ComPhyBase + COMMON_PHY_SD_CTRL1,
> + COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_WR_DISABLE,
> + COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK);
> + }
> + MemoryFence ();
> +
> + /* Wait 20ms until status of all lanes stabilize */
> + MicroSecondDelay (20000);
> +
> + /* Make sure all lanes are UP */
> + for (Loop = StartLane; Loop < EndLane; Loop++) {
> + Data = MmioRead32 (HPIPE_ADDR (HpipeBase, Loop) + HPIPE_LANE_STATUS0_REG);
> +
> + if ((Data & HPIPE_LANE_STATUS0_PCLK_EN_MASK) == 0) {
> + DEBUG ((DEBUG_ERROR,
> + "%a: Read from lane%d, reg = %p - value = 0x%x\n",
> + __FUNCTION__,
> + Loop,
> + HPIPE_ADDR (HpipeBase, Loop) + HPIPE_LANE_STATUS0_REG,
> + Data));
> + DEBUG ((DEBUG_ERROR,
> + "%a: HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n",
> + __FUNCTION__));
> + Status = EFI_D_ERROR;
> + break;
> + }
> + }
> }
>
> return Status;
> @@ -443,8 +537,9 @@ ComPhyPcieCheckPll (
> STATIC
> EFI_STATUS
> ComPhyPciePowerUp (
> + IN UINT8 ChipId,
> IN UINT32 Lane,
> - IN UINT32 PcieBy4,
> + IN UINT32 PcieWidth,
> IN EFI_PHYSICAL_ADDRESS HpipeBase,
> IN EFI_PHYSICAL_ADDRESS ComPhyBase
> )
> @@ -452,26 +547,36 @@ ComPhyPciePowerUp (
> EFI_STATUS Status = EFI_SUCCESS;
> EFI_PHYSICAL_ADDRESS HpipeAddr = HPIPE_ADDR(HpipeBase, Lane);
> EFI_PHYSICAL_ADDRESS ComPhyAddr = COMPHY_ADDR(ComPhyBase, Lane);
> + UINT32 PcieClk;
> +
> + /*
> + * Obtain clock direction from sample-at-reset configuration.
> + * 4th and 5th SerDes lanes can belong only to PCIE Port1 and
> + * Port2, which use different clock type specifier than Port0.
> + */
> + if (Lane == 4 || Lane == 5) {
> + PcieClk = SampleAtResetGetPcieClockDirection (ChipId, CP110_PCIE_REF_CLK_TYPE12);
> + } else {
> + PcieClk = SampleAtResetGetPcieClockDirection (ChipId, CP110_PCIE_REF_CLK_TYPE0);
> + }
> +
> + DEBUG ((DEBUG_INFO, "%a: ChipId: %d PcieClk:%d\n", __FUNCTION__, ChipId, PcieClk));
>
> DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset ComPhy\n"));
>
> - ComPhyPcieRFUConfiguration (ComPhyAddr);
> + ComPhyPcieRFUConfiguration (Lane, PcieWidth, ComPhyAddr);
>
> DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy configuration\n"));
>
> - ComPhyPciePhyConfiguration (ComPhyAddr, HpipeAddr);
> + ComPhyPciePhyConfiguration (Lane, PcieWidth, PcieClk, ComPhyAddr, HpipeAddr);
>
> DEBUG((DEBUG_INFO, "ComPhy: stage: Set analog paramters\n"));
>
> ComPhyPcieSetAnalogParameters (HpipeAddr);
>
> - DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy power up\n"));
> + DEBUG ((DEBUG_INFO, "%a: stage: ComPhy power up and check PLL\n", __FUNCTION__));
>
> - ComPhyPciePhyPowerUp (HpipeAddr);
> -
> - DEBUG((DEBUG_INFO, "ComPhy: stage: Check PLL\n"));
> -
> - Status = ComPhyPcieCheckPll (HpipeAddr);
> + Status = ComPhyPciePhyPowerUp (Lane, PcieWidth, ComPhyBase, HpipeBase);
>
> return Status;
> }
> @@ -1780,28 +1885,35 @@ ComPhyCp110Init (
> COMPHY_MAP *PtrComPhyMap, *SerdesMap;
> EFI_PHYSICAL_ADDRESS ComPhyBaseAddr, HpipeBaseAddr;
> UINT32 ComPhyMaxCount, Lane;
> - UINT32 PcieBy4 = 1; // Indicating if first 4 lanes set to PCIE
> + UINT32 PcieWidth = 0;
> + UINT8 ChipId;
>
> ComPhyMaxCount = PtrChipCfg->LanesCount;
> ComPhyBaseAddr = PtrChipCfg->ComPhyBaseAddr;
> HpipeBaseAddr = PtrChipCfg->Hpipe3BaseAddr;
> SerdesMap = PtrChipCfg->MapData;
> + ChipId = PtrChipCfg->ChipId;
>
> /* Config Comphy mux configuration */
> ComPhyMuxCp110(PtrChipCfg, SerdesMap);
>
> /* Check if the first 4 Lanes configured as By-4 */
> for (Lane = 0, PtrComPhyMap = SerdesMap; Lane < 4; Lane++, PtrComPhyMap++) {
> - if (PtrComPhyMap->Type != COMPHY_TYPE_PCIE0) {
> - PcieBy4 = 0;
> + if (PtrComPhyMap->Type != COMPHY_TYPE_PCIE0)
> break;
> - }
Please reinstate the braces ({}) for the if.
> + PcieWidth++;
> }
>
> for (Lane = 0, PtrComPhyMap = SerdesMap; Lane < ComPhyMaxCount;
> Lane++, PtrComPhyMap++) {
> DEBUG((DEBUG_INFO, "ComPhy: Initialize serdes number %d\n", Lane));
> DEBUG((DEBUG_INFO, "ComPhy: Serdes Type = 0x%x\n", PtrComPhyMap->Type));
> +
> + if (Lane >= 4) {
> + /* PCIe lanes above the first 4 lanes, can be only by1 */
> + PcieWidth = 1;
> + }
> +
> switch (PtrComPhyMap->Type) {
> case COMPHY_TYPE_UNCONNECTED:
> continue;
> @@ -1810,7 +1922,7 @@ ComPhyCp110Init (
> case COMPHY_TYPE_PCIE1:
> case COMPHY_TYPE_PCIE2:
> case COMPHY_TYPE_PCIE3:
> - Status = ComPhyPciePowerUp(Lane, PcieBy4, HpipeBaseAddr, ComPhyBaseAddr);
> + Status = ComPhyPciePowerUp (ChipId, Lane, PcieWidth, HpipeBaseAddr, ComPhyBaseAddr);
> break;
> case COMPHY_TYPE_SATA0:
> case COMPHY_TYPE_SATA1:
> diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c
> index bf21dca..b03bc35 100644
> --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c
> +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c
> @@ -192,6 +192,7 @@ InitComPhyConfig (
> ChipConfig->Hpipe3BaseAddr = Desc->ComPhyHpipe3BaseAddresses[Id];
> ChipConfig->LanesCount = Desc->ComPhyLaneCount[Id];
> ChipConfig->MuxBitCount = Desc->ComPhyMuxBitCount[Id];
> + ChipConfig->ChipId = Id;
>
> /*
> * Below macro contains variable name concatenation (used to form PCD's name).
> diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
> index 5899a4a..c675d74 100644
> --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
> +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
> @@ -252,14 +252,17 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
>
> #define HPIPE_LANE_ALIGN_REG 0x124
> #define HPIPE_LANE_ALIGN_OFF_OFFSET 12
> +#define HPIPE_LANE_ALIGN_OFF (0x0 << HPIPE_LANE_ALIGN_OFF_OFFSET)
> #define HPIPE_LANE_ALIGN_OFF_MASK (0x1 << HPIPE_LANE_ALIGN_OFF_OFFSET)
>
> #define HPIPE_MISC_REG 0x13C
> #define HPIPE_MISC_CLK100M_125M_OFFSET 4
> +#define HPIPE_MISC_CLK100M_125M_EN (0x1 << HPIPE_MISC_CLK100M_125M_OFFSET)
> #define HPIPE_MISC_CLK100M_125M_MASK (0x1 << HPIPE_MISC_CLK100M_125M_OFFSET)
> #define HPIPE_MISC_ICP_FORCE_OFFSET 5
> #define HPIPE_MISC_ICP_FORCE_MASK (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET)
> #define HPIPE_MISC_TXDCLK_2X_OFFSET 6
> +#define HPIPE_MISC_TXDCLK_2X_500MHZ (0x0 << HPIPE_MISC_TXDCLK_2X_OFFSET)
> #define HPIPE_MISC_TXDCLK_2X_MASK (0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET)
> #define HPIPE_MISC_CLK500_EN_OFFSET 7
> #define HPIPE_MISC_CLK500_EN_MASK (0x1 << HPIPE_MISC_CLK500_EN_OFFSET)
> @@ -476,30 +479,52 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> #define HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET 1
> #define HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK (0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET)
> #define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET 2
> +#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_DEFAULT (0x1 << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET)
> #define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK (0xf << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET)
>
> #define HPIPE_RST_CLK_CTRL_REG 0x704
> +#define HPIPE_RST_CLK_CTRL_CLR_ALL_MASK MAX_UINT32
> #define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0
> +#define HPIPE_RST_CLK_CTRL_PIPE_RST_DISABLE (0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET)
> #define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK (0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET)
> #define HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET 2
> #define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET)
> +#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_WIDTH_8 (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET)
> +#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_WIDTH_16 (0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET)
> #define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET 3
> #define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK (0x1 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET)
> +#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_OFFSET 4
> +#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_MASK (0x3 << HPIPE_RST_CLK_CTRL_MODE_REFDIV_OFFSET)
> +#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_1 (0x0 << HPIPE_RST_CLK_CTRL_MODE_REFDIV_OFFSET)
> +#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_2 (0x1 << HPIPE_RST_CLK_CTRL_MODE_REFDIV_OFFSET)
> +#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_4 (0x2 << HPIPE_RST_CLK_CTRL_MODE_REFDIV_OFFSET)
> +#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_8 (0x3 << HPIPE_RST_CLK_CTRL_MODE_REFDIV_OFFSET)
> #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET 9
> #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK (0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET)
>
> #define HPIPE_CLK_SRC_LO_REG 0x70c
> +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET 1
> +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_DEFAULT (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET)
> +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET)
> +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET 2
> +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_DEFAULT (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET)
> +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK (0x3 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET)
> #define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET 5
> +#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_DEFAULT (0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET)
> #define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK (0x7 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET)
>
> #define HPIPE_CLK_SRC_HI_REG 0x710
> #define HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET 0
> +#define HPIPE_CLK_SRC_HI_LANE_STRT_EN (0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET)
> #define HPIPE_CLK_SRC_HI_LANE_STRT_MASK (0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET)
> #define HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET 1
> +#define HPIPE_CLK_SRC_HI_LANE_BREAK_EN (0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET)
> #define HPIPE_CLK_SRC_HI_LANE_BREAK_MASK (0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET)
> #define HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET 2
> +#define HPIPE_CLK_SRC_HI_LANE_MASTER_EN (0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET)
> #define HPIPE_CLK_SRC_HI_LANE_MASTER_MASK (0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET)
> #define HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET 7
> +#define HPIPE_CLK_SRC_HI_MODE_PIPE_EN (0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET)
> #define HPIPE_CLK_SRC_HI_MODE_PIPE_MASK (0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET)
>
> #define HPIPE_GLOBAL_MISC_CTRL 0x718
> @@ -528,6 +553,16 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> #define COMMON_SELECTOR_PIPE_OFFSET 0x144
>
> #define COMMON_PHY_SD_CTRL1 0x148
> +#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET 0
> +#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_WR_ENABLE 0x0
> +#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_WR_DISABLE 0x3210
> +#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK 0xFFFF
> +#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET 24
> +#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET)
> +#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET)
> +#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET 25
> +#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET)
> +#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET)
> #define COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET 26
> #define COMMON_PHY_SD_CTRL1_RXAUI1_MASK (0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET)
> #define COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET 27
> @@ -594,6 +629,7 @@ struct _CHIP_COMPHY_CONFIG {
> COMPHY_CHIP_INIT Init;
> UINT32 LanesCount;
> UINT32 MuxBitCount;
> + UINT8 ChipId;
> };
>
> VOID
> diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf
> index a1584b4..ce0af54 100644
> --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf
> +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf
> @@ -50,6 +50,7 @@
> DebugLib
> MemoryAllocationLib
> PcdLib
> + SampleAtResetLib
> IoLib
>
> [Sources.common]
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [platforms PATCH v2 4/4] Marvell/Library: ComPhyLib: Fix configuration for PCIE x4 and x2
2018-05-09 16:49 ` Leif Lindholm
@ 2018-05-21 10:54 ` Marcin Wojtas
2018-05-22 11:20 ` Leif Lindholm
0 siblings, 1 reply; 10+ messages in thread
From: Marcin Wojtas @ 2018-05-21 10:54 UTC (permalink / raw)
To: Leif Lindholm; +Cc: edk2-devel-01, Ard Biesheuvel, Grzegorz Jaszczyk
Hi Leif,
2018-05-09 18:49 GMT+02:00 Leif Lindholm <leif.lindholm@linaro.org>:
> A couple of minor style comments.
>
> If you don't disagree, I can fix that up before pushing and you can
> have Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> for 1,3-4.
>
>
Yes, I would appreciate that.
Thanks,
Marcin
> On Wed, May 09, 2018 at 03:51:11PM +0200, Marcin Wojtas wrote:
> > From: Evan Wang <xswang@marvell.com>
> >
> > PCIE clock direction (input/output) has implications on comphy settings.
> > There are 2 PCIe clocks in CP110:
> > - Ref clock 0 for lanes 1,2 and 3
>
> Space after ,.
>
> > - Ref clock 1 for lanes 4 and 5
> > A proper handling of above had to be added, using newly introduced
> > sample at reset library class for Marvell SoCs.
> >
> > Other than that, update HPIPE settings and the reset sequence,
> > which differ from one used in x1 link.
> >
> > This patch fixes PCIE x4 and x2 configuration, which helps
> > to overcome link establishing issue for multi-lane end points.
> >
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Evan Wang <xswang@marvell.com>
> > Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> > ---
> > Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 1 +
> > Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c | 216
> +++++++++++++++-----
> > Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c | 1 +
> > Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h | 36 ++++
> > Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf | 1 +
> > 5 files changed, 203 insertions(+), 52 deletions(-)
> >
> > diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
> b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
> > index a147b6e..4129742 100644
> > --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
> > +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
> > @@ -36,6 +36,7 @@
> > ComPhyLib|Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf
> > MppLib|Silicon/Marvell/Library/MppLib/MppLib.inf
> > NorFlashInfoLib|EmbeddedPkg/Library/NorFlashInfoLib/
> NorFlashInfoLib.inf
> > + SampleAtResetLib|Silicon/Marvell/Armada7k8k/Library/
> Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.inf
> > UtmiPhyLib|Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf
> >
> > DebugLib|MdePkg/Library/BaseDebugLibSerialPort/
> BaseDebugLibSerialPort.inf
> > diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
> b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
> > index 40a7b99..5c7e769 100755
> > --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
> > +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
> > @@ -34,6 +34,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
> DAMAGE.
> >
> > #include "ComPhyLib.h"
> > #include <Library/MvHwDescLib.h>
> > +#include <Library/SampleAtResetLib.h>
> >
> > #define SD_LANE_ADDR_WIDTH 0x1000
> > #define HPIPE_ADDR_OFFSET 0x800
> > @@ -42,6 +43,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
> DAMAGE.
> > #define HPIPE_ADDR(base, Lane) (SD_ADDR(base, Lane) +
> HPIPE_ADDR_OFFSET)
> > #define COMPHY_ADDR(base, Lane) (base + COMPHY_ADDR_LANE_WIDTH *
> Lane)
> >
> > +#define CP110_PCIE_REF_CLK_TYPE0 0
> > +#define CP110_PCIE_REF_CLK_TYPE12 1
> > +
> > DECLARE_A7K8K_NONDISCOVERABLE_TEMPLATE;
> >
> > /*
> > @@ -99,11 +103,26 @@ COMPHY_MUX_DATA Cp110ComPhyPipeMuxData[] = {
> > STATIC
> > VOID
> > ComPhyPcieRFUConfiguration (
> > + IN UINT32 Lane,
> > + IN UINT32 PcieWidth,
> > IN EFI_PHYSICAL_ADDRESS ComPhyAddr
> > )
> > {
> > UINT32 Mask, Data;
> >
> > + /* Enable PCIe by4 and by2 */
> > + if (Lane == 0) {
> > + if (PcieWidth == 4) {
> > + RegSet (ComPhyAddr + COMMON_PHY_SD_CTRL1,
> > + COMMON_PHY_SD_CTRL1_PCIE_X4_EN,
> > + COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK);
> > + } else if (PcieWidth == 2) {
> > + RegSet (ComPhyAddr + COMMON_PHY_SD_CTRL1,
> > + COMMON_PHY_SD_CTRL1_PCIE_X2_EN,
> > + COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK);
> > + }
> > + }
> > +
> > /* RFU configurations - hard reset ComPhy */
> > Mask = COMMON_PHY_CFG1_PWR_UP_MASK;
> > Data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
> > @@ -132,11 +151,14 @@ ComPhyPcieRFUConfiguration (
> > STATIC
> > VOID
> > ComPhyPciePhyConfiguration (
> > + IN UINT32 Lane,
> > + IN UINT32 PcieWidth,
> > + IN UINT32 PcieClk,
> > IN EFI_PHYSICAL_ADDRESS ComPhyAddr,
> > IN EFI_PHYSICAL_ADDRESS HpipeAddr
> > )
> > {
> > - UINT32 Mask, Data, PcieClk = 0;
> > + UINT32 Mask, Data;
> >
> > /* Set PIPE soft reset */
> > Mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK;
> > @@ -156,13 +178,31 @@ ComPhyPciePhyConfiguration (
> > RegSet (HpipeAddr + HPIPE_RST_CLK_CTRL_REG, Data, Mask);
> >
> > /* Set PLL ready delay for 0x2 */
> > - RegSet (HpipeAddr + HPIPE_CLK_SRC_LO_REG,
> > - 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET,
> > - HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK);
> > + Data = HPIPE_CLK_SRC_LO_PLL_RDY_DL_DEFAULT;
> > + Mask = HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK;
> > + if (PcieWidth != 1) {
> > + Data |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_DEFAULT |
> > + HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_DEFAULT;
> > + Mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK |
> > + HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK;
> > + }
> > + RegSet (HpipeAddr + HPIPE_CLK_SRC_LO_REG, Data, Mask);
> >
> > /* Set PIPE mode interface to PCIe3 - 0x1 */
> > - RegSet (HpipeAddr + HPIPE_CLK_SRC_HI_REG,
> > - 0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET,
> HPIPE_CLK_SRC_HI_MODE_PIPE_MASK);
> > + Data = HPIPE_CLK_SRC_HI_MODE_PIPE_EN;
> > + Mask = HPIPE_CLK_SRC_HI_MODE_PIPE_MASK;
> > + if (PcieWidth != 1) {
> > + Mask |= HPIPE_CLK_SRC_HI_LANE_STRT_MASK |
> > + HPIPE_CLK_SRC_HI_LANE_MASTER_MASK |
> > + HPIPE_CLK_SRC_HI_LANE_BREAK_MASK;
> > + if (Lane == 0) {
> > + Data |= HPIPE_CLK_SRC_HI_LANE_STRT_EN |
> > + HPIPE_CLK_SRC_HI_LANE_MASTER_EN;
> > + } else if (Lane == (PcieWidth - 1)) {
> > + Data |= HPIPE_CLK_SRC_HI_LANE_BREAK_EN;
> > + }
> > + }
> > + RegSet (HpipeAddr + HPIPE_CLK_SRC_HI_REG, Data, Mask);
> >
> > /* Config update polarity equalization */
> > RegSet (HpipeAddr + HPIPE_LANE_EQ_CFG1_REG,
> > @@ -172,19 +212,21 @@ ComPhyPciePhyConfiguration (
> > RegSet (HpipeAddr + HPIPE_DFE_CTRL_28_REG,
> > 0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET,
> HPIPE_DFE_CTRL_28_PIPE4_MASK);
> >
> > - /* Enable PIN clock 100M_125M */
> > - Mask = HPIPE_MISC_CLK100M_125M_MASK;
> > - Data = 0x1 << HPIPE_MISC_CLK100M_125M_OFFSET;
> > -
> > /* Set PIN_TXDCLK_2X Clock Frequency Selection for outputs 500MHz
> clock */
> > - Mask |= HPIPE_MISC_TXDCLK_2X_MASK;
> > - Data |= 0x0 << HPIPE_MISC_TXDCLK_2X_OFFSET;
> > + Mask = HPIPE_MISC_TXDCLK_2X_MASK;
> > + Data = HPIPE_MISC_TXDCLK_2X_500MHZ;
> >
> > /* Enable 500MHz Clock */
> > Mask |= HPIPE_MISC_CLK500_EN_MASK;
> > Data |= 0x1 << HPIPE_MISC_CLK500_EN_OFFSET;
> >
> > if (PcieClk) {
> > + /*
> > + * Enable PIN clock 100M_125M
> > + * Only if clock is output, configure the clock-source mux
> > + */
> > + Mask |= HPIPE_MISC_CLK100M_125M_MASK;
> > + Data |= HPIPE_MISC_CLK100M_125M_EN;
> > /* Set reference clock comes from group 1 */
> > Mask |= HPIPE_MISC_REFCLK_SEL_MASK;
> > Data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET;
> > @@ -214,6 +256,13 @@ ComPhyPciePhyConfiguration (
> > Data |= 0x3 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
> > RegSet (HpipeAddr + HPIPE_PWR_PLL_REG, Data, Mask);
> >
> > + /* Ref clock alignment */
> > + if (PcieWidth != 1) {
> > + RegSet (HpipeAddr + HPIPE_LANE_ALIGN_REG,
> > + HPIPE_LANE_ALIGN_OFF,
> > + HPIPE_LANE_ALIGN_OFF_MASK);
> > + }
> > +
> > /*
> > * Set the amount of time spent in the LoZ state - set
> > * for 0x7 only if the PCIe clock is output
> > @@ -396,7 +445,7 @@ ComPhyPcieSetAnalogParameters (
> > HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK;
> > Data = (0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET) |
> > (0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET) |
> > - (0x2 << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET);
> > + (HPIPE_LANE_CFG_FOM_PRESET_VECTOR_DEFAULT);
> > MmioAndThenOr32 (HpipeAddr + HPIPE_LANE_EQ_REMOTE_SETTING_REG,
> ~Mask, Data);
> >
> > /* Set phy in root complex mode */
> > @@ -404,37 +453,82 @@ ComPhyPcieSetAnalogParameters (
> > }
> >
> > STATIC
> > -VOID
> > -ComPhyPciePhyPowerUp (
> > - IN EFI_PHYSICAL_ADDRESS HpipeAddr
> > -)
> > -{
> > - /* Release from PIPE soft reset */
> > - RegSet (HpipeAddr + HPIPE_RST_CLK_CTRL_REG,
> > - 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET,
> > - HPIPE_RST_CLK_CTRL_PIPE_RST_MASK);
> > -
> > - /* Wait 15ms - for ComPhy calibration done */
> > - MicroSecondDelay (15000);
> > - MemoryFence ();
> > -}
> > -
> > -STATIC
> > EFI_STATUS
> > -ComPhyPcieCheckPll (
> > - IN EFI_PHYSICAL_ADDRESS HpipeAddr
> > +ComPhyPciePhyPowerUp (
> > + IN UINT32 Lane,
> > + IN UINT32 PcieWidth,
> > + IN EFI_PHYSICAL_ADDRESS ComPhyBase,
> > + IN EFI_PHYSICAL_ADDRESS HpipeBase
> > )
> > {
> > EFI_STATUS Status = EFI_SUCCESS;
> > + UINT8 StartLane, EndLane, Loop;
> > UINT32 Data;
> >
> > - /* Read Lane status */
> > - Data = MmioRead32 (HpipeAddr + HPIPE_LANE_STATUS0_REG);
> > - if ((Data & HPIPE_LANE_STATUS0_PCLK_EN_MASK) == 0) {
> > - DEBUG((DEBUG_INFO, "ComPhy: Read from reg = %p - value = 0x%x\n",
> > - HpipeAddr + HPIPE_LANE_STATUS0_REG, Data));
> > - DEBUG((DEBUG_INFO, "ComPhy: HPIPE_LANE_STATUS0_PCLK_EN_MASK is
> 0\n"));
> > - Status = EFI_D_ERROR;
> > + /*
> > + * For PCIe by4 or by2 - release from reset only after finish to
> > + * configure all lanes
> > + */
> > + if ((PcieWidth == 1) || (Lane == (PcieWidth - 1))) {
> > + if (PcieWidth != 1) {
> > + /* Allows writing to all lanes in one write */
> > + RegSet (ComPhyBase + COMMON_PHY_SD_CTRL1,
> > + COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_WR_ENABLE,
> > + COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK);
> > + StartLane = 0;
> > + EndLane = PcieWidth;
> > +
> > + /*
> > + * Release from PIPE soft reset
> > + * for PCIe by4 or by2 - release from soft reset
> > + * all lanes - can't use read modify write
> > + */
> > + RegSet (HPIPE_ADDR (HpipeBase, 0) + HPIPE_RST_CLK_CTRL_REG,
> > + HPIPE_RST_CLK_CTRL_FIXED_PCLK_WIDTH_8 |
> HPIPE_RST_CLK_CTRL_MODE_REFDIV_4,
> > + HPIPE_RST_CLK_CTRL_CLR_ALL_MASK);
> > + } else {
> > + StartLane = Lane;
> > + EndLane = Lane + 1;
> > +
> > + /*
> > + * Release from PIPE soft reset
> > + * for PCIe by4 or by2 - release from soft reset
> > + * all lanes
> > + */
> > + RegSet (HPIPE_ADDR (HpipeBase, Lane) + HPIPE_RST_CLK_CTRL_REG,
> > + HPIPE_RST_CLK_CTRL_PIPE_RST_DISABLE,
> > + HPIPE_RST_CLK_CTRL_PIPE_RST_MASK);
> > + }
> > +
> > + if (PcieWidth != 1) {
> > + /* Disable writing to all lanes with one write */
> > + RegSet (ComPhyBase + COMMON_PHY_SD_CTRL1,
> > + COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_WR_DISABLE,
> > + COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK);
> > + }
> > + MemoryFence ();
> > +
> > + /* Wait 20ms until status of all lanes stabilize */
> > + MicroSecondDelay (20000);
> > +
> > + /* Make sure all lanes are UP */
> > + for (Loop = StartLane; Loop < EndLane; Loop++) {
> > + Data = MmioRead32 (HPIPE_ADDR (HpipeBase, Loop) +
> HPIPE_LANE_STATUS0_REG);
> > +
> > + if ((Data & HPIPE_LANE_STATUS0_PCLK_EN_MASK) == 0) {
> > + DEBUG ((DEBUG_ERROR,
> > + "%a: Read from lane%d, reg = %p - value = 0x%x\n",
> > + __FUNCTION__,
> > + Loop,
> > + HPIPE_ADDR (HpipeBase, Loop) + HPIPE_LANE_STATUS0_REG,
> > + Data));
> > + DEBUG ((DEBUG_ERROR,
> > + "%a: HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n",
> > + __FUNCTION__));
> > + Status = EFI_D_ERROR;
> > + break;
> > + }
> > + }
> > }
> >
> > return Status;
> > @@ -443,8 +537,9 @@ ComPhyPcieCheckPll (
> > STATIC
> > EFI_STATUS
> > ComPhyPciePowerUp (
> > + IN UINT8 ChipId,
> > IN UINT32 Lane,
> > - IN UINT32 PcieBy4,
> > + IN UINT32 PcieWidth,
> > IN EFI_PHYSICAL_ADDRESS HpipeBase,
> > IN EFI_PHYSICAL_ADDRESS ComPhyBase
> > )
> > @@ -452,26 +547,36 @@ ComPhyPciePowerUp (
> > EFI_STATUS Status = EFI_SUCCESS;
> > EFI_PHYSICAL_ADDRESS HpipeAddr = HPIPE_ADDR(HpipeBase, Lane);
> > EFI_PHYSICAL_ADDRESS ComPhyAddr = COMPHY_ADDR(ComPhyBase, Lane);
> > + UINT32 PcieClk;
> > +
> > + /*
> > + * Obtain clock direction from sample-at-reset configuration.
> > + * 4th and 5th SerDes lanes can belong only to PCIE Port1 and
> > + * Port2, which use different clock type specifier than Port0.
> > + */
> > + if (Lane == 4 || Lane == 5) {
> > + PcieClk = SampleAtResetGetPcieClockDirection (ChipId,
> CP110_PCIE_REF_CLK_TYPE12);
> > + } else {
> > + PcieClk = SampleAtResetGetPcieClockDirection (ChipId,
> CP110_PCIE_REF_CLK_TYPE0);
> > + }
> > +
> > + DEBUG ((DEBUG_INFO, "%a: ChipId: %d PcieClk:%d\n", __FUNCTION__,
> ChipId, PcieClk));
> >
> > DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset
> ComPhy\n"));
> >
> > - ComPhyPcieRFUConfiguration (ComPhyAddr);
> > + ComPhyPcieRFUConfiguration (Lane, PcieWidth, ComPhyAddr);
> >
> > DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy configuration\n"));
> >
> > - ComPhyPciePhyConfiguration (ComPhyAddr, HpipeAddr);
> > + ComPhyPciePhyConfiguration (Lane, PcieWidth, PcieClk, ComPhyAddr,
> HpipeAddr);
> >
> > DEBUG((DEBUG_INFO, "ComPhy: stage: Set analog paramters\n"));
> >
> > ComPhyPcieSetAnalogParameters (HpipeAddr);
> >
> > - DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy power up\n"));
> > + DEBUG ((DEBUG_INFO, "%a: stage: ComPhy power up and check PLL\n",
> __FUNCTION__));
> >
> > - ComPhyPciePhyPowerUp (HpipeAddr);
> > -
> > - DEBUG((DEBUG_INFO, "ComPhy: stage: Check PLL\n"));
> > -
> > - Status = ComPhyPcieCheckPll (HpipeAddr);
> > + Status = ComPhyPciePhyPowerUp (Lane, PcieWidth, ComPhyBase,
> HpipeBase);
> >
> > return Status;
> > }
> > @@ -1780,28 +1885,35 @@ ComPhyCp110Init (
> > COMPHY_MAP *PtrComPhyMap, *SerdesMap;
> > EFI_PHYSICAL_ADDRESS ComPhyBaseAddr, HpipeBaseAddr;
> > UINT32 ComPhyMaxCount, Lane;
> > - UINT32 PcieBy4 = 1; // Indicating if first 4 lanes set to PCIE
> > + UINT32 PcieWidth = 0;
> > + UINT8 ChipId;
> >
> > ComPhyMaxCount = PtrChipCfg->LanesCount;
> > ComPhyBaseAddr = PtrChipCfg->ComPhyBaseAddr;
> > HpipeBaseAddr = PtrChipCfg->Hpipe3BaseAddr;
> > SerdesMap = PtrChipCfg->MapData;
> > + ChipId = PtrChipCfg->ChipId;
> >
> > /* Config Comphy mux configuration */
> > ComPhyMuxCp110(PtrChipCfg, SerdesMap);
> >
> > /* Check if the first 4 Lanes configured as By-4 */
> > for (Lane = 0, PtrComPhyMap = SerdesMap; Lane < 4; Lane++,
> PtrComPhyMap++) {
> > - if (PtrComPhyMap->Type != COMPHY_TYPE_PCIE0) {
> > - PcieBy4 = 0;
> > + if (PtrComPhyMap->Type != COMPHY_TYPE_PCIE0)
> > break;
> > - }
>
> Please reinstate the braces ({}) for the if.
>
> > + PcieWidth++;
> > }
> >
> > for (Lane = 0, PtrComPhyMap = SerdesMap; Lane < ComPhyMaxCount;
> > Lane++, PtrComPhyMap++) {
> > DEBUG((DEBUG_INFO, "ComPhy: Initialize serdes number %d\n", Lane));
> > DEBUG((DEBUG_INFO, "ComPhy: Serdes Type = 0x%x\n",
> PtrComPhyMap->Type));
> > +
> > + if (Lane >= 4) {
> > + /* PCIe lanes above the first 4 lanes, can be only by1 */
> > + PcieWidth = 1;
> > + }
> > +
> > switch (PtrComPhyMap->Type) {
> > case COMPHY_TYPE_UNCONNECTED:
> > continue;
> > @@ -1810,7 +1922,7 @@ ComPhyCp110Init (
> > case COMPHY_TYPE_PCIE1:
> > case COMPHY_TYPE_PCIE2:
> > case COMPHY_TYPE_PCIE3:
> > - Status = ComPhyPciePowerUp(Lane, PcieBy4, HpipeBaseAddr,
> ComPhyBaseAddr);
> > + Status = ComPhyPciePowerUp (ChipId, Lane, PcieWidth,
> HpipeBaseAddr, ComPhyBaseAddr);
> > break;
> > case COMPHY_TYPE_SATA0:
> > case COMPHY_TYPE_SATA1:
> > diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c
> b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c
> > index bf21dca..b03bc35 100644
> > --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c
> > +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c
> > @@ -192,6 +192,7 @@ InitComPhyConfig (
> > ChipConfig->Hpipe3BaseAddr = Desc->ComPhyHpipe3BaseAddresses[Id];
> > ChipConfig->LanesCount = Desc->ComPhyLaneCount[Id];
> > ChipConfig->MuxBitCount = Desc->ComPhyMuxBitCount[Id];
> > + ChipConfig->ChipId = Id;
> >
> > /*
> > * Below macro contains variable name concatenation (used to form
> PCD's name).
> > diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
> b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
> > index 5899a4a..c675d74 100644
> > --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
> > +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
> > @@ -252,14 +252,17 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
> SUCH DAMAGE.
> >
> > #define HPIPE_LANE_ALIGN_REG 0x124
> > #define HPIPE_LANE_ALIGN_OFF_OFFSET 12
> > +#define HPIPE_LANE_ALIGN_OFF (0x0 <<
> HPIPE_LANE_ALIGN_OFF_OFFSET)
> > #define HPIPE_LANE_ALIGN_OFF_MASK (0x1 <<
> HPIPE_LANE_ALIGN_OFF_OFFSET)
> >
> > #define HPIPE_MISC_REG 0x13C
> > #define HPIPE_MISC_CLK100M_125M_OFFSET 4
> > +#define HPIPE_MISC_CLK100M_125M_EN (0x1 <<
> HPIPE_MISC_CLK100M_125M_OFFSET)
> > #define HPIPE_MISC_CLK100M_125M_MASK (0x1 <<
> HPIPE_MISC_CLK100M_125M_OFFSET)
> > #define HPIPE_MISC_ICP_FORCE_OFFSET 5
> > #define HPIPE_MISC_ICP_FORCE_MASK (0x1 <<
> HPIPE_MISC_ICP_FORCE_OFFSET)
> > #define HPIPE_MISC_TXDCLK_2X_OFFSET 6
> > +#define HPIPE_MISC_TXDCLK_2X_500MHZ (0x0 <<
> HPIPE_MISC_TXDCLK_2X_OFFSET)
> > #define HPIPE_MISC_TXDCLK_2X_MASK (0x1 <<
> HPIPE_MISC_TXDCLK_2X_OFFSET)
> > #define HPIPE_MISC_CLK500_EN_OFFSET 7
> > #define HPIPE_MISC_CLK500_EN_MASK (0x1 <<
> HPIPE_MISC_CLK500_EN_OFFSET)
> > @@ -476,30 +479,52 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
> SUCH DAMAGE.
> > #define HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET 1
> > #define HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK (0x1 <<
> HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET)
> > #define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET 2
> > +#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_DEFAULT (0x1 <<
> HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET)
> > #define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK (0xf <<
> HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET)
> >
> > #define HPIPE_RST_CLK_CTRL_REG 0x704
> > +#define HPIPE_RST_CLK_CTRL_CLR_ALL_MASK MAX_UINT32
> > #define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0
> > +#define HPIPE_RST_CLK_CTRL_PIPE_RST_DISABLE (0x0 <<
> HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET)
> > #define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK (0x1 <<
> HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET)
> > #define HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET 2
> > #define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK (0x1 <<
> HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET)
> > +#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_WIDTH_8 (0x1 <<
> HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET)
> > +#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_WIDTH_16 (0x0 <<
> HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET)
> > #define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET 3
> > #define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK (0x1 <<
> HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET)
> > +#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_OFFSET 4
> > +#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_MASK (0x3 <<
> HPIPE_RST_CLK_CTRL_MODE_REFDIV_OFFSET)
> > +#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_1 (0x0 <<
> HPIPE_RST_CLK_CTRL_MODE_REFDIV_OFFSET)
> > +#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_2 (0x1 <<
> HPIPE_RST_CLK_CTRL_MODE_REFDIV_OFFSET)
> > +#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_4 (0x2 <<
> HPIPE_RST_CLK_CTRL_MODE_REFDIV_OFFSET)
> > +#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_8 (0x3 <<
> HPIPE_RST_CLK_CTRL_MODE_REFDIV_OFFSET)
> > #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET 9
> > #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK (0x1 <<
> HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET)
> >
> > #define HPIPE_CLK_SRC_LO_REG 0x70c
> > +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET 1
> > +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_DEFAULT (0x1 <<
> HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET)
> > +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK (0x1 <<
> HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET)
> > +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET 2
> > +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_DEFAULT (0x1 <<
> HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET)
> > +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK (0x3 <<
> HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET)
> > #define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET 5
> > +#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_DEFAULT (0x2 <<
> HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET)
> > #define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK (0x7 <<
> HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET)
> >
> > #define HPIPE_CLK_SRC_HI_REG 0x710
> > #define HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET 0
> > +#define HPIPE_CLK_SRC_HI_LANE_STRT_EN (0x1 <<
> HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET)
> > #define HPIPE_CLK_SRC_HI_LANE_STRT_MASK (0x1 <<
> HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET)
> > #define HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET 1
> > +#define HPIPE_CLK_SRC_HI_LANE_BREAK_EN (0x1 <<
> HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET)
> > #define HPIPE_CLK_SRC_HI_LANE_BREAK_MASK (0x1 <<
> HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET)
> > #define HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET 2
> > +#define HPIPE_CLK_SRC_HI_LANE_MASTER_EN (0x1 <<
> HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET)
> > #define HPIPE_CLK_SRC_HI_LANE_MASTER_MASK (0x1 <<
> HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET)
> > #define HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET 7
> > +#define HPIPE_CLK_SRC_HI_MODE_PIPE_EN (0x1 <<
> HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET)
> > #define HPIPE_CLK_SRC_HI_MODE_PIPE_MASK (0x1 <<
> HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET)
> >
> > #define HPIPE_GLOBAL_MISC_CTRL 0x718
> > @@ -528,6 +553,16 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
> SUCH DAMAGE.
> > #define COMMON_SELECTOR_PIPE_OFFSET 0x144
> >
> > #define COMMON_PHY_SD_CTRL1 0x148
> > +#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET 0
> > +#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_WR_ENABLE 0x0
> > +#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_WR_DISABLE 0x3210
> > +#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK 0xFFFF
> > +#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET 24
> > +#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN (0x1 <<
> COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET)
> > +#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK (0x1 <<
> COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET)
> > +#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET 25
> > +#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN (0x1 <<
> COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET)
> > +#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK (0x1 <<
> COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET)
> > #define COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET 26
> > #define COMMON_PHY_SD_CTRL1_RXAUI1_MASK (0x1 <<
> COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET)
> > #define COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET 27
> > @@ -594,6 +629,7 @@ struct _CHIP_COMPHY_CONFIG {
> > COMPHY_CHIP_INIT Init;
> > UINT32 LanesCount;
> > UINT32 MuxBitCount;
> > + UINT8 ChipId;
> > };
> >
> > VOID
> > diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf
> b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf
> > index a1584b4..ce0af54 100644
> > --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf
> > +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf
> > @@ -50,6 +50,7 @@
> > DebugLib
> > MemoryAllocationLib
> > PcdLib
> > + SampleAtResetLib
> > IoLib
> >
> > [Sources.common]
> > --
> > 2.7.4
> >
>
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [platforms PATCH v2 4/4] Marvell/Library: ComPhyLib: Fix configuration for PCIE x4 and x2
2018-05-21 10:54 ` Marcin Wojtas
@ 2018-05-22 11:20 ` Leif Lindholm
2018-05-22 17:29 ` Marcin Wojtas
0 siblings, 1 reply; 10+ messages in thread
From: Leif Lindholm @ 2018-05-22 11:20 UTC (permalink / raw)
To: Marcin Wojtas; +Cc: edk2-devel-01, Ard Biesheuvel, Grzegorz Jaszczyk
On Mon, May 21, 2018 at 12:54:01PM +0200, Marcin Wojtas wrote:
> Hi Leif,
>
>
> 2018-05-09 18:49 GMT+02:00 Leif Lindholm <leif.lindholm@linaro.org>:
>
> > A couple of minor style comments.
> >
> > If you don't disagree, I can fix that up before pushing and you can
> > have Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> for 1,3-4.
> >
> >
> Yes, I would appreciate that.
1,3-4/4 pushed as 5cfda16b1a..a310c6b5e1.
/
Leif
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [platforms PATCH v2 4/4] Marvell/Library: ComPhyLib: Fix configuration for PCIE x4 and x2
2018-05-22 11:20 ` Leif Lindholm
@ 2018-05-22 17:29 ` Marcin Wojtas
0 siblings, 0 replies; 10+ messages in thread
From: Marcin Wojtas @ 2018-05-22 17:29 UTC (permalink / raw)
To: Leif Lindholm; +Cc: edk2-devel-01, Ard Biesheuvel, Grzegorz Jaszczyk
2018-05-22 13:20 GMT+02:00 Leif Lindholm <leif.lindholm@linaro.org>:
> On Mon, May 21, 2018 at 12:54:01PM +0200, Marcin Wojtas wrote:
>> Hi Leif,
>>
>>
>> 2018-05-09 18:49 GMT+02:00 Leif Lindholm <leif.lindholm@linaro.org>:
>>
>> > A couple of minor style comments.
>> >
>> > If you don't disagree, I can fix that up before pushing and you can
>> > have Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> for 1,3-4.
>> >
>> >
>> Yes, I would appreciate that.
>
> 1,3-4/4 pushed as 5cfda16b1a..a310c6b5e1.
>
> /
> Leif
Thank you!
Marcin
^ permalink raw reply [flat|nested] 10+ messages in thread