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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id r11-v6sm1612908ljg.37.2018.05.09.06.51.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 09 May 2018 06:51:37 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jinghua@marvell.com, jaz@semihalf.com, Igal Liberman Date: Wed, 9 May 2018 15:51:10 +0200 Message-Id: <1525873871-799-4-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1525873871-799-1-git-send-email-mw@semihalf.com> References: <1525873871-799-1-git-send-email-mw@semihalf.com> Subject: [platforms PATCH v2 3/4] Marvell/Armada7k8k: Add basic sample at reset library X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 09 May 2018 13:51:41 -0000 From: Igal Liberman The sample at reset library adds the following functionalities: - MvSARGetCpuFreq - Get the CPU frequency - MvSARGetDramFreq - Get the DRAM frequency - MvSARGetPcieClkDirection - Determine the PCIe clock direction for two types specified in CP110 HW block. It will be needed for proper configuration during the PCIE SerDes training. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Igal Liberman Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.c | 111 ++++++++++++++++++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.h | 109 +++++++++++++++++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.inf | 54 ++++++++++ Silicon/Marvell/Include/Library/SampleAtResetLib.h | 57 ++++++++++ Silicon/Marvell/Marvell.dec | 3 + 5 files changed, 334 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.c new file mode 100644 index 0000000..3ebff56 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.c @@ -0,0 +1,111 @@ +/******************************************************************************** +Copyright (C) 2018 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must Retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +Glossary - abbreviations used in Marvell SampleAtReset library implementation: +AP - Application Processor hardware block (Armada 7k8k incorporates AP806) +CP - South Bridge hardware blocks (Armada 7k8k incorporates CP110) +SAR - Sample At Reset + +*******************************************************************************/ + +#include + +#include +#include +#include + +#include "Armada7k8kSampleAtResetLib.h" + +UINT32 +EFIAPI +SampleAtResetGetCpuFrequency ( + VOID + ) +{ + CONST PLL_FREQUENCY_DESCRIPTION *PllFrequencies; + UINT32 ClockValue; + UINT32 Index; + + ClockValue = MmioAnd32 (AP806_SAR_BASE, SAR_CLOCK_FREQUENCY_MODE_MASK); + + PllFrequencies = PllFrequencyTable; + + for (Index = 0; Index < SAR_MAX_OPTIONS; Index++, PllFrequencies++) { + if (PllFrequencies->ClockingOption == ClockValue) { + break; + } + } + + return PllFrequencies->CpuFrequency; +} + +UINT32 +EFIAPI +SampleAtResetGetDramFrequency ( + VOID + ) +{ + CONST PLL_FREQUENCY_DESCRIPTION *PllFrequencies; + UINT32 ClockValue; + UINT32 Index; + + ClockValue = MmioAnd32 (AP806_SAR_BASE, SAR_CLOCK_FREQUENCY_MODE_MASK); + + PllFrequencies = PllFrequencyTable; + + for (Index = 0; Index < SAR_MAX_OPTIONS; Index++, PllFrequencies++) { + if (PllFrequencies->ClockingOption == ClockValue) { + break; + } + } + + return PllFrequencies->DdrFrequency; +} + +UINT32 +EFIAPI +SampleAtResetGetPcieClockDirection ( + IN UINT32 CpIndex, + IN UINT32 PcieIndex + ) +{ + UINT32 ClockDirection; + + ASSERT (CpIndex < MAX_CP_COUNT); + ASSERT (PcieIndex < MAX_PCIE_CLK_TYPE_COUNT); + + ClockDirection = MmioAnd32 (CP110_SAR_BASE (CpIndex), + PcieClockMask[CpIndex][PcieIndex] >> + PcieClockOffset[CpIndex][PcieIndex]); + + return ClockDirection; +} diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.h new file mode 100644 index 0000000..323399f --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.h @@ -0,0 +1,109 @@ +/******************************************************************************** +Copyright (C) 2018 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must Retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +Glossary - abbreviations used in Marvell SampleAtReset library implementation: +AP - Application Processor hardware block (Armada 7k8k incorporates AP806) +CP - South Bridge hardware blocks (Armada 7k8k incorporates CP110) +SAR - Sample At Reset + +*******************************************************************************/ + +#define SAR_MAX_OPTIONS 16 + +#define AP806_SAR_BASE 0xf06f8200 +#define SAR_CLOCK_FREQUENCY_MODE_MASK 0x1f + +#define CP110_SAR_BASE(_CpIndex) (0xf2000000 + (0x2000000 * (_CpIndex)) + 0x400200) + +#define MAX_CP_COUNT 2 +#define MAX_PCIE_CLK_TYPE_COUNT 2 + +#define CP0_PCIE0_CLK_OFFSET 2 +#define CP0_PCIE1_CLK_OFFSET 3 +#define CP1_PCIE0_CLK_OFFSET 0 +#define CP1_PCIE1_CLK_OFFSET 1 +#define CP0_PCIE0_CLK_MASK (1 << CP0_PCIE0_CLK_OFFSET) +#define CP0_PCIE1_CLK_MASK (1 << CP0_PCIE1_CLK_OFFSET) +#define CP1_PCIE0_CLK_MASK (1 << CP1_PCIE0_CLK_OFFSET) +#define CP1_PCIE1_CLK_MASK (1 << CP1_PCIE1_CLK_OFFSET) + +typedef enum { + CPU_2000_DDR_1200_RCLK_1200 = 0x0, + CPU_2000_DDR_1050_RCLK_1050 = 0x1, + CPU_1600_DDR_800_RCLK_800 = 0x4, + CPU_1800_DDR_1200_RCLK_1200 = 0x6, + CPU_1800_DDR_1050_RCLK_1050 = 0x7, + CPU_1600_DDR_1050_RCLK_1050 = 0x0d, + CPU_1000_DDR_650_RCLK_650 = 0x13, + CPU_1300_DDR_800_RCLK_800 = 0x14, + CPU_1300_DDR_650_RCLK_650 = 0x17, + CPU_1200_DDR_800_RCLK_800 = 0x19, + CPU_1400_DDR_800_RCLK_800 = 0x1a, + CPU_600_DDR_800_RCLK_800 = 0x1b, + CPU_800_DDR_800_RCLK_800 = 0x1c, + CPU_1000_DDR_800_RCLK_800 = 0x1d, +} CLOCKING_OPTIONS; + +typedef struct { + UINT32 CpuFrequency; + UINT32 DdrFrequency; + UINT32 RingFrequency; + CLOCKING_OPTIONS ClockingOption; +} PLL_FREQUENCY_DESCRIPTION; + +STATIC CONST PLL_FREQUENCY_DESCRIPTION PllFrequencyTable[SAR_MAX_OPTIONS] = { + /* CPU DDR Ring [MHz] */ + {2000, 1200, 1200, CPU_2000_DDR_1200_RCLK_1200}, + {2000, 1050, 1050, CPU_2000_DDR_1050_RCLK_1050}, + {1800, 1200, 1200, CPU_1800_DDR_1200_RCLK_1200}, + {1800, 1050, 1050, CPU_1800_DDR_1050_RCLK_1050}, + {1600, 1050, 1050, CPU_1600_DDR_1050_RCLK_1050}, + {1300, 800 , 800 , CPU_1300_DDR_800_RCLK_800}, + {1300, 650 , 650 , CPU_1300_DDR_650_RCLK_650}, + {1600, 800 , 800 , CPU_1600_DDR_800_RCLK_800}, + {1000, 650 , 650 , CPU_1000_DDR_650_RCLK_650}, + {1200, 800 , 800 , CPU_1200_DDR_800_RCLK_800}, + {1400, 800 , 800 , CPU_1400_DDR_800_RCLK_800}, + {600 , 800 , 800 , CPU_600_DDR_800_RCLK_800}, + {800 , 800 , 800 , CPU_800_DDR_800_RCLK_800}, + {1000, 800 , 800 , CPU_1000_DDR_800_RCLK_800} +}; + +STATIC CONST UINT32 PcieClockMask[MAX_CP_COUNT][MAX_PCIE_CLK_TYPE_COUNT] = { + {CP0_PCIE0_CLK_MASK, CP0_PCIE1_CLK_MASK}, + {CP1_PCIE0_CLK_MASK, CP1_PCIE1_CLK_MASK} +}; + +STATIC CONST UINT32 PcieClockOffset[MAX_CP_COUNT][MAX_PCIE_CLK_TYPE_COUNT] = { + {CP0_PCIE0_CLK_OFFSET, CP0_PCIE1_CLK_OFFSET}, + {CP1_PCIE0_CLK_OFFSET, CP1_PCIE1_CLK_OFFSET} +}; diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.inf new file mode 100644 index 0000000..5a21cde --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.inf @@ -0,0 +1,54 @@ +# Copyright (C) 2018 Marvell International Ltd. +# +# Marvell BSD License Option +# +# If you received this File from Marvell, you may opt to use, redistribute and/or +# modify this File under the following licensing terms. +# Redistribution and use in source and binary forms, with or without modification, +# are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# * Neither the name of Marvell nor the names of its contributors may be +# used to endorse or promote products derived from this software without +# specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = Armada7k8kSampleAtResetLib + FILE_GUID = 03e022c7-9bd7-4608-aa21-379deaac2430 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = SampleAtResetLib + +[Sources] + Armada7k8kSampleAtResetLib.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Marvell/Marvell.dec + +[LibraryClasses] + DebugLib + IoLib + +[Depex] + TRUE diff --git a/Silicon/Marvell/Include/Library/SampleAtResetLib.h b/Silicon/Marvell/Include/Library/SampleAtResetLib.h new file mode 100644 index 0000000..1be3a6a --- /dev/null +++ b/Silicon/Marvell/Include/Library/SampleAtResetLib.h @@ -0,0 +1,57 @@ +/******************************************************************************** +Copyright (C) 2018 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must Retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __SAMPLE_AT_RESET_LIB_H__ +#define __SAMPLE_AT_RESET_LIB_H__ + +UINT32 +EFIAPI +SampleAtResetGetCpuFrequency ( + VOID + ); + +UINT32 +EFIAPI +SampleAtResetGetDramFrequency ( + VOID + ); + +UINT32 +EFIAPI +SampleAtResetGetPcieClockDirection ( + IN UINT32 CpIndex, + IN UINT32 PcieIndex + ); + +#endif /* __SAMPLE_AT_RESET_LIB_H__ */ diff --git a/Silicon/Marvell/Marvell.dec b/Silicon/Marvell/Marvell.dec index 2eb6238..be74b4e 100644 --- a/Silicon/Marvell/Marvell.dec +++ b/Silicon/Marvell/Marvell.dec @@ -59,6 +59,9 @@ gMarvellFvbDxeGuid = { 0x42903750, 0x7e61, 0x4aaf, { 0x83, 0x29, 0xbf, 0x42, 0x36, 0x4e, 0x24, 0x85 } } gMarvellSpiFlashDxeGuid = { 0x49d7fb74, 0x306d, 0x42bd, { 0x94, 0xc8, 0xc0, 0xc5, 0x4b, 0x18, 0x1d, 0xd7 } } +[LibraryClasses] + SampleAtResetLib|Include/Library/SampleAtResetLib.h + [Protocols] # installed as a protocol by PlatInitDxe to force ordering between DXE drivers # that depend on the lowlevel platform initialization having been completed -- 2.7.4