From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c01::242; helo=mail-pl0-x242.google.com; envelope-from=haojian.zhuang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pl0-x242.google.com (mail-pl0-x242.google.com [IPv6:2607:f8b0:400e:c01::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CE86D20837982 for ; Wed, 9 May 2018 19:17:38 -0700 (PDT) Received: by mail-pl0-x242.google.com with SMTP id a39-v6so362073pla.10 for ; Wed, 09 May 2018 19:17:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZqiQxzKveKL64c2hk2YHJtKcOvFbm4mAA0d3yo3pXM8=; b=KvOf/GGBJGPS0dHKVXqtEhkXsZLb0w9GzM2OS3EwEwUBVgqgNS5b+3K4CxjH2oUHKn K4l+QJefNUuGEuw87LDdli3padj2sMNUFRctO5M5FV/GubNmk5likEBl5bhlNzmokW1n ZKnF0Y5tSSYaC5c/zG2SdDDmu+qJb5MQwOj38= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZqiQxzKveKL64c2hk2YHJtKcOvFbm4mAA0d3yo3pXM8=; b=ZB7MrYks0J7pqg5lowIG6lOvCaL1BmX/Nr/BC6wXDkTIkyj82TDbj75iDGyaYU0Dnc 97n/HH0zWUW8VIjURL/8lEVqS/qIRCCQ/s0CPzUn4y7SXSQ7BuSeRX5dys0M/Vr7X2tn RfKfI2lbJjhpBZrOJFa9rJSro6eyTtmVY2Qnks+98F7ndP3G5+LAmhxkBD1uxsBFokKv x1gwRBmFMkpTBsKuqvVuf2m6oVNAV7JYzjT7oZhidEhmYPn7RGgmBTkEouZelK6nNnbG 26kNBHe9FF11ZzJz+wOnIJO6KXEjx3eCf92IFOkq0a9NJOxJ4GHKIHC1mPPyL6CWUilE 1I3g== X-Gm-Message-State: ALQs6tCThHNWRNla+CbZuDyHzWTkIpkTJNGvHoi1HHirCyOo1wrfmxHP BSc4aDvciZYm9edgblALXWi6sPYl8Xw= X-Google-Smtp-Source: AB8JxZpqRbx7Fd7/PqQZEDG45AUosaNhkIVWUjXScxkQOwSJ455n7KTrHL8P2lerNzciWhM/iCg1lg== X-Received: by 2002:a17:902:4203:: with SMTP id g3-v6mr47110660pld.315.1525918657663; Wed, 09 May 2018 19:17:37 -0700 (PDT) Received: from localhost.localdomain ([64.64.108.93]) by smtp.gmail.com with ESMTPSA id z15-v6sm46351857pgr.55.2018.05.09.19.17.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 09 May 2018 19:17:36 -0700 (PDT) From: Haojian Zhuang To: edk2-devel@lists.01.org Cc: Haojian Zhuang , Leif Lindholm , Ard Biesheuvel Date: Thu, 10 May 2018 10:17:15 +0800 Message-Id: <1525918639-22690-3-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1525918639-22690-1-git-send-email-haojian.zhuang@linaro.org> References: <1525918639-22690-1-git-send-email-haojian.zhuang@linaro.org> Subject: [PATCH edk2-platforms v3 2/6] Platform/HiKey960: do basic initialization X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 10 May 2018 02:17:39 -0000 Do some basic initliazation on peripherals, such as pins and regulators. Cc: Leif Lindholm Cc: Ard Biesheuvel Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Haojian Zhuang --- Platform/Hisilicon/HiKey960/HiKey960.dsc | 2 + Platform/Hisilicon/HiKey960/HiKey960.fdf | 2 + .../Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.c | 179 +++++++++++++++++++++ .../Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.h | 91 +++++++++++ .../Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf | 47 ++++++ Silicon/Hisilicon/Hi3660/Hi3660.dec | 32 ++++ Silicon/Hisilicon/Hi3660/Include/Hi3660.h | 175 ++++++++++++++++++++ Silicon/Hisilicon/Hi3660/Include/Hkadc.h | 68 ++++++++ 8 files changed, 596 insertions(+) create mode 100644 Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.c create mode 100644 Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.h create mode 100644 Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf create mode 100644 Silicon/Hisilicon/Hi3660/Hi3660.dec create mode 100644 Silicon/Hisilicon/Hi3660/Include/Hi3660.h create mode 100644 Silicon/Hisilicon/Hi3660/Include/Hkadc.h diff --git a/Platform/Hisilicon/HiKey960/HiKey960.dsc b/Platform/Hisilicon/HiKey960/HiKey960.dsc index 3da1b8556321..6cc1c1edf453 100644 --- a/Platform/Hisilicon/HiKey960/HiKey960.dsc +++ b/Platform/Hisilicon/HiKey960/HiKey960.dsc @@ -182,6 +182,8 @@ [Components.common] Platform/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.inf ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf + Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf + # # USB Host Support # diff --git a/Platform/Hisilicon/HiKey960/HiKey960.fdf b/Platform/Hisilicon/HiKey960/HiKey960.fdf index 162dbaaf2646..b7d70b010598 100644 --- a/Platform/Hisilicon/HiKey960/HiKey960.fdf +++ b/Platform/Hisilicon/HiKey960/HiKey960.fdf @@ -123,6 +123,8 @@ [FV.FvMain] INF Platform/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.inf INF ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf + INF Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf + # # USB Host Support # diff --git a/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.c b/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.c new file mode 100644 index 000000000000..154996026737 --- /dev/null +++ b/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.c @@ -0,0 +1,179 @@ +/** @file +* +* Copyright (c) 2018, Linaro Ltd. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include "HiKey960Dxe.h" + +STATIC UINTN mBoardId; + +STATIC +VOID +InitSdCard ( + IN VOID + ) +{ + UINT32 Data; + + // + // LDO16 + // + Data = MmioRead32 (PMU_REG_BASE + (0x79 << 2)) & 7; + Data |= 6; + MmioWrite32 (PMU_REG_BASE + (0x79 << 2), Data); + MmioOr32 (PMU_REG_BASE + (0x78 << 2), 2); + // + // wait regulator stable + // + MicroSecondDelay (100); + + // + // LDO9 + // + Data = MmioRead32 (PMU_REG_BASE + (0x6b << 2)) & 7; + Data |= 5; + MmioWrite32 (PMU_REG_BASE + (0x6b << 2), Data); + MmioOr32 (PMU_REG_BASE + (0x6a << 2), 2); + // + // wait regulator stable + // + MicroSecondDelay (100); + + // + // GPIO203 + // + MmioWrite32 (0xfff11000 + (24 << 2), 0); // GPIO function + + // + // SD pinmux + // + MmioWrite32 (IOMG_MMC0_000_REG, IOMG_FUNC1); // SD_CLK + MmioWrite32 (IOMG_MMC0_001_REG, IOMG_FUNC1); // SD_CMD + MmioWrite32 (IOMG_MMC0_002_REG, IOMG_FUNC1); // SD_DATA0 + MmioWrite32 (IOMG_MMC0_003_REG, IOMG_FUNC1); // SD_DATA1 + MmioWrite32 (IOMG_MMC0_004_REG, IOMG_FUNC1); // SD_DATA2 + MmioWrite32 (IOMG_MMC0_005_REG, IOMG_FUNC1); // SD_DATA3 + MmioWrite32 (IOCG_MMC0_000_REG, IOCG_DRIVE (15)); // SD_CLK float with 32mA + MmioWrite32 (IOCG_MMC0_001_REG, IOCG_PULLUP | IOCG_DRIVE (8)); // SD_CMD + MmioWrite32 (IOCG_MMC0_002_REG, IOCG_PULLUP | IOCG_DRIVE (8)); // SD_DATA0 + MmioWrite32 (IOCG_MMC0_003_REG, IOCG_PULLUP | IOCG_DRIVE (8)); // SD_DATA1 + MmioWrite32 (IOCG_MMC0_004_REG, IOCG_PULLUP | IOCG_DRIVE (8)); // SD_DATA2 + MmioWrite32 (IOCG_MMC0_005_REG, IOCG_PULLUP | IOCG_DRIVE (8)); // SD_DATA3 + + do { + MmioOr32 (CRG_REG_BASE + 0xb8, (1 << 6) | (1 << 6 << 16) | (0 << 4) | (3 << 4 << 16)); + Data = MmioRead32 (CRG_REG_BASE + 0xb8); + } while ((Data & ((1 << 6) | (3 << 4))) != ((1 << 6) | (0 << 4))); + + // + // Unreset SD controller + // + MmioWrite32 (CRG_PERRSTDIS4, PERRSTEN4_SD); + do { + Data = MmioRead32 (CRG_PERRSTSTAT4); + } while ((Data & PERRSTEN4_SD) == PERRSTEN4_SD); + // + // Enable SD controller clock + // + MmioOr32 (CRG_PEREN0, PEREN0_GT_HCLK_SD); + MmioOr32 (CRG_PEREN4, PEREN4_GT_CLK_SD); + do { + Data = MmioRead32 (CRG_PERCLKEN4); + } while ((Data & PEREN4_GT_CLK_SD) != PEREN4_GT_CLK_SD); +} + +VOID +InitPeripherals ( + IN VOID + ) +{ + // + // Enable FPLL0 + // + MmioOr32 (SCTRL_SCFPLLCTRL0, SCTRL_SCFPLLCTRL0_FPLL0_EN); + + InitSdCard (); + + // + // Enable wifi clock + // + MmioOr32 (PMIC_HARDWARE_CTRL0, PMIC_HARDWARE_CTRL0_WIFI_CLK); + MmioOr32 (PMIC_OSC32K_ONOFF_CTRL, PMIC_OSC32K_ONOFF_CTRL_EN_32K); +} + +/** + Notification function of the event defined as belonging to the + EFI_END_OF_DXE_EVENT_GROUP_GUID event group that was created in + the entry point of the driver. + + This function is called when an event belonging to the + EFI_END_OF_DXE_EVENT_GROUP_GUID event group is signalled. Such an + event is signalled once at the end of the dispatching of all + drivers (end of the so called DXE phase). + + @param[in] Event Event declared in the entry point of the driver whose + notification function is being invoked. + @param[in] Context NULL +**/ +STATIC +VOID +OnEndOfDxe ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + UINT32 BootMode; + + BootMode = MmioRead32 (SCTRL_BAK_DATA0) & BOOT_MODE_MASK; + if (BootMode == BOOT_MODE_RECOVERY) { + SerialPortWrite ((UINT8 *)"WARNING: CAN NOT BOOT KERNEL IN RECOVERY MODE!\r\n", 48); + SerialPortWrite ((UINT8 *)"Switch to normal boot mode, then reboot to boot kernel.\r\n", 57); + } +} + +EFI_STATUS +EFIAPI +HiKey960EntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_EVENT EndOfDxeEvent; + + Status = InitBoardId (&mBoardId); + if (EFI_ERROR (Status)) { + return Status; + } + + InitPeripherals (); + + // + // Create an event belonging to the "gEfiEndOfDxeEventGroupGuid" group. + // The "OnEndOfDxe()" function is declared as the call back function. + // It will be called at the end of the DXE phase when an event of the + // same group is signalled to inform about the end of the DXE phase. + // Install the INSTALL_FDT_PROTOCOL protocol. + // + Status = gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + OnEndOfDxe, + NULL, + &gEfiEndOfDxeEventGroupGuid, + &EndOfDxeEvent + ); + if (EFI_ERROR (Status)) { + return Status; + } + return Status; +} diff --git a/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.h b/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.h new file mode 100644 index 000000000000..2e89d10e2723 --- /dev/null +++ b/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.h @@ -0,0 +1,91 @@ +/** @file +* +* Copyright (c) 2018, Linaro Ltd. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __HIKEY960DXE_H__ +#define __HIKEY960DXE_H__ + +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ADC_ADCIN0 0 +#define ADC_ADCIN1 1 +#define ADC_ADCIN2 2 + +#define HKADC_DATA_GRADE0 0 +#define HKADC_DATA_GRADE1 100 +#define HKADC_DATA_GRADE2 300 +#define HKADC_DATA_GRADE3 500 +#define HKADC_DATA_GRADE4 700 +#define HKADC_DATA_GRADE5 900 +#define HKADC_DATA_GRADE6 1100 +#define HKADC_DATA_GRADE7 1300 +#define HKADC_DATA_GRADE8 1500 +#define HKADC_DATA_GRADE9 1700 +#define HKADC_DATA_GRADE10 1800 + +#define BOARDID_VALUE0 0 +#define BOARDID_VALUE1 1 +#define BOARDID_VALUE2 2 +#define BOARDID_VALUE3 3 +#define BOARDID_VALUE4 4 +#define BOARDID_VALUE5 5 +#define BOARDID_VALUE6 6 +#define BOARDID_VALUE7 7 +#define BOARDID_VALUE8 8 +#define BOARDID_VALUE9 9 +#define BOARDID_UNKNOWN 0xF + +#define BOARDID3_BASE 5 + +#define HIKEY960_BOARDID_V1 5300 +#define HIKEY960_BOARDID_V2 5301 + +#define HIKEY960_COMPATIBLE_LEDS_V1 "gpio-leds_v1" +#define HIKEY960_COMPATIBLE_LEDS_V2 "gpio-leds_v2" +#define HIKEY960_COMPATIBLE_HUB_V1 "hisilicon,gpio_hubv1" +#define HIKEY960_COMPATIBLE_HUB_V2 "hisilicon,gpio_hubv2" + +#define ADB_REBOOT_ADDRESS 0x32100000 +#define ADB_REBOOT_BOOTLOADER 0x77665500 +#define ADB_REBOOT_NONE 0x77665501 + +#define DETECT_SW_FASTBOOT 68 // GPIO8_4 + +enum { + BOOT_MODE_RECOVERY = 0, + BOOT_MODE_NORMAL, + BOOT_MODE_MASK = 1, +}; + +typedef struct { + UINTN DataGrade; + UINTN BoardidValue; +} HKADC_DATA; + +#endif /* __HIKEY960DXE_H__ */ diff --git a/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf b/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf new file mode 100644 index 000000000000..a1a7d005ce8b --- /dev/null +++ b/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf @@ -0,0 +1,47 @@ +# +# Copyright (c) 2018, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +[Defines] + INF_VERSION = 0x0001001a + BASE_NAME = HiKey960Dxe + FILE_GUID = 6d824b2c-640e-4643-b9f2-9c09e8bff429 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = HiKey960EntryPoint + +[Sources.common] + HiKey960Dxe.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Hisilicon/Hi3660/Hi3660.dec + +[LibraryClasses] + BaseMemoryLib + CacheMaintenanceLib + DxeServicesTableLib + IoLib + PcdLib + TimerLib + UefiDriverEntryPoint + UefiLib + +[Protocols] + gEmbeddedGpioProtocolGuid + +[Guids] + gEfiEndOfDxeEventGroupGuid + +[Depex] + TRUE diff --git a/Silicon/Hisilicon/Hi3660/Hi3660.dec b/Silicon/Hisilicon/Hi3660/Hi3660.dec new file mode 100644 index 000000000000..5c69ac4f19b8 --- /dev/null +++ b/Silicon/Hisilicon/Hi3660/Hi3660.dec @@ -0,0 +1,32 @@ +# +# Copyright (c) 2018, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +[Defines] + DEC_SPECIFICATION = 0x0001001a + PACKAGE_NAME = Hi3660 + PACKAGE_GUID = e457ba7c-faba-4dea-b274-f5962d016c79 + PACKAGE_VERSION = 0.1 + +################################################################################ +# +# Include Section - list of Include Paths that are provided by this package. +# Comments are used for Keywords and Module Types. +# +# Supported Module Types: +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION +# +################################################################################ +[Includes.common] + Include # Root include for the package + +[Guids.common] + gHi3660TokenSpaceGuid = { 0x4abc73fa, 0x8a49, 0x4d2c, { 0x95, 0x44, 0x17, 0x87, 0x29, 0x06, 0x20, 0xb4 } } diff --git a/Silicon/Hisilicon/Hi3660/Include/Hi3660.h b/Silicon/Hisilicon/Hi3660/Include/Hi3660.h new file mode 100644 index 000000000000..58974b9dd408 --- /dev/null +++ b/Silicon/Hisilicon/Hi3660/Include/Hi3660.h @@ -0,0 +1,175 @@ +/** @file +* +* Copyright (c) 2018, Linaro Ltd. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __HI3660_H__ +#define __HI3660_H__ + +#define HKADC_SSI_REG_BASE 0xE82B8000 + +#define PCTRL_REG_BASE 0xE8A09000 + +#define PCTRL_CTRL3 (PCTRL_REG_BASE + 0x010) +#define PCTRL_CTRL24 (PCTRL_REG_BASE + 0x064) + +#define PCTRL_CTRL3_USB_TXCO_EN (1 << 1) +#define PCTRL_CTRL24_USB3PHY_3MUX1_SEL (1 << 25) + +#define SCTRL_REG_BASE 0xFFF0A000 + +#define SCTRL_SCFPLLCTRL0 (SCTRL_REG_BASE + 0x120) +#define SCTRL_SCFPLLCTRL0_FPLL0_EN (1 << 0) + +#define SCTRL_BAK_DATA0 (SCTRL_REG_BASE + 0x40C) + +#define USB3OTG_BC_REG_BASE 0xFF200000 + +#define USB3OTG_CTRL0 (USB3OTG_BC_REG_BASE + 0x000) +#define USB3OTG_CTRL2 (USB3OTG_BC_REG_BASE + 0x008) +#define USB3OTG_CTRL3 (USB3OTG_BC_REG_BASE + 0x00C) +#define USB3OTG_CTRL4 (USB3OTG_BC_REG_BASE + 0x010) +#define USB3OTG_CTRL6 (USB3OTG_BC_REG_BASE + 0x018) +#define USB3OTG_CTRL7 (USB3OTG_BC_REG_BASE + 0x01C) +#define USB3OTG_PHY_CR_STS (USB3OTG_BC_REG_BASE + 0x050) +#define USB3OTG_PHY_CR_CTRL (USB3OTG_BC_REG_BASE + 0x054) + +#define USB3OTG_CTRL0_SC_USB3PHY_ABB_GT_EN (1 << 15) +#define USB3OTG_CTRL2_TEST_POWERDOWN_SSP (1 << 1) +#define USB3OTG_CTRL2_TEST_POWERDOWN_HSP (1 << 0) +#define USB3OTG_CTRL3_VBUSVLDEXT (1 << 6) +#define USB3OTG_CTRL3_VBUSVLDEXTSEL (1 << 5) +#define USB3OTG_CTRL7_REF_SSP_EN (1 << 16) +#define USB3OTG_PHY_CR_DATA_OUT(x) (((x) & 0xFFFF) << 1) +#define USB3OTG_PHY_CR_ACK (1 << 0) +#define USB3OTG_PHY_CR_DATA_IN(x) (((x) & 0xFFFF) << 4) +#define USB3OTG_PHY_CR_WRITE (1 << 3) +#define USB3OTG_PHY_CR_READ (1 << 2) +#define USB3OTG_PHY_CR_CAP_DATA (1 << 1) +#define USB3OTG_PHY_CR_CAP_ADDR (1 << 0) + +#define PMU_REG_BASE 0xFFF34000 +#define PMIC_HARDWARE_CTRL0 (PMU_REG_BASE + (0x0C5 << 2)) +#define PMIC_OSC32K_ONOFF_CTRL (PMU_REG_BASE + (0x0CC << 2)) + +#define PMIC_HARDWARE_CTRL0_WIFI_CLK (1 << 5) +#define PMIC_OSC32K_ONOFF_CTRL_EN_32K (1 << 1) + + +#define CRG_REG_BASE 0xFFF35000 + +#define CRG_PEREN0 (CRG_REG_BASE + 0x000) +#define CRG_PEREN2 (CRG_REG_BASE + 0x020) +#define CRG_PERDIS2 (CRG_REG_BASE + 0x024) +#define CRG_PERCLKEN2 (CRG_REG_BASE + 0x028) +#define CRG_PERSTAT2 (CRG_REG_BASE + 0x02C) +#define CRG_PEREN4 (CRG_REG_BASE + 0x040) +#define CRG_PERDIS4 (CRG_REG_BASE + 0x044) +#define CRG_PERCLKEN4 (CRG_REG_BASE + 0x048) +#define CRG_PERSTAT4 (CRG_REG_BASE + 0x04C) +#define CRG_PERRSTEN2 (CRG_REG_BASE + 0x078) +#define CRG_PERRSTDIS2 (CRG_REG_BASE + 0x07C) +#define CRG_PERRSTSTAT2 (CRG_REG_BASE + 0x080) +#define CRG_PERRSTEN3 (CRG_REG_BASE + 0x084) +#define CRG_PERRSTDIS3 (CRG_REG_BASE + 0x088) +#define CRG_PERRSTSTAT3 (CRG_REG_BASE + 0x08C) +#define CRG_PERRSTEN4 (CRG_REG_BASE + 0x090) +#define CRG_PERRSTDIS4 (CRG_REG_BASE + 0x094) +#define CRG_PERRSTSTAT4 (CRG_REG_BASE + 0x098) +#define CRG_ISOEN (CRG_REG_BASE + 0x144) +#define CRG_ISODIS (CRG_REG_BASE + 0x148) +#define CRG_ISOSTAT (CRG_REG_BASE + 0x14C) + +#define PERI_UFS_BIT (1 << 12) +#define PERI_ARST_UFS_BIT (1 << 7) + +#define PEREN0_GT_HCLK_SD BIT30 + +#define PEREN2_HKADCSSI BIT24 + +#define PEREN4_GT_CLK_SD BIT17 +#define PEREN4_GT_ACLK_USB3OTG (1 << 1) +#define PEREN4_GT_CLK_USB3OTG_REF (1 << 0) + +#define PERRSTEN2_HKADCSSI BIT24 + +#define PERRSTEN4_SD BIT18 + +#define PERRSTEN4_USB3OTG_MUX (1 << 8) +#define PERRSTEN4_USB3OTG_AHBIF (1 << 7) +#define PERRSTEN4_USB3OTG_32K (1 << 6) +#define PERRSTEN4_USB3OTG (1 << 5) +#define PERRSTEN4_USB3OTGPHY_POR (1 << 3) + +#define PERISOEN_USB_REFCLK_ISO_EN (1 << 25) + +#define CRG_CLKDIV16_OFFSET 0x0E8 +#define SC_DIV_UFSPHY_CFG_MASK (0x3 << 9) +#define SC_DIV_UFSPHY_CFG(x) (((x) & 0x3) << 9) + +#define CRG_CLKDIV17_OFFSET 0x0EC +#define SC_DIV_UFS_PERIBUS (1 << 14) + +#define IOMG_MMC0_REG_BASE 0xFF37E000 +#define IOMG_MMC0_000_REG (IOMG_MMC0_REG_BASE + 0x000) +#define IOMG_MMC0_001_REG (IOMG_MMC0_REG_BASE + 0x004) +#define IOMG_MMC0_002_REG (IOMG_MMC0_REG_BASE + 0x008) +#define IOMG_MMC0_003_REG (IOMG_MMC0_REG_BASE + 0x00C) +#define IOMG_MMC0_004_REG (IOMG_MMC0_REG_BASE + 0x010) +#define IOMG_MMC0_005_REG (IOMG_MMC0_REG_BASE + 0x014) + +#define IOCG_MMC0_REG_BASE 0xFF37E800 +#define IOCG_MMC0_000_REG (IOCG_MMC0_REG_BASE + 0x000) +#define IOCG_MMC0_001_REG (IOCG_MMC0_REG_BASE + 0x004) +#define IOCG_MMC0_002_REG (IOCG_MMC0_REG_BASE + 0x008) +#define IOCG_MMC0_003_REG (IOCG_MMC0_REG_BASE + 0x00C) +#define IOCG_MMC0_004_REG (IOCG_MMC0_REG_BASE + 0x010) +#define IOCG_MMC0_005_REG (IOCG_MMC0_REG_BASE + 0x014) + +#define IOMG_FUNC0 0 +#define IOMG_FUNC1 1 +#define IOCG_PULLUP BIT0 +#define IOCG_PULLDOWN BIT1 +#define IOCG_DRIVE(x) ((x) << 4) + +#define UFS_SYS_REG_BASE 0xFF3B1000 + +#define UFS_SYS_PSW_POWER_CTRL_OFFSET 0x004 +#define UFS_SYS_PHY_ISO_EN_OFFSET 0x008 +#define UFS_SYS_HC_LP_CTRL_OFFSET 0x00C +#define UFS_SYS_PHY_CLK_CTRL_OFFSET 0x010 +#define UFS_SYS_PSW_CLK_CTRL_OFFSET 0x014 +#define UFS_SYS_CLOCK_GATE_BYPASS_OFFSET 0x018 +#define UFS_SYS_RESET_CTRL_EN_OFFSET 0x01C +#define UFS_SYS_MONITOR_HH_OFFSET 0x03C +#define UFS_SYS_UFS_SYSCTRL_OFFSET 0x05C +#define UFS_SYS_UFS_DEVICE_RESET_CTRL_OFFSET 0x060 +#define UFS_SYS_UFS_APB_ADDR_MASK_OFFSET 0x064 + +#define BIT_UFS_PSW_ISO_CTRL (1 << 16) +#define BIT_UFS_PSW_MTCMOS_EN (1 << 0) +#define BIT_UFS_REFCLK_ISO_EN (1 << 16) +#define BIT_UFS_PHY_ISO_CTRL (1 << 0) +#define BIT_SYSCTRL_LP_ISOL_EN (1 << 16) +#define BIT_SYSCTRL_PWR_READY (1 << 8) +#define BIT_SYSCTRL_REF_CLOCK_EN (1 << 24) +#define MASK_SYSCTRL_REF_CLOCK_SEL (3 << 8) +#define MASK_SYSCTRL_CFG_CLOCK_FREQ (0xFF) +#define BIT_SYSCTRL_PSW_CLK_EN (1 << 4) +#define MASK_UFS_CLK_GATE_BYPASS (0x3F) +#define BIT_SYSCTRL_LP_RESET_N (1 << 0) +#define BIT_UFS_REFCLK_SRC_SE1 (1 << 0) +#define MASK_UFS_SYSCTRL_BYPASS (0x3F << 16) +#define MASK_UFS_DEVICE_RESET (1 << 16) +#define BIT_UFS_DEVICE_RESET (1 << 0) + +#endif /* __HI3660_H__ */ diff --git a/Silicon/Hisilicon/Hi3660/Include/Hkadc.h b/Silicon/Hisilicon/Hi3660/Include/Hkadc.h new file mode 100644 index 000000000000..990c0928eaab --- /dev/null +++ b/Silicon/Hisilicon/Hi3660/Include/Hkadc.h @@ -0,0 +1,68 @@ +/** @file +* +* Copyright (c) 2018, Linaro Ltd. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __HKADC_H__ +#define __HKADC_H__ + +#include + +#define HKADC_DSP_START (HKADC_SSI_REG_BASE + 0x000) +#define DSP_START_BIT BIT0 + +#define HKADC_WR_NUM (HKADC_SSI_REG_BASE + 0x008) +#define HKADC_DSP_START_CLR (HKADC_SSI_REG_BASE + 0x01C) +#define HKADC_WR01_DATA (HKADC_SSI_REG_BASE + 0x020) + +#define WR1_WRITE_MODE BIT31 +#define WR1_READ_MODE (0 << 31) +#define WR1_ADDR(x) (((x) & 0x7F) << 24) +#define WR1_DATA(x) (((x) & 0xFF) << 16) +#define WR0_WRITE_MODE BIT15 +#define WR0_READ_MODE (0 << 15) +#define WR0_ADDR(x) (((x) & 0x7F) << 8) +#define WR0_DATA(x) ((x) & 0xFF) + +#define HKADC_WR23_DATA (HKADC_SSI_REG_BASE + 0x024) +#define HKADC_WR45_DATA (HKADC_SSI_REG_BASE + 0x028) +#define HKADC_DELAY01 (HKADC_SSI_REG_BASE + 0x030) +#define HKADC_DELAY23 (HKADC_SSI_REG_BASE + 0x034) +#define HKADC_DELAY45 (HKADC_SSI_REG_BASE + 0x038) +#define HKADC_DSP_RD2_DATA (HKADC_SSI_REG_BASE + 0x048) +#define HKADC_DSP_RD3_DATA (HKADC_SSI_REG_BASE + 0x04C) + +// HKADC Internal Registers +#define HKADC_CTRL_ADDR 0x00 +#define HKADC_START_ADDR 0x01 +#define HKADC_DATA1_ADDR 0x03 // high 8 bits +#define HKADC_DATA0_ADDR 0x04 // low 8 bits +#define HKADC_MODE_CFG 0x0A + +#define HKADC_VALUE_HIGH 0x0FF0 +#define HKADC_VALUE_LOW 0x000F +#define HKADC_VALID_VALUE 0x0FFF + +#define HKADC_CHANNEL_MAX 15 +#define HKADC_VREF_1V8 1800 +#define HKADC_ACCURACY 0x0FFF + +#define HKADC_WR01_VALUE ((HKADC_START_ADDR << 24) | (0x1 << 16)) +#define HKADC_WR23_VALUE ((0x1 << 31) | (HKADC_DATA0_ADDR << 24) | (1 << 15) | (HKADC_DATA1_ADDR << 8)) +#define HKADC_WR45_VALUE (0x80) +#define HKADC_CHANNEL0_DELAY01_VALUE ((0x0700 << 16) | 0xFFFF) +#define HKADC_DELAY01_VALUE ((0x0700 << 16) | 0x0200) +#define HKADC_DELAY23_VALUE ((0x00C8 << 16) | 0x00C8) +#define START_DELAY_TIMEOUT 2000 +#define HKADC_WR_NUM_VALUE 4 + +#endif /* __HKADC_H__ */ -- 2.7.4