From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.101.70; helo=foss.arm.com; envelope-from=thomas.abraham@arm.com; receiver=edk2-devel@lists.01.org Received: from foss.arm.com (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by ml01.01.org (Postfix) with ESMTP id 3B31320965DD2 for ; Mon, 21 May 2018 01:26:03 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E1A8A1529; Mon, 21 May 2018 01:26:02 -0700 (PDT) Received: from usa.arm.com (a74716-lin.blr.arm.com [10.162.4.145]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id CE4BB3F25D; Mon, 21 May 2018 01:26:01 -0700 (PDT) From: Thomas Abraham To: edk2-devel@lists.01.org Cc: ard.biesheuvel@linaro.org, leif.lindholm@linaro.org Date: Mon, 21 May 2018 13:55:44 +0530 Message-Id: <1526891152-18739-2-git-send-email-thomas.abraham@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1526891152-18739-1-git-send-email-thomas.abraham@arm.com> References: <1526891152-18739-1-git-send-email-thomas.abraham@arm.com> Subject: [PATCH edk2-platforms v4 1/9] Platform/ARM/Sgi: Add Platform library implementation X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 21 May 2018 08:26:03 -0000 Add initial SGI platform library support. This includes the virtual memory map and helper functions for platform intialization. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Thomas Abraham --- Platform/ARM/SgiPkg/Include/SgiPlatform.h | 67 +++++++++++++ .../SgiPkg/Library/PlatformLib/AArch64/Helper.S | 65 +++++++++++++ .../ARM/SgiPkg/Library/PlatformLib/PlatformLib.c | 73 +++++++++++++++ .../ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf | 66 +++++++++++++ .../SgiPkg/Library/PlatformLib/PlatformLibMem.c | 104 +++++++++++++++++++++ 5 files changed, 375 insertions(+) create mode 100644 Platform/ARM/SgiPkg/Include/SgiPlatform.h create mode 100644 Platform/ARM/SgiPkg/Library/PlatformLib/AArch64/Helper.S create mode 100644 Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c create mode 100644 Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf create mode 100644 Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c diff --git a/Platform/ARM/SgiPkg/Include/SgiPlatform.h b/Platform/ARM/SgiPkg/Include/SgiPlatform.h new file mode 100644 index 0000000..441a467 --- /dev/null +++ b/Platform/ARM/SgiPkg/Include/SgiPlatform.h @@ -0,0 +1,67 @@ +/** @file +* +* Copyright (c) 2018, ARM Limited. All rights reserved. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __SGI_PLATFORM_H__ +#define __SGI_PLATFORM_H__ + +/*********************************************************************************** +// Platform Memory Map +************************************************************************************/ + +// Expansion AXI - SMC Chip Select 0 +#define SGI_EXP_SMC_CS0_BASE 0x08000000 +#define SGI_EXP_SMC_CS0_SZ SIZE_64MB + +// Expansion AXI - SMC Chip Select 1 +#define SGI_EXP_SMC_CS1_BASE 0x0C000000 +#define SGI_EXP_SMC_CS1_SZ SIZE_64MB + +// Expansion AXI - System peripherals +#define SGI_EXP_SYS_PERIPH_BASE 0x1C000000 +#define SGI_EXP_SYS_PERIPH_SZ SIZE_2MB + +// Base address of system peripherals +#define SGI_EXP_SYSPH_SYSTEM_REGISTERS 0x1C010000 +#define SGI_EXP_SYSPH_VIRTIO_BLOCK_BASE 0x1C130000 + +// Sub System Peripherals - UART0 +#define SGI_SUBSYS_UART0_BASE 0x2A400000 +#define SGI_SUBSYS_UART0_SZ 0x00010000 + +// Sub System Peripherals - UART1 +#define SGI_SUBSYS_UART1_BASE 0x2A410000 +#define SGI_SUBSYS_UART1_SZ 0x00010000 + +// Sub System Peripherals - Generic Watchdog +#define SGI_SUBSYS_GENERIC_WDOG_BASE 0x2A440000 +#define SGI_SUBSYS_GENERIC_WDOG_SZ SIZE_128KB + +// Sub System Peripherals - GIC +#define SGI_SUBSYS_GENERIC_GIC_BASE 0x30000000 +#define SGI_SUBSYS_GENERIC_GICR_BASE 0x300C0000 +#define SGI_SUBSYS_GENERIC_GIC_SZ SIZE_1MB + +// Expansion AXI - Platform Peripherals - UART0 +#define SGI_EXP_PLAT_PERIPH_UART0_BASE 0x7FF70000 +#define SGI_EXP_PLAT_PERIPH_UART0_SZ SIZE_64KB + +// Expansion AXI - Platform Peripherals - UART1 +#define SGI_EXP_PLAT_PERIPH_UART1_BASE 0x7FF80000 +#define SGI_EXP_PLAT_PERIPH_UART1_SZ SIZE_64KB + +// Register offsets into the System Registers Block +#define SGI_SYSPH_SYS_REG_FLASH 0x4C +#define SGI_SYSPH_SYS_REG_FLASH_RWEN 0x1 + +#endif // __SGI_PLATFORM_H__ diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/AArch64/Helper.S b/Platform/ARM/SgiPkg/Library/PlatformLib/AArch64/Helper.S new file mode 100644 index 0000000..dab6c77 --- /dev/null +++ b/Platform/ARM/SgiPkg/Library/PlatformLib/AArch64/Helper.S @@ -0,0 +1,65 @@ +/** @file +* +* Copyright (c) 2018, ARM Limited. All rights reserved. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include + +.text +.align 3 + +GCC_ASM_EXPORT(ArmPlatformPeiBootAction) +GCC_ASM_EXPORT(ArmPlatformGetCorePosition) +GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId) +GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore) + +// +// First platform specific function to be called in the PEI phase +// +// This function is actually the first function called by the PrePi +// or PrePeiCore modules. It allows to retrieve arguments passed to +// the UEFI firmware through the CPU registers. +// +ASM_PFX(ArmPlatformPeiBootAction): + ret + +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +// With this function: CorePos = (ClusterId * 2) + CoreId +ASM_PFX(ArmPlatformGetCorePosition): + and x1, x0, #ARM_CORE_MASK + and x0, x0, #ARM_CLUSTER_MASK + add x0, x1, x0, LSR #7 + ret + +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_PFX(ArmPlatformGetPrimaryCoreMpId): + MOV32 (w0, FixedPcdGet32(PcdArmPrimaryCore)) + ret + +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_PFX(ArmPlatformIsPrimaryCore): + MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCoreMask)) + and x0, x0, x1 + MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCore)) + cmp w0, w1 + cset x0, eq + ret diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c new file mode 100644 index 0000000..ea3201a --- /dev/null +++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c @@ -0,0 +1,73 @@ +/** @file +* +* Copyright (c) 2018, ARM Limited. All rights reserved. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include +#include + +STATIC ARM_CORE_INFO mCoreInfoTable[] = { + { + // Cluster 0, Core 0 + 0x0, 0x0, + }, +}; + +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + +RETURN_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + return RETURN_SUCCESS; +} + +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + *CoreCount = 1; + *ArmCoreTable = mCoreInfoTable; + return EFI_SUCCESS; +} + +STATIC ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { + PrePeiCoreGetMpCoreInfo +}; + +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + } +}; + +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + *PpiListSize = sizeof (gPlatformPpiTable); + *PpiList = gPlatformPpiTable; +} diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf new file mode 100644 index 0000000..1751cc2 --- /dev/null +++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf @@ -0,0 +1,66 @@ +# +# Copyright (c) 2018, ARM Limited. All rights reserved. +# +# This program and the accompanying materials are licensed and made available +# under the terms and conditions of the BSD License which accompanies this +# distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = ArmSgiLib + FILE_GUID = 1d0ee1e1-d791-4ecf-a43e-a9c76e674264 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = ArmPlatformLib + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Platform/ARM/SgiPkg/SgiPlatform.dec + +[LibraryClasses] + ArmLib + DebugLib + HobLib + IoLib + MemoryAllocationLib + SerialPortLib + +[Sources.common] + PlatformLibMem.c + PlatformLib.c + +[Sources.AARCH64] + AArch64/Helper.S | GCC + +[FixedPcd] + gArmPlatformTokenSpaceGuid.PcdClusterCount + gArmPlatformTokenSpaceGuid.PcdCoreCount + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + gArmTokenSpaceGuid.PcdFvBaseAddress + gArmTokenSpaceGuid.PcdArmPrimaryCore + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + + gArmTokenSpaceGuid.PcdPciMmio32Base + gArmTokenSpaceGuid.PcdPciMmio32Size + gArmTokenSpaceGuid.PcdPciMmio64Base + gArmTokenSpaceGuid.PcdPciMmio64Size + gArmSgiTokenSpaceGuid.PcdPciConfigurationSpaceBaseAddress + gArmSgiTokenSpaceGuid.PcdPciConfigurationSpaceSize + +[Guids] + gEfiHobListGuid ## CONSUMES ## SystemTable + +[Ppis] + gArmMpCoreInfoPpiGuid diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c new file mode 100644 index 0000000..9be71fb --- /dev/null +++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c @@ -0,0 +1,104 @@ +/** @file +* +* Copyright (c) 2018, ARM Limited. All rights reserved. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include +#include +#include +#include +#include + +#include + +// Total number of descriptors, including the final "end-of-table" descriptor. +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 8 + +/** + Returns the Virtual Memory Map of the platform. + + This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU + on your platform. + + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing + a Physical-to-Virtual Memory mapping. This array + must be ended by a zero-filled entry. +**/ +VOID +ArmPlatformGetVirtualMemoryMap ( + IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap + ) +{ + UINTN Index = 0; + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; + + ASSERT (VirtualMemoryMap != NULL); + + VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages + (EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * + MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS)); + if (VirtualMemoryTable == NULL) { + return; + } + + // Expansion AXI - SMC Chip Select 0 (NOR Flash) + VirtualMemoryTable[Index].PhysicalBase = SGI_EXP_SMC_CS0_BASE; + VirtualMemoryTable[Index].VirtualBase = SGI_EXP_SMC_CS0_BASE; + VirtualMemoryTable[Index].Length = SIZE_64MB; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // Expansion AXI - SMC Chip Select 1 (NOR Flash) + VirtualMemoryTable[++Index].PhysicalBase = SGI_EXP_SMC_CS1_BASE; + VirtualMemoryTable[Index].VirtualBase = SGI_EXP_SMC_CS1_BASE; + VirtualMemoryTable[Index].Length = SIZE_64MB; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // Expansion AXI - System Peripherals + VirtualMemoryTable[++Index].PhysicalBase = SGI_EXP_SYS_PERIPH_BASE; + VirtualMemoryTable[Index].VirtualBase = SGI_EXP_SYS_PERIPH_BASE; + VirtualMemoryTable[Index].Length = SGI_EXP_SYS_PERIPH_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // Sub System Peripherals - Generic Watchdog + VirtualMemoryTable[++Index].PhysicalBase = SGI_SUBSYS_GENERIC_WDOG_BASE; + VirtualMemoryTable[Index].VirtualBase = SGI_SUBSYS_GENERIC_WDOG_BASE; + VirtualMemoryTable[Index].Length = SGI_SUBSYS_GENERIC_WDOG_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // Sub System Peripherals - GIC-600 + VirtualMemoryTable[++Index].PhysicalBase = SGI_SUBSYS_GENERIC_GIC_BASE; + VirtualMemoryTable[Index].VirtualBase = SGI_SUBSYS_GENERIC_GIC_BASE; + VirtualMemoryTable[Index].Length = SGI_SUBSYS_GENERIC_GIC_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // Expansion AXI - Platform Peripherals - UART1 + VirtualMemoryTable[++Index].PhysicalBase = SGI_EXP_PLAT_PERIPH_UART1_BASE; + VirtualMemoryTable[Index].VirtualBase = SGI_EXP_PLAT_PERIPH_UART1_BASE; + VirtualMemoryTable[Index].Length = SGI_EXP_PLAT_PERIPH_UART1_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // DDR - (2GB - 16MB) + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase); + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase); + VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize); + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK; + + // End of Table + VirtualMemoryTable[++Index].PhysicalBase = 0; + VirtualMemoryTable[Index].VirtualBase = 0; + VirtualMemoryTable[Index].Length = 0; + VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0; + + ASSERT ((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + *VirtualMemoryMap = VirtualMemoryTable; +} -- 2.7.4