From: Leo Duran <leo.duran@amd.com>
To: edk2-devel@lists.01.org
Subject: [PATCH] Set FIFO Polled Mode on 16550 UART
Date: Thu, 24 May 2018 14:07:29 -0500 [thread overview]
Message-ID: <1527188850-4553-1-git-send-email-leo.duran@amd.com> (raw)
This patch ensures the 16500 UART is initialiazed in FIFO Polled Mode.
For an example, please see:
http://www.ti.com/lit/ds/symlink/pc16550d.pdf
8.4.2 FIFO Polled Mode Operation
With FCR0=1 resetting IER0, IER1, IER2, IER3 or all to zero puts the UART
in the FIFO Polled Mode of operation.
Leo Duran (1):
MdeModulePkg/Library/BaseSerialPortLib16550: Ensure FIFO Polled Mode
.../BaseSerialPortLib16550/BaseSerialPortLib16550.c | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
--
2.7.4
next reply other threads:[~2018-05-24 19:07 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-24 19:07 Leo Duran [this message]
2018-05-24 19:07 ` [PATCH] MdeModulePkg/Library/BaseSerialPortLib16550: Ensure FIFO Polled Mode Leo Duran
2018-05-25 8:20 ` Ni, Ruiyu
2018-05-25 11:13 ` Zeng, Star
2018-05-25 13:38 ` Duran, Leo
2018-06-05 21:21 ` Duran, Leo
2018-06-06 0:43 ` Zeng, Star
2018-06-06 1:05 ` Duran, Leo
2018-06-06 9:07 ` Zeng, Star
2018-06-09 23:30 ` Duran, Leo
2018-06-11 2:41 ` Zeng, Star
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