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20:BBwa+21NhJS//MXcE/m8icHec3l98oJWkcgRysKkTY12QUCVns+pLiIbinEYwgANX/VZtwzgdWxha2eJnF8kdTp74bRsge42iu3kDb6+wonTu/WGUPHpV3nM3b6pAFFnIBJaItMme8opVojGVdRGqCE+qROOS1Af9mBD0/AOc4VHw203L1APoeuKxJoqYf9rpGmZzHiENN5DpuLI/KbrLrO/dZsTx0J45NZw3DTAfIACtlvrxBfUqJZ+yBn+7EBf X-MS-Office365-Filtering-Correlation-Id: 0553e80f-e05e-40e3-bb12-08d5c1a99f4b X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 May 2018 19:07:40.6945 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0553e80f-e05e-40e3-bb12-08d5c1a99f4b X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1811 Subject: [PATCH] Set FIFO Polled Mode on 16550 UART X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 24 May 2018 19:07:43 -0000 Content-Type: text/plain This patch ensures the 16500 UART is initialiazed in FIFO Polled Mode. For an example, please see: http://www.ti.com/lit/ds/symlink/pc16550d.pdf 8.4.2 FIFO Polled Mode Operation With FCR0=1 resetting IER0, IER1, IER2, IER3 or all to zero puts the UART in the FIFO Polled Mode of operation. Leo Duran (1): MdeModulePkg/Library/BaseSerialPortLib16550: Ensure FIFO Polled Mode .../BaseSerialPortLib16550/BaseSerialPortLib16550.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) -- 2.7.4