From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::242; helo=mail-lf0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org Received: from mail-lf0-x242.google.com (mail-lf0-x242.google.com [IPv6:2a00:1450:4010:c07::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7FEF9210D6CC4 for ; Fri, 1 Jun 2018 07:32:22 -0700 (PDT) Received: by mail-lf0-x242.google.com with SMTP id v135-v6so15157375lfa.9 for ; Fri, 01 Jun 2018 07:32:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=f82/LRK7vCVhE5XNu3ulUEUzYe8HVDi762/4cBaJE0E=; b=HKlZSnurkLCKAIFdifQj36NeV9GyBl3XzLvhUqaD22XahnXbsChNu+M2Cpfq9xC77e CnrtnCd8RqmDfVnF+M8skELfgiWZ/hPdVE6pwg4UYLhIVuJDRJZqPAY6j2ib15BzPVKb ID3+Q4brMC+ZZBHlt7yL2g3m5AxJd8ZXmHx/r/la3SIFmJebK5xk4hgwgOWAdgTUbWSS XbYyFnx1kCusL43ngxv2B9eThzmRBtujkkqz6lyhea7eMBUXjgdakJkE9siXkPf2RDVC F0pIl9PNLiyomSkdNhD1V2yHgYT4BtKwXaNXDv+IM4hapxu15Mfr9GAI3E0eAEp2+5S/ +ICA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=f82/LRK7vCVhE5XNu3ulUEUzYe8HVDi762/4cBaJE0E=; b=Y6CijU+DARYpao4uNvHM5sa83Etf4pNU3pzf1p/ojpyFcZfkJsvQWUdBcp5schW1OG 1hLfPCs/bTpdO4Ieq49X73QpCdMjVbBQ7F5PpGkSKGVEYFeHpPrkHCew4Fj+rKn7L5mr 0ylUvje6/zp1kvFNp/CGe/U8qNLPPv8DzODIAkhoOAwl7kGXAw2QhBjKbo/lxIpd+BnI yHUhf+x32IpYKnIoc35bDStw0GAGO44+wy0DE1s4QQoZBZo5z3zjoBGtpNhvvCshqz3a UwcBtopn/1V56yhSFsRfUYt4ogcp/wD9Eqcyy18hBIpa3GRjRzoINuls9gMDsf8ptGp9 EULA== X-Gm-Message-State: ALKqPwdBdu/turdEa2SWLuZUP1AaVyq6pYF+hbLs9HX1nM5OBlZaLBzo 5NktpxXnjvbuqW4dpvcvpe1yN8nzBgM= X-Google-Smtp-Source: ADUXVKLT6Y6kfjrJb0QheFMeW+JsjjhldyI0SNLRI1KTo2wzjtim4mCTYcyVlnqUrCpiLnehaUDbrA== X-Received: by 2002:a2e:5f1a:: with SMTP id t26-v6mr8583304ljb.0.1527863540194; Fri, 01 Jun 2018 07:32:20 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id 4-v6sm1524064ljc.1.2018.06.01.07.32.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 01 Jun 2018 07:32:19 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jinghua@marvell.com, jaz@semihalf.com, davidsn@marvell.com Date: Fri, 1 Jun 2018 16:32:03 +0200 Message-Id: <1527863526-5494-2-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1527863526-5494-1-git-send-email-mw@semihalf.com> References: <1527863526-5494-1-git-send-email-mw@semihalf.com> Subject: [platforms PATCH 1/4] Marvell/Armada70x0Db: Shift main FV from 0x0 address X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 01 Jun 2018 14:32:23 -0000 When using PEI phase, UEFI interprets 0x0 address of boot FV as an error. In order to avoid it, shift it to 0x1000 and put a hardcoded 'jump to 0x1000' at offset 0x0. This patch is a preparation for using PEI by Armada platforms. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf b/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf index befb107..69cb4cd 100644 --- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf +++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf @@ -49,7 +49,21 @@ NumBlocks = 0x400 # ################################################################################ -0x00000000|0x00100000 +# +# UEFI has trouble dealing with FVs that reside at physical address 0x0. +# So instead, put a hardcoded 'jump to 0x1000' at offset 0x0, and put the +# real FV at offset 0x1000 +# +0x00000000|0x00001000 +DATA = { +!if $(ARCH) == AARCH64 + 0x00, 0x04, 0x00, 0x14 # 'b 0x1000' in AArch64 ASM +!else + 0xfe, 0x03, 0x00, 0xea # 'b 0x1000' in AArch32 ASM +!endif +} + +0x00001000|0x000ff000 gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize FV = FVMAIN_COMPACT @@ -191,7 +205,6 @@ FvNameGuid = 5eda4200-2c5f-43cb-9da3-0baf74b1b30c # PEI phase firmware volume [FV.FVMAIN_COMPACT] FvAlignment = 8 -FvForceRebase = TRUE ERASE_POLARITY = 1 MEMORY_MAPPED = TRUE STICKY_WRITE = TRUE -- 2.7.4