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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id v79-v6sm7355396lfd.32.2018.06.08.08.34.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Jun 2018 08:34:54 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, jinghua@marvell.com, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com Date: Fri, 8 Jun 2018 17:34:09 +0200 Message-Id: <1528472063-1660-12-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528472063-1660-1-git-send-email-mw@semihalf.com> References: <1528472063-1660-1-git-send-email-mw@semihalf.com> Subject: [platforms PATCH 11/25] Marvell/Armada7k8k: Extend ArmadaSoCDescLib with AHCI/SDMMC/XHCI X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jun 2018 15:34:58 -0000 This patch introduces new library callbacks for NonDiscoverable devices i.e. AHCI/XHCI/SDMMC. They dynamically allocate and fill according structures with the SoC description of the devices. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Hua Jing --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c | 114 ++++++++++++++++++++ Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h | 48 +++++++++ 2 files changed, 162 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c index 36b445e..de57b47 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c @@ -32,6 +32,120 @@ #define MV_SOC_CP_BASE(Cp) (0xF2000000 + (Cp) * 0x2000000) // +// Platform description of NonDiscoverableDevices +// + +// +// Platform description of AHCI controllers +// +#define MV_SOC_AHCI_BASE(Cp) MV_SOC_CP_BASE ((Cp)) + 0x540000 +#define MV_SOC_AHCI_ID(Cp) ((Cp) % 2) + +EFI_STATUS +EFIAPI +ArmadaSoCDescAhciGet ( + IN OUT MV_SOC_AHCI_DESC **AhciDesc, + IN OUT UINT8 *DescCount + ) +{ + MV_SOC_AHCI_DESC *Desc; + UINT8 CpCount = FixedPcdGet8 (PcdMaxCpCount); + UINT8 CpIndex; + + Desc = AllocateZeroPool (CpCount * sizeof (MV_SOC_AHCI_DESC)); + if (Desc == NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + for (CpIndex = 0; CpIndex < CpCount; CpIndex++) { + Desc[CpIndex].AhciId = MV_SOC_AHCI_ID (CpIndex); + Desc[CpIndex].AhciBaseAddress = MV_SOC_AHCI_BASE (CpIndex); + Desc[CpIndex].AhciMemSize = SIZE_8KB; + Desc[CpIndex].AhciDmaType = NonDiscoverableDeviceDmaTypeCoherent; + } + + *AhciDesc = Desc; + *DescCount = CpCount; + + return EFI_SUCCESS; +} + +// +// Platform description of SDMMC controllers +// +#define MV_SOC_MAX_SDMMC_COUNT 2 +#define MV_SOC_SDMMC_BASE(Index) ((Index) == 0 ? 0xF06E0000 : 0xF2780000) + +EFI_STATUS +EFIAPI +ArmadaSoCDescSdMmcGet ( + IN OUT MV_SOC_SDMMC_DESC **SdMmcDesc, + IN OUT UINT8 *DescCount + ) +{ + MV_SOC_SDMMC_DESC *Desc; + UINT8 Index; + + Desc = AllocateZeroPool (MV_SOC_MAX_SDMMC_COUNT * sizeof (MV_SOC_SDMMC_DESC)); + if (Desc == NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + for (Index = 0; Index < MV_SOC_MAX_SDMMC_COUNT; Index++) { + Desc[Index].SdMmcBaseAddress = MV_SOC_SDMMC_BASE (Index); + Desc[Index].SdMmcMemSize = SIZE_1KB; + Desc[Index].SdMmcDmaType = NonDiscoverableDeviceDmaTypeCoherent; + } + + *SdMmcDesc = Desc; + *DescCount = MV_SOC_MAX_SDMMC_COUNT; + + return EFI_SUCCESS; +} + +// +// Platform description of XHCI controllers +// +#define MV_SOC_XHCI_PER_CP_COUNT 2 +#define MV_SOC_XHCI_BASE(Xhci) (0x500000 + (Xhci) * 0x10000) + +EFI_STATUS +EFIAPI +ArmadaSoCDescXhciGet ( + IN OUT MV_SOC_XHCI_DESC **XhciDesc, + IN OUT UINT8 *DescCount + ) +{ + MV_SOC_XHCI_DESC *Desc; + UINT8 CpCount = FixedPcdGet8 (PcdMaxCpCount); + UINT8 Index, CpIndex, XhciIndex = 0; + + Desc = AllocateZeroPool (CpCount * MV_SOC_XHCI_PER_CP_COUNT * + sizeof (MV_SOC_XHCI_DESC)); + if (Desc == NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + for (CpIndex = 0; CpIndex < CpCount; CpIndex++) { + for (Index = 0; Index < MV_SOC_XHCI_PER_CP_COUNT; Index++) { + Desc[XhciIndex].XhciBaseAddress = + MV_SOC_CP_BASE (CpIndex) + MV_SOC_XHCI_BASE (Index); + Desc[XhciIndex].XhciMemSize = SIZE_16KB; + Desc[XhciIndex].XhciDmaType = NonDiscoverableDeviceDmaTypeCoherent; + XhciIndex++; + } + } + + *XhciDesc = Desc; + *DescCount = XhciIndex; + + return EFI_SUCCESS; +} + +// // Platform description of PP2 NIC // #define MV_SOC_PP2_BASE(Cp) MV_SOC_CP_BASE ((Cp)) diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h index 559642b..438f838 100644 --- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h @@ -14,6 +14,54 @@ #ifndef __ARMADA_SOC_DESC_LIB_H__ #define __ARMADA_SOC_DESC_LIB_H__ +#include + +// +// NonDiscoverable devices SoC description +// +// AHCI +typedef struct { + UINT8 AhciId; + UINTN AhciBaseAddress; + UINTN AhciMemSize; + NON_DISCOVERABLE_DEVICE_DMA_TYPE AhciDmaType; +} MV_SOC_AHCI_DESC; + +EFI_STATUS +EFIAPI +ArmadaSoCDescAhciGet ( + IN OUT MV_SOC_AHCI_DESC **AhciDesc, + IN OUT UINT8 *DescCount + ); + +// SDMMC +typedef struct { + UINTN SdMmcBaseAddress; + UINTN SdMmcMemSize; + NON_DISCOVERABLE_DEVICE_DMA_TYPE SdMmcDmaType; +} MV_SOC_SDMMC_DESC; + +EFI_STATUS +EFIAPI +ArmadaSoCDescSdMmcGet ( + IN OUT MV_SOC_SDMMC_DESC **SdMmcDesc, + IN OUT UINT8 *DescCount + ); + +// XHCI +typedef struct { + UINTN XhciBaseAddress; + UINTN XhciMemSize; + NON_DISCOVERABLE_DEVICE_DMA_TYPE XhciDmaType; +} MV_SOC_XHCI_DESC; + +EFI_STATUS +EFIAPI +ArmadaSoCDescXhciGet ( + IN OUT MV_SOC_XHCI_DESC **XhciDesc, + IN OUT UINT8 *DescCount + ); + // // PP2 NIC devices SoC description // -- 2.7.4