[platforms: PATCH v2 0/4] Armada7k8k new boards support

[platforms: PATCH v2 0/4] Armada7k8k new boards support

[Marcin Wojtas]

Hi,

v2 of the boards support adds NOOPT flag to all Armada boards
and upgrades version of the new files to 0x1A.

The patches are available in the github:
https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/boards-upstream-r20180613

I'm looking forward to review and any comments/remarks.

Best regards,
Marcin


Marcin Wojtas (4):
  Marvell/Armada7k8k: Use common .fdf file
  Marvell/Armada7k8k: Introduce support for Armada-8040-McBin
  Marvell/Armada7k8k: Introduce support for Armada-8040-Db
  Marvell/Armada70x0Db: Enable building with NOOPT flag

 Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc                                              |   4 +-
 Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc                                              | 158 ++++++++++++++++++++
 Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc                                       | 149 ++++++++++++++++++
 Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf => Silicon/Marvell/Armada7k8k/Armada7k8k.fdf |   2 +-
 4 files changed, 310 insertions(+), 3 deletions(-)
 create mode 100644 Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc
 create mode 100644 Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
 rename Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf => Silicon/Marvell/Armada7k8k/Armada7k8k.fdf (97%)

-- 
2.7.4

[platforms: PATCH v2 1/4] Marvell/Armada7k8k: Use common .fdf file

[Marcin Wojtas]

As for the preparation for adding multiple boards support,
move common part of the .fdf file to the SoC family directory
and change output FD file name to more generic.

Once needed, possible per-board differences will be resolved
by including custom .fdf.inc file. This way adding new common
changes for entire SoC family won't require any
duplication and at the same time the per-board .fdf.inc
will allow better suiting the .FD file contents.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
 Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc                                              | 2 +-
 Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf => Silicon/Marvell/Armada7k8k/Armada7k8k.fdf | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)
 rename Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf => Silicon/Marvell/Armada7k8k/Armada7k8k.fdf (97%)

diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc
index 46a1ea9..eedb025 100644
--- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc
+++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc
@@ -43,7 +43,7 @@
   SUPPORTED_ARCHITECTURES        = AARCH64|ARM
   BUILD_TARGETS                  = DEBUG|RELEASE
   SKUID_IDENTIFIER               = DEFAULT
-  FLASH_DEFINITION               = Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf
+  FLASH_DEFINITION               = Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
 
 !include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
 
diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf b/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
similarity index 97%
rename from Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf
rename to Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
index e5e5443..180b6c9 100644
--- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf
+++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
@@ -24,7 +24,7 @@
 #
 ################################################################################
 
-[FD.Armada70x0Db_EFI]
+[FD.Armada_EFI]
 BaseAddress   = 0x00000000|gArmTokenSpaceGuid.PcdFdBaseAddress  # The base address of the Firmware in NOR Flash.
 Size          = 0x00400000|gArmTokenSpaceGuid.PcdFdSize         # The size in bytes of the FLASH Device
 ErasePolarity = 1
-- 
2.7.4

[platforms: PATCH v2 2/4] Marvell/Armada7k8k: Introduce support for Armada-8040-McBin

[Marcin Wojtas]

Add new board description file Armada80x0McBin.dsc,
which uses common Armada7k8k.fdf file. By default
build capsule components.
Most of the interfaces are fully functional, except for:
- USB ports - it requires merging GPIO support and VBUS
  power supply enabling
- SdMmc ports - they are kept enabled, as no issues were
  observed on v1.3 board so far. However higher speed modes
  (HS200) and full stability will be gained after Xenon
  driver improvements merge.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
 Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc | 149 ++++++++++++++++++++
 1 file changed, 149 insertions(+)
 create mode 100644 Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc

diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
new file mode 100644
index 0000000..8230d67
--- /dev/null
+++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
@@ -0,0 +1,149 @@
+#Copyright (C) 2017 Marvell International Ltd.
+#
+#Marvell BSD License Option
+#
+#If you received this File from Marvell, you may opt to use, redistribute and/or
+#modify this File under the following licensing terms.
+#Redistribution and use in source and binary forms, with or without modification,
+#are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Marvell nor the names of its contributors may be
+# used to endorse or promote products derived from this software without
+# specific prior written permission.
+#
+#THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+#ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+#WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+#DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+#ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+#(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+#LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+#ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+#(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+#SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                  = Armada80x0McBin
+  PLATFORM_GUID                  = 256e46dc-bff2-4e83-8ab3-6d2a3bec3f62
+  PLATFORM_VERSION               = 0.1
+  DSC_SPECIFICATION              = 0x0001001A
+  OUTPUT_DIRECTORY               = Build/$(PLATFORM_NAME)-$(ARCH)
+  SUPPORTED_ARCHITECTURES        = AARCH64|ARM
+  BUILD_TARGETS                  = DEBUG|RELEASE|NOOPT
+  SKUID_IDENTIFIER               = DEFAULT
+  FLASH_DEFINITION               = Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
+  CAPSULE_ENABLE                 = TRUE
+
+!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsFixedAtBuild.common]
+  #MPP
+  gMarvellTokenSpaceGuid.PcdMppChipCount|3
+
+  # APN806-A0 MPP SET
+  gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
+  gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
+  gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20
+  gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
+  gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 }
+
+  # CP110 MPP SET - master
+  gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE
+  gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000
+  gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64
+  gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+  gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+  gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+  gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xFF, 0x0, 0x7, 0xA, 0x7, 0x2, 0x2, 0x2, 0x2, 0xA }
+  gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x7, 0x7, 0x8, 0x8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+  gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x0, 0x0, 0x9, 0x0, 0x0, 0x0, 0xE, 0xE, 0xE, 0xE }
+  gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+
+  # CP110 MPP SET - slave
+  gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE
+  gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000
+  gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64
+  gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x8, 0x8, 0x0, 0x0 }
+  gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x3, 0x3, 0x3, 0x3, 0x3, 0xFF, 0xFF, 0xFF }
+  gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0x0, 0xFF, 0x0, 0x0, 0x0, 0x0 }
+  gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0x0, 0x0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+  gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+  gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+  gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+
+  #SPI
+  gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF4700680
+  gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000
+  gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000
+
+  gMarvellTokenSpaceGuid.PcdSpiFlashMode|3
+  gMarvellTokenSpaceGuid.PcdSpiFlashCs|0
+
+  #ComPhy
+  gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 }
+  # ComPhy0
+  # 0: PCIE0         5 Gbps
+  # 1: PCIE0         5 Gbps
+  # 2: PCIE0         5 Gbps
+  # 3: PCIE0         5 Gbps
+  # 4: SFI           10.31 Gbps
+  # 5: SATA1         5 Gbps
+  gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1)}
+  gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G) }
+  # ComPhy1
+  # 0: SGMII1        1.25 Gbps
+  # 1: SATA0         5 Gbps
+  # 2: USB3_HOST0    5 Gbps
+  # 3: SATA1         5 Gbps
+  # 4: SFI           10.31 Gbps
+  # 5: SGMII2        3.125 Gbps
+  gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_SGMII1), $(CP_SATA2), $(CP_USB3_HOST0), $(CP_SATA3), $(CP_SFI), $(CP_SGMII2) }
+  gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_1_25G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_3_125G) }
+
+  #UtmiPhy
+  gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x1, 0x0 }
+  gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
+
+  #MDIO
+  gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 }
+
+  #PHY
+  gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0 }
+  gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0 }
+  gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 }
+  gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
+
+  #NET
+  gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x0, 0x2, 0x3 }
+  gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 }
+  gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_2500) }
+  gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_SFI), $(PHY_SGMII), $(PHY_SGMII) }
+  gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0xFF, 0x0, 0xFF }
+  gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x1, 0x1, 0x1 }
+  gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x0, 0x1, 0x2 }
+  gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 }
+
+  #PciEmulation
+  gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x1, 0x0 }
+  gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 }
+  gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
+
+  #RTC
+  gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x0, 0x1 }
-- 
2.7.4

[platforms: PATCH v2 3/4] Marvell/Armada7k8k: Introduce support for Armada-8040-Db

[Marcin Wojtas]

Add new board description file Armada80x0Db.dsc,
which uses common Armada7k8k.fdf file.
Most of the interfaces are fully functional, except for:
- USB ports - it requires merging GPIO support and VBUS
  power supply enabling

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
 Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc | 158 ++++++++++++++++++++
 1 file changed, 158 insertions(+)
 create mode 100644 Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc

diff --git a/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc b/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc
new file mode 100644
index 0000000..582e939
--- /dev/null
+++ b/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc
@@ -0,0 +1,158 @@
+#Copyright (C) 2017 Marvell International Ltd.
+#
+#Marvell BSD License Option
+#
+#If you received this File from Marvell, you may opt to use, redistribute and/or
+#modify this File under the following licensing terms.
+#Redistribution and use in source and binary forms, with or without modification,
+#are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Marvell nor the names of its contributors may be
+# used to endorse or promote products derived from this software without
+# specific prior written permission.
+#
+#THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+#ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+#WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+#DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+#ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+#(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+#LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+#ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+#(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+#SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                  = Armada80x0Db
+  PLATFORM_GUID                  = 5cc803a0-9c42-498e-9086-e176d4a1f598
+  PLATFORM_VERSION               = 0.1
+  DSC_SPECIFICATION              = 0x0001001A
+  OUTPUT_DIRECTORY               = Build/$(PLATFORM_NAME)-$(ARCH)
+  SUPPORTED_ARCHITECTURES        = AARCH64|ARM
+  BUILD_TARGETS                  = DEBUG|RELEASE|NOOPT
+  SKUID_IDENTIFIER               = DEFAULT
+  FLASH_DEFINITION               = Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
+
+!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsFixedAtBuild.common]
+  #MPP
+  gMarvellTokenSpaceGuid.PcdMppChipCount|3
+
+  # APN806-A0 MPP SET
+  gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
+  gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
+  gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20
+  gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
+  gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 }
+
+  # CP110 MPP SET - master
+  gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE
+  gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000
+  gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64
+  gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+  gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+  gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+  gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xFF, 0xFF, 0x7,  0x0,  0x7,  0xA,  0xA,  0x2,  0x2,  0x5  }
+  gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x9,  0x9,  0x8,  0x8,  0x1,  0x1,  0x1,  0x1,  0x1,  0x1  }
+  gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x1,  0x1,  0x1,  0x1,  0x1,  0x1,  0xE,  0xE,  0xE,  0xE  }
+  gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE,  0xE,  0xE,  0x0,  0x0,  0x0,  0x0,  0x0,  0x0,  0x0  }
+
+  # CP110 MPP SET - slave
+  gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE
+  gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000
+  gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64
+  gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x3,  0x3,  0x3,  0x3,  0x3,  0x3,  0x3,  0x3,  0x3,  0x3  }
+  gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x3,  0x3,  0x3,  0x3,  0x3,  0x3,  0x3,  0xFF, 0xFF, 0xFF }
+  gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x8,  0x9,  0xA  }
+  gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0xA,  0x8,  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+  gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+  gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+  gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0,  0x0,  0x0,  0x0,  0x0,  0x0,  0x0  }
+
+  # I2C
+  gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57, 0x50, 0x57, 0x21, 0x25 }
+  gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x1, 0x1, 0x0, 0x0 }
+  gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x1, 0x0, 0x1 }
+  gMarvellTokenSpaceGuid.PcdEepromI2cAddresses|{ 0x50, 0x57, 0x50, 0x57 }
+  gMarvellTokenSpaceGuid.PcdEepromI2cBuses|{ 0x0, 0x0, 0x1, 0x1 }
+  gMarvellTokenSpaceGuid.PcdI2cClockFrequency|250000000
+  gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000
+  gMarvellTokenSpaceGuid.PcdI2cBusCount|2
+
+  #SPI
+  gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF4700680
+  gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000
+  gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000
+
+  gMarvellTokenSpaceGuid.PcdSpiFlashMode|3
+  gMarvellTokenSpaceGuid.PcdSpiFlashCs|0
+
+  #ComPhy
+  gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 }
+  # ComPhy0
+  # 0: PCIE0         5 Gbps
+  # 1: SATA0         5 Gbps
+  # 2: SFI           10.31 Gbps
+  # 3: SATA1         5 Gbps
+  # 4: USB_HOST1     5 Gbps
+  # 5: PCIE2         5 Gbps
+  gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_SATA0), $(CP_SFI), $(CP_SATA1), $(CP_USB3_HOST1), $(CP_PCIE2) }
+  gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G), $(CP_5G), $(CP_5G) }
+  # ComPhy1
+  # 0: PCIE0         5 Gbps
+  # 1: SATA0         5 Gbps
+  # 2: SFI           10.31 Gbps
+  # 3: SATA1         5 Gbps
+  # 4: PCIE1         5 Gbps
+  # 5: PCIE2         5 Gbps
+  gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_PCIE0), $(CP_SATA2), $(CP_SFI), $(CP_SATA3), $(CP_PCIE1), $(CP_PCIE2) }
+  gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5_15625G), $(CP_5G), $(CP_5G), $(CP_5G) }
+
+  #UtmiPhy
+  gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x1, 0x0 }
+  gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
+
+  #MDIO
+  gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x1 }
+
+  #PHY
+  gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x1 }
+  gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 }
+  gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x1, 0x0 }
+  gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
+
+  #NET
+  gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x3, 0x0, 0x2 }
+  gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 }
+  gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_10000), $(PHY_SPEED_1000) }
+  gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII), $(PHY_SFI), $(PHY_RGMII) }
+  gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF, 0x1 }
+  gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x1, 0x1 }
+  gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x2, 0x0, 0x1 }
+  gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 }
+
+  #PciEmulation
+  gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x1, 0x0 }
+  gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 }
+  gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
+
+  #RTC
+  gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x0, 0x1 }
-- 
2.7.4

[platforms: PATCH v2 4/4] Marvell/Armada70x0Db: Enable building with NOOPT flag

[Marcin Wojtas]

Newly added boards can build with TARGET set to NOOPT,
so align the Armada70x0Db.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
 Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc
index eedb025..68813f8 100644
--- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc
+++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc
@@ -41,7 +41,7 @@
   DSC_SPECIFICATION              = 0x00010005
   OUTPUT_DIRECTORY               = Build/$(PLATFORM_NAME)-$(ARCH)
   SUPPORTED_ARCHITECTURES        = AARCH64|ARM
-  BUILD_TARGETS                  = DEBUG|RELEASE
+  BUILD_TARGETS                  = DEBUG|RELEASE|NOOPT
   SKUID_IDENTIFIER               = DEFAULT
   FLASH_DEFINITION               = Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
 
-- 
2.7.4

Re: [platforms: PATCH v2 0/4] Armada7k8k new boards support

[Leif Lindholm]

On Wed, Jun 13, 2018 at 11:02:49AM +0200, Marcin Wojtas wrote:
> Hi,
> 
> v2 of the boards support adds NOOPT flag to all Armada boards
> and upgrades version of the new files to 0x1A.
> 
> The patches are available in the github:
> https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/boards-upstream-r20180613
> 
> I'm looking forward to review and any comments/remarks.

For me:
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

But I'll wait until Ard has had the time to have a look before I push
anything.

Regards,

Leif

> Best regards,
> Marcin
> 
> 
> Marcin Wojtas (4):
>   Marvell/Armada7k8k: Use common .fdf file
>   Marvell/Armada7k8k: Introduce support for Armada-8040-McBin
>   Marvell/Armada7k8k: Introduce support for Armada-8040-Db
>   Marvell/Armada70x0Db: Enable building with NOOPT flag
> 
>  Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc                                              |   4 +-
>  Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc                                              | 158 ++++++++++++++++++++
>  Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc                                       | 149 ++++++++++++++++++
>  Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf => Silicon/Marvell/Armada7k8k/Armada7k8k.fdf |   2 +-
>  4 files changed, 310 insertions(+), 3 deletions(-)
>  create mode 100644 Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc
>  create mode 100644 Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
>  rename Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf => Silicon/Marvell/Armada7k8k/Armada7k8k.fdf (97%)
> 
> -- 
> 2.7.4
> 

Re: [platforms: PATCH v2 0/4] Armada7k8k new boards support

[Ard Biesheuvel]

On 13 June 2018 at 16:23, Leif Lindholm <leif.lindholm@linaro.org> wrote:
> On Wed, Jun 13, 2018 at 11:02:49AM +0200, Marcin Wojtas wrote:
>> Hi,
>>
>> v2 of the boards support adds NOOPT flag to all Armada boards
>> and upgrades version of the new files to 0x1A.
>>
>> The patches are available in the github:
>> https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/boards-upstream-r20180613
>>
>> I'm looking forward to review and any comments/remarks.
>
> For me:
> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
>
> But I'll wait until Ard has had the time to have a look before I push
> anything.
>

Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

Re: [platforms: PATCH v2 0/4] Armada7k8k new boards support

[Leif Lindholm]

On Wed, Jun 13, 2018 at 05:10:08PM +0200, Ard Biesheuvel wrote:
> On 13 June 2018 at 16:23, Leif Lindholm <leif.lindholm@linaro.org> wrote:
> > On Wed, Jun 13, 2018 at 11:02:49AM +0200, Marcin Wojtas wrote:
> >> Hi,
> >>
> >> v2 of the boards support adds NOOPT flag to all Armada boards
> >> and upgrades version of the new files to 0x1A.
> >>
> >> The patches are available in the github:
> >> https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/boards-upstream-r20180613
> >>
> >> I'm looking forward to review and any comments/remarks.
> >
> > For me:
> > Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> >
> > But I'll wait until Ard has had the time to have a look before I push
> > anything.
> >
> 
> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

Thanks - series pushed as 1160c702c2..1cd14dea5f.

/
    Leif

Re: [platforms: PATCH v2 0/4] Armada7k8k new boards support

[Marcin Wojtas]

2018-06-13 17:35 GMT+02:00 Leif Lindholm <leif.lindholm@linaro.org>:
> On Wed, Jun 13, 2018 at 05:10:08PM +0200, Ard Biesheuvel wrote:
>> On 13 June 2018 at 16:23, Leif Lindholm <leif.lindholm@linaro.org> wrote:
>> > On Wed, Jun 13, 2018 at 11:02:49AM +0200, Marcin Wojtas wrote:
>> >> Hi,
>> >>
>> >> v2 of the boards support adds NOOPT flag to all Armada boards
>> >> and upgrades version of the new files to 0x1A.
>> >>
>> >> The patches are available in the github:
>> >> https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/boards-upstream-r20180613
>> >>
>> >> I'm looking forward to review and any comments/remarks.
>> >
>> > For me:
>> > Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
>> >
>> > But I'll wait until Ard has had the time to have a look before I push
>> > anything.
>> >
>>
>> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>
> Thanks - series pushed as 1160c702c2..1cd14dea5f.
>

Thanks a lot!

Marcin