From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::241; helo=mail-lf0-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org Received: from mail-lf0-x241.google.com (mail-lf0-x241.google.com [IPv6:2a00:1450:4010:c07::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 87C222097213B for ; Sun, 17 Jun 2018 13:12:49 -0700 (PDT) Received: by mail-lf0-x241.google.com with SMTP id i15-v6so21569694lfc.2 for ; Sun, 17 Jun 2018 13:12:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lbOgbNOJmzUnogAwGfzVR8jgxMOu+u3H5A+jLVFwFJU=; b=kPWsBKKvMR/oJn8N4z2ACnDf62iino8W2+8bxAQgKlgVxo4/69HF0rZmhKVcnYz3z8 WgeM3jn/76PGySQt1tEsGYgnBtRKZMhd1cnYggNMcSo98mWw6SYubFjmfNN8buFHlOL6 T8wdYU7MNj9gi5bK6hOyuz3pp5t+3H6QN27BoB7xPUq3+8sLAkb2UrHLLWgYzTqQdnUX cID18gf7aRmT0JfhEosM9BCXNg5L2IyOxUfGAQckrSrCNvgMVvDw36hSZXv71SKefufr BXxDcQ+6V5bJWoPTtiBJMJbBJC3gtx4Wsf+SH5MvhhVeyFQX/VAJY6l4DGEqc5Bjfvys MZRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lbOgbNOJmzUnogAwGfzVR8jgxMOu+u3H5A+jLVFwFJU=; b=UBm8/QPd+4CWdpjG4Jj7Jf2OalSsCT8xMnKUH0teXKpFbe28kRUcZadDOoL5KTlbok 6gwHb3Z4/lXdLEcLAKd+XXL+YqtOmQXT9il2w+MaD9e+BD1AJ6u0W5SftSK7eTcb2uBz 0SHkXbK/GEsmX4x0heww4yMzjlCkLqhuSTLwWZc93+w3+FF6V5wQ5aIyLIV6qLAe9+xk t0I4rR6r9tY36UL64YqvjyvvXilOMklABSVXyIcTUQRdDGlARNtS1ocgVkBJGcunypoW PaiDrNsowRvwNSl9BhihsTPm3tVqZDcc9HBiji8u2dKrmmu2m0gJ/tP6+xCRDfi1qAje Uf0w== X-Gm-Message-State: APt69E0zVW3JChsMk+bVyjIcEVTosE1IlEXIF81YqiNdE6WLiMfwTuGF iqUjIwtUEa5aFSoWvKV3m0EdZTAcZ9w= X-Google-Smtp-Source: ADUXVKLUq3vAMnFh+cGqxSiysNUoEsQaqdxm7WArnCaytFS14o27m2u5Ewl94sy1phOpagS4pOD6mw== X-Received: by 2002:a19:5c12:: with SMTP id q18-v6mr3803074lfb.145.1529266367593; Sun, 17 Jun 2018 13:12:47 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id q75-v6sm387272lfq.47.2018.06.17.13.12.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 17 Jun 2018 13:12:46 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, jinghua@marvell.com, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com Date: Sun, 17 Jun 2018 22:11:57 +0200 Message-Id: <1529266325-18371-18-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529266325-18371-1-git-send-email-mw@semihalf.com> References: <1529266325-18371-1-git-send-email-mw@semihalf.com> Subject: [platforms: PATCH v2 17/25] Marvell/Library: ComPhyLib: Switch library to use MARVELL_BOARD_DESC X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 17 Jun 2018 20:12:50 -0000 MvComPhyLib library used to get Armada7k8k SerDes multiplexing controller description from hardcoded values stored in the header file MvHwDescLib.h. As a result it is very hard to support other Armada SoC families with this library. This patch updates the library, so that it can obtain the description from newly introduced MARVELL_BOARD_DESC protocol, and removes the dependency on the hardcoded structures. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Include/Library/MvHwDescLib.h | 39 ----------- Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c | 74 ++++++++++++-------- 2 files changed, 45 insertions(+), 68 deletions(-) diff --git a/Silicon/Marvell/Include/Library/MvHwDescLib.h b/Silicon/Marvell/Include/Library/MvHwDescLib.h index 9f383f4..423ca17 100644 --- a/Silicon/Marvell/Include/Library/MvHwDescLib.h +++ b/Silicon/Marvell/Include/Library/MvHwDescLib.h @@ -35,8 +35,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #ifndef __MVHWDESCLIB_H__ #define __MVHWDESCLIB_H__ -#include - // // Helper macros // @@ -45,20 +43,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define MVHW_DEV_ENABLED(type, index) (type ## DeviceTable[index]) // -// CommonPhy devices description template definition -// -#define MVHW_MAX_COMPHY_DEVS 4 - -typedef struct { - UINT8 ComPhyDevCount; - UINTN ComPhyBaseAddresses[MVHW_MAX_COMPHY_DEVS]; - UINTN ComPhyHpipe3BaseAddresses[MVHW_MAX_COMPHY_DEVS]; - UINTN ComPhyLaneCount[MVHW_MAX_COMPHY_DEVS]; - UINTN ComPhyMuxBitCount[MVHW_MAX_COMPHY_DEVS]; - MV_COMPHY_CHIP_TYPE ComPhyChipType[MVHW_MAX_COMPHY_DEVS]; -} MVHW_COMPHY_DESC; - -// // I2C devices description template definition // #define MVHW_MAX_I2C_DEVS 4 @@ -79,29 +63,6 @@ typedef struct { } MVHW_MDIO_DESC; // -// Platform description of CommonPhy devices -// -#define MVHW_CP0_COMPHY_BASE 0xF2441000 -#define MVHW_CP0_HPIPE3_BASE 0xF2120000 -#define MVHW_CP0_COMPHY_LANES 6 -#define MVHW_CP0_COMPHY_MUX_BITS 4 -#define MVHW_CP1_COMPHY_BASE 0xF4441000 -#define MVHW_CP1_HPIPE3_BASE 0xF4120000 -#define MVHW_CP1_COMPHY_LANES 6 -#define MVHW_CP1_COMPHY_MUX_BITS 4 - -#define DECLARE_A7K8K_COMPHY_TEMPLATE \ -STATIC \ -MVHW_COMPHY_DESC mA7k8kComPhyDescTemplate = {\ - 2,\ - { MVHW_CP0_COMPHY_BASE, MVHW_CP1_COMPHY_BASE },\ - { MVHW_CP0_HPIPE3_BASE, MVHW_CP1_HPIPE3_BASE },\ - { MVHW_CP0_COMPHY_LANES, MVHW_CP1_COMPHY_LANES },\ - { MVHW_CP0_COMPHY_MUX_BITS, MVHW_CP1_COMPHY_MUX_BITS },\ - { MvComPhyTypeCp110, MvComPhyTypeCp110 }\ -} - -// // Platform description of I2C devices // #define MVHW_CP0_I2C0_BASE 0xF2701000 diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c index b03bc35..2ef9af4 100644 --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c @@ -34,9 +34,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "ComPhyLib.h" #include -#include - -DECLARE_A7K8K_COMPHY_TEMPLATE; CHAR16 * TypeStringTable [] = {L"unconnected", L"PCIE0", L"PCIE1", L"PCIE2", L"PCIE3", L"SATA0", L"SATA1", L"SATA2", L"SATA3", @@ -182,22 +179,20 @@ VOID InitComPhyConfig ( IN OUT CHIP_COMPHY_CONFIG *ChipConfig, IN OUT PCD_LANE_MAP *LaneData, - IN UINT8 Id + IN MV_BOARD_COMPHY_DESC *Desc ) { - MVHW_COMPHY_DESC *Desc = &mA7k8kComPhyDescTemplate; - - ChipConfig->ChipType = Desc->ComPhyChipType[Id]; - ChipConfig->ComPhyBaseAddr = Desc->ComPhyBaseAddresses[Id]; - ChipConfig->Hpipe3BaseAddr = Desc->ComPhyHpipe3BaseAddresses[Id]; - ChipConfig->LanesCount = Desc->ComPhyLaneCount[Id]; - ChipConfig->MuxBitCount = Desc->ComPhyMuxBitCount[Id]; - ChipConfig->ChipId = Id; + ChipConfig->ChipType = Desc->SoC->ComPhyChipType; + ChipConfig->ComPhyBaseAddr = Desc->SoC->ComPhyBaseAddress; + ChipConfig->Hpipe3BaseAddr = Desc->SoC->ComPhyHpipe3BaseAddress; + ChipConfig->LanesCount = Desc->SoC->ComPhyLaneCount; + ChipConfig->MuxBitCount = Desc->SoC->ComPhyMuxBitCount; + ChipConfig->ChipId = Desc->SoC->ComPhyId; /* * Below macro contains variable name concatenation (used to form PCD's name). */ - switch (Id) { + switch (ChipConfig->ChipId) { case 0: GetComPhyPcd (LaneData, 0); break; @@ -219,32 +214,49 @@ MvComPhyInit ( ) { EFI_STATUS Status; - CHIP_COMPHY_CONFIG ChipConfig[MVHW_MAX_COMPHY_DEVS], *PtrChipCfg; - PCD_LANE_MAP LaneData[MVHW_MAX_COMPHY_DEVS]; + CHIP_COMPHY_CONFIG *ChipConfig, *PtrChipCfg; + MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol; + MV_BOARD_COMPHY_DESC *ComPhyBoardDesc; + PCD_LANE_MAP *LaneData; UINT32 Lane, MaxComphyCount; - UINT8 *ComPhyDeviceTable, Index; + UINTN Index; /* Obtain table with enabled ComPhy devices */ - ComPhyDeviceTable = (UINT8 *)PcdGetPtr (PcdComPhyDevices); - if (ComPhyDeviceTable == NULL) { - DEBUG ((DEBUG_ERROR, "Missing PcdComPhyDevices\n")); - return EFI_INVALID_PARAMETER; + Status = gBS->LocateProtocol (&gMarvellBoardDescProtocolGuid, + NULL, + (VOID **)&BoardDescProtocol); + if (EFI_ERROR (Status)) { + return Status; + } + + Status = BoardDescProtocol->BoardDescComPhyGet (BoardDescProtocol, + &ComPhyBoardDesc); + if (EFI_ERROR (Status)) { + return Status; } - if (PcdGetSize (PcdComPhyDevices) > MVHW_MAX_COMPHY_DEVS) { - DEBUG ((DEBUG_ERROR, "Wrong PcdComPhyDevices format\n")); - return EFI_INVALID_PARAMETER; + ChipConfig = AllocateZeroPool (ComPhyBoardDesc->ComPhyDevCount * + sizeof (CHIP_COMPHY_CONFIG)); + if (ChipConfig == NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + BoardDescProtocol->BoardDescFree (ComPhyBoardDesc); + return EFI_OUT_OF_RESOURCES; + } + + LaneData = AllocateZeroPool (ComPhyBoardDesc->ComPhyDevCount * + sizeof (PCD_LANE_MAP)); + if (ChipConfig == NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + BoardDescProtocol->BoardDescFree (ComPhyBoardDesc); + FreePool (ChipConfig); + return EFI_OUT_OF_RESOURCES; } /* Initialize enabled chips */ - for (Index = 0; Index < PcdGetSize (PcdComPhyDevices); Index++) { - if (!MVHW_DEV_ENABLED (ComPhy, Index)) { - DEBUG ((DEBUG_ERROR, "Skip ComPhy chip %d\n", Index)); - continue; - } + for (Index = 0; Index < ComPhyBoardDesc->ComPhyDevCount; Index++) { PtrChipCfg = &ChipConfig[Index]; - InitComPhyConfig(PtrChipCfg, LaneData, Index); + InitComPhyConfig (PtrChipCfg, LaneData, &ComPhyBoardDesc[Index]); /* Get the count of the SerDes of the specific chip */ MaxComphyCount = PtrChipCfg->LanesCount; @@ -275,5 +287,9 @@ MvComPhyInit ( PtrChipCfg->Init (PtrChipCfg); } + BoardDescProtocol->BoardDescFree (ComPhyBoardDesc); + FreePool (ChipConfig); + FreePool (LaneData); + return EFI_SUCCESS; } -- 2.7.4