From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::243; helo=mail-lf0-x243.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org Received: from mail-lf0-x243.google.com (mail-lf0-x243.google.com [IPv6:2a00:1450:4010:c07::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 66B6A2110A000 for ; Mon, 18 Jun 2018 15:59:13 -0700 (PDT) Received: by mail-lf0-x243.google.com with SMTP id p23-v6so15465111lfh.11 for ; Mon, 18 Jun 2018 15:59:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ag6qi/ZHHx6IR7akOXVNm/PIl53moxExvDj7wQ3kj9s=; b=N/yDATYtbXab3u4WBFaFuIqJwq3/TZxsD3BD+6zm+5bQ7MElPinZmxxOcTiFd/YW52 d49IG8uyaGeeNvrfHtn5DDxVbi2jFgcpMAvIbUpGxJqiBasY95hi+okTT/IDqPY133Dz FRpqlibXWru/N4bs3Ns0pD8u2n+MVb14n7jPDf71R/XemTtABSuXC+5iJ10L2aJBH5ha w7Z2ny/bU6As/DXUHTomiV8I2de4XL6UWHy9u2EUpvayj0McBPB9xTKRLa2Bo9G0OHeu FKCyBzGi0L7XlWwFnzfCF51PXEsMEBtdH122ARjC1I4luHLjZPJYqnuTE9XYmsr1RykV PRYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ag6qi/ZHHx6IR7akOXVNm/PIl53moxExvDj7wQ3kj9s=; b=s22xuD/36JsZY2o2HmdE+mHfC5CEoB7bpjjz5e7/j4VF73kyJJxT/OYmzLPOzfmsXt 7NNnKNkLcI8TbRWTJl5AfpCCH72nQ2qGh2vEYgVn6fsF74/AObBquAwkZNAz27C7Fee9 DVi0oMWk8HWUGANq2LJ47XXR92WQVUXjo2z1usTrTzxPZ1nitt29pH9s7LcMk2hW/iSy GeqeBm4Hqe2jxZ5BiJUhCraTfsrKwzCsB5Tl1A7qWfZTqZ5+7nvOYLNDdnskhN2/SYQw 9KhK+x9x1hqEc938RnqWV6scy3eMthrilT5qmSHMuNr4FUmhjs37/0lI/QvxVcjPMvQr DjAg== X-Gm-Message-State: APt69E2Tb4DxQsoAv6y8/qP/9O7B2BMG36G5BOyMbBTwYpu0VubyDDkc DRYK0q1MyK4k/fTNZL+LMfz2PhScEB0= X-Google-Smtp-Source: ADUXVKIM4/oG7cxxhAN8LLuRVIK/U6rfOHBNpPmZIjFxOmk+fjWtw0+R8Tlsua6b99ccdynQcMDZKg== X-Received: by 2002:a2e:330b:: with SMTP id d11-v6mr9135508ljc.67.1529362751419; Mon, 18 Jun 2018 15:59:11 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id h136-v6sm3020754lfe.23.2018.06.18.15.59.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 Jun 2018 15:59:10 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, jinghua@marvell.com, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com Date: Tue, 19 Jun 2018 00:58:29 +0200 Message-Id: <1529362724-9244-11-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529362724-9244-1-git-send-email-mw@semihalf.com> References: <1529362724-9244-1-git-send-email-mw@semihalf.com> Subject: [platforms: PATCH v3 10/25] Marvell/Drivers: Pp2Dxe: Switch to use MARVELL_BOARD_DESC protocol X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 18 Jun 2018 22:59:14 -0000 Pp2Dxe driver used to get Armada7k8k PP2 controller description from hardcoded values stored in the header file MvHwDescLib.h. As a result it is very hard to support other Armada SoC families with this driver. This patch updates the driver to get PP2 controller description from newly introduced MARVELL_BOARD_DESC protocol, and removes the dependency on the hardcoded structures. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf | 2 +- Silicon/Marvell/Include/Library/MvHwDescLib.h | 26 ------------ Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c | 43 ++++++++------------ 3 files changed, 19 insertions(+), 52 deletions(-) diff --git a/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf b/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf index fcd0611..be536ab 100644 --- a/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf +++ b/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf @@ -67,11 +67,11 @@ gEfiSimpleNetworkProtocolGuid gEfiDevicePathProtocolGuid gEfiCpuArchProtocolGuid + gMarvellBoardDescProtocolGuid gMarvellMdioProtocolGuid gMarvellPhyProtocolGuid [Pcd] - gMarvellTokenSpaceGuid.PcdPp2Controllers gMarvellTokenSpaceGuid.PcdPp2GopIndexes gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed diff --git a/Silicon/Marvell/Include/Library/MvHwDescLib.h b/Silicon/Marvell/Include/Library/MvHwDescLib.h index 34d03d4..5fd514c 100644 --- a/Silicon/Marvell/Include/Library/MvHwDescLib.h +++ b/Silicon/Marvell/Include/Library/MvHwDescLib.h @@ -105,17 +105,6 @@ typedef struct { } MVHW_NONDISCOVERABLE_DESC; // -// PP2 NIC devices description template definition -// -#define MVHW_MAX_PP2_DEVS 4 - -typedef struct { - UINT8 Pp2DevCount; - UINTN Pp2BaseAddresses[MVHW_MAX_PP2_DEVS]; - UINTN Pp2ClockFrequency[MVHW_MAX_PP2_DEVS]; -} MVHW_PP2_DESC; - -// // Platform description of CommonPhy devices // #define MVHW_CP0_COMPHY_BASE 0xF2441000 @@ -200,19 +189,4 @@ MVHW_NONDISCOVERABLE_DESC mA7k8kNonDiscoverableDescTemplate = {\ { NonDiscoverableDeviceDmaTypeCoherent, NonDiscoverableDeviceDmaTypeCoherent }\ } -// -// Platform description of Pp2 NIC devices -// -#define MVHW_CP0_PP2_BASE 0xF2000000 -#define MVHW_CP1_PP2_BASE 0xF4000000 -#define MVHW_PP2_CLK_FREQ 333333333 - -#define DECLARE_A7K8K_PP2_TEMPLATE \ -STATIC \ -MVHW_PP2_DESC mA7k8kPp2DescTemplate = {\ - 2,\ - { MVHW_CP0_PP2_BASE, MVHW_CP1_PP2_BASE },\ - { MVHW_PP2_CLK_FREQ, MVHW_PP2_CLK_FREQ } \ -} - #endif /* __MVHWDESCLIB_H__ */ diff --git a/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c b/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c index 3ed10f6..02b2798 100644 --- a/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c +++ b/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c @@ -32,6 +32,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *******************************************************************************/ +#include #include #include #include @@ -42,7 +43,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include #include #include -#include #include #include #include @@ -54,8 +54,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define ReturnUnlock(tpl, status) do { gBS->RestoreTPL (tpl); return (status); } while(0) -DECLARE_A7K8K_PP2_TEMPLATE; - STATIC PP2_DEVICE_PATH Pp2DevicePathTemplate = { { { @@ -1343,35 +1341,28 @@ Pp2DxeInitialise ( IN EFI_SYSTEM_TABLE *SystemTable ) { - MVHW_PP2_DESC *Desc = &mA7k8kPp2DescTemplate; - UINT8 *Pp2DeviceTable, Index; + MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol; + MV_BOARD_PP2_DESC *Pp2BoardDesc; MVPP2_SHARED *Mvpp2Shared; EFI_STATUS Status; + UINTN Index; /* Obtain table with enabled Pp2 devices */ - Pp2DeviceTable = (UINT8 *)PcdGetPtr (PcdPp2Controllers); - if (Pp2DeviceTable == NULL) { - DEBUG ((DEBUG_ERROR, "Missing PcdPp2Controllers\n")); - return EFI_INVALID_PARAMETER; - } - - if (PcdGetSize (PcdPp2Controllers) > MVHW_MAX_PP2_DEVS) { - DEBUG ((DEBUG_ERROR, "Wrong PcdPp2Controllers format\n")); - return EFI_INVALID_PARAMETER; + Status = gBS->LocateProtocol (&gMarvellBoardDescProtocolGuid, + NULL, + (VOID **)&BoardDescProtocol); + if (EFI_ERROR (Status)) { + return Status; } - /* Check amount of declared ports */ - if (PcdGetSize (PcdPp2Port2Controller) > Desc->Pp2DevCount * MVPP2_MAX_PORT) { - DEBUG ((DEBUG_ERROR, "Pp2Dxe: Wrong too many ports declared\n")); - return EFI_INVALID_PARAMETER; + Status = BoardDescProtocol->BoardDescPp2Get (BoardDescProtocol, + &Pp2BoardDesc); + if (EFI_ERROR (Status)) { + return Status; } /* Initialize enabled chips */ - for (Index = 0; Index < PcdGetSize (PcdPp2Controllers); Index++) { - if (!MVHW_DEV_ENABLED (Pp2, Index)) { - DEBUG ((DEBUG_ERROR, "Skip Pp2 controller %d\n", Index)); - continue; - } + for (Index = 0; Index < Pp2BoardDesc->Pp2DevCount; Index++) { /* Initialize private data */ Mvpp2Shared = AllocateZeroPool (sizeof (MVPP2_SHARED)); @@ -1383,8 +1374,8 @@ Pp2DxeInitialise ( Status = Pp2DxeInitialiseController ( Index, Mvpp2Shared, - Desc->Pp2BaseAddresses[Index], - Desc->Pp2ClockFrequency[Index] + Pp2BoardDesc[Index].SoC->Pp2BaseAddress, + Pp2BoardDesc[Index].SoC->Pp2ClockFrequency ); if (EFI_ERROR(Status)) { FreePool (Mvpp2Shared); @@ -1393,5 +1384,7 @@ Pp2DxeInitialise ( } } + BoardDescProtocol->BoardDescFree (Pp2BoardDesc); + return EFI_SUCCESS; } -- 2.7.4