[platforms: PATCH v3 15/25] Marvell/Armada7k8k: Extend ArmadaSoCDescLib with ComPhy information

[Marcin Wojtas <mw@semihalf.com>]

This patch introduces new library callback (ArmadaSoCDescComPhyGet ()),
which dynamically allocates and fills MV_SOC_COMPHY_DESC structure with
the SoC description of ComPhy SerDes controllers.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
 Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h |  8 +++++
 Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h                             | 20 ++++++++++++
 Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c | 33 ++++++++++++++++++++
 3 files changed, 61 insertions(+)

diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h
index d7557e8..f254b1c 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h
@@ -30,6 +30,14 @@
 #define MV_SOC_AHCI_ID(Cp)               ((Cp) % 2)
 
 //
+// Platform description of ComPhy controllers
+//
+#define MV_SOC_COMPHY_BASE(Cp)           (MV_SOC_CP_BASE (Cp) + 0x441000)
+#define MV_SOC_HPIPE3_BASE(Cp)           (MV_SOC_CP_BASE (Cp) + 0x120000)
+#define MV_SOC_COMPHY_LANE_COUNT         6
+#define MV_SOC_COMPHY_MUX_BITS           4
+
+//
 // Platform description of PP2 NIC
 //
 #define MV_SOC_PP2_BASE(Cp)              MV_SOC_CP_BASE (Cp)
diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h
index 3b29d78..a133d1c 100644
--- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h
+++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h
@@ -14,9 +14,29 @@
 #ifndef __ARMADA_SOC_DESC_LIB_H__
 #define __ARMADA_SOC_DESC_LIB_H__
 
+#include <Library/MvComPhyLib.h>
 #include <Library/NonDiscoverableDeviceRegistrationLib.h>
 
 //
+// ComPhy SoC description
+//
+typedef struct {
+  UINTN ComPhyId;
+  UINTN ComPhyBaseAddress;
+  UINTN ComPhyHpipe3BaseAddress;
+  UINTN ComPhyLaneCount;
+  UINTN ComPhyMuxBitCount;
+  MV_COMPHY_CHIP_TYPE ComPhyChipType;
+} MV_SOC_COMPHY_DESC;
+
+EFI_STATUS
+EFIAPI
+ArmadaSoCDescComPhyGet (
+  IN OUT MV_SOC_COMPHY_DESC  **ComPhyDesc,
+  IN OUT UINTN                *DescCount
+  );
+
+//
 // NonDiscoverable devices SoC description
 //
 // AHCI
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c
index 97fe3f8..580c0f4 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c
@@ -30,6 +30,39 @@
 
 EFI_STATUS
 EFIAPI
+ArmadaSoCDescComPhyGet (
+  IN OUT MV_SOC_COMPHY_DESC  **ComPhyDesc,
+  IN OUT UINTN                *DescCount
+  )
+{
+  MV_SOC_COMPHY_DESC *Desc;
+  UINTN CpCount, CpIndex;
+
+  CpCount = FixedPcdGet8 (PcdMaxCpCount);
+
+  Desc = AllocateZeroPool (CpCount * sizeof (MV_SOC_COMPHY_DESC));
+  if (Desc == NULL) {
+    DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__));
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  for (CpIndex = 0; CpIndex < CpCount; CpIndex++) {
+    Desc[CpIndex].ComPhyBaseAddress = MV_SOC_COMPHY_BASE (CpIndex);
+    Desc[CpIndex].ComPhyHpipe3BaseAddress = MV_SOC_HPIPE3_BASE (CpIndex);
+    Desc[CpIndex].ComPhyLaneCount = MV_SOC_COMPHY_LANE_COUNT;
+    Desc[CpIndex].ComPhyMuxBitCount = MV_SOC_COMPHY_MUX_BITS;
+    Desc[CpIndex].ComPhyChipType = MvComPhyTypeCp110;
+    Desc[CpIndex].ComPhyId = CpIndex;
+  }
+
+  *ComPhyDesc = Desc;
+  *DescCount = CpCount;
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
 ArmadaSoCDescAhciGet (
   IN OUT MV_SOC_AHCI_DESC  **AhciDesc,
   IN OUT UINTN              *DescCount
-- 
2.7.4