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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id h136-v6sm3020754lfe.23.2018.06.18.15.59.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 Jun 2018 15:59:21 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, jinghua@marvell.com, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com Date: Tue, 19 Jun 2018 00:58:37 +0200 Message-Id: <1529362724-9244-19-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529362724-9244-1-git-send-email-mw@semihalf.com> References: <1529362724-9244-1-git-send-email-mw@semihalf.com> Subject: [platforms: PATCH v3 18/25] Marvell/Armada7k8k: Extend ArmadaSoCDescLib with MDIO information X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 18 Jun 2018 22:59:25 -0000 This patch introduces new library callback (ArmadaSoCDescMdioGet ()), which dynamically allocates and fills MV_SOC_MDIO_DESC structure with the SoC description of Mdio controllers. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h | 6 ++++ Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h | 15 ++++++++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c | 29 ++++++++++++++++++++ 3 files changed, 50 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h index f254b1c..87fc140 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h @@ -38,6 +38,12 @@ #define MV_SOC_COMPHY_MUX_BITS 4 // +// Platform description of MDIO controllers +// +#define MV_SOC_MDIO_BASE(Cp) (MV_SOC_CP_BASE (Cp) + 0x12A200) +#define MV_SOC_MDIO_ID(Cp) (Cp) + +// // Platform description of PP2 NIC // #define MV_SOC_PP2_BASE(Cp) MV_SOC_CP_BASE (Cp) diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h index a133d1c..304d068 100644 --- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h @@ -37,6 +37,21 @@ ArmadaSoCDescComPhyGet ( ); // +// MDIO +// +typedef struct { + UINTN MdioId; + UINTN MdioBaseAddress; +} MV_SOC_MDIO_DESC; + +EFI_STATUS +EFIAPI +ArmadaSoCDescMdioGet ( + IN OUT MV_SOC_MDIO_DESC **MdioDesc, + IN OUT UINTN *DescCount + ); + +// // NonDiscoverable devices SoC description // // AHCI diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c index 580c0f4..652677f 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c @@ -63,6 +63,35 @@ ArmadaSoCDescComPhyGet ( EFI_STATUS EFIAPI +ArmadaSoCDescMdioGet ( + IN OUT MV_SOC_MDIO_DESC **MdioDesc, + IN OUT UINTN *DescCount + ) +{ + MV_SOC_MDIO_DESC *Desc; + UINTN CpCount, CpIndex; + + CpCount = FixedPcdGet8 (PcdMaxCpCount); + + Desc = AllocateZeroPool (CpCount * sizeof (MV_SOC_MDIO_DESC)); + if (Desc == NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + for (CpIndex = 0; CpIndex < CpCount; CpIndex++) { + Desc[CpIndex].MdioId = MV_SOC_MDIO_ID (CpIndex); + Desc[CpIndex].MdioBaseAddress = MV_SOC_MDIO_BASE (CpIndex); + } + + *MdioDesc = Desc; + *DescCount = CpCount; + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI ArmadaSoCDescAhciGet ( IN OUT MV_SOC_AHCI_DESC **AhciDesc, IN OUT UINTN *DescCount -- 2.7.4