From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4864:20::244; helo=mail-lj1-x244.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org Received: from mail-lj1-x244.google.com (mail-lj1-x244.google.com [IPv6:2a00:1450:4864:20::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4854A202E5483 for ; Thu, 12 Jul 2018 00:40:51 -0700 (PDT) Received: by mail-lj1-x244.google.com with SMTP id v9-v6so10954840ljk.4 for ; Thu, 12 Jul 2018 00:40:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=khXYrXboyx3QH1WBZ/mJZbVwxRFH3071/vUReyzgwNg=; b=IyWgTgLVAZnLjm/k98snth4f7E1cI4nvHO9ISQG10elxjWfw3PWlKa1TIltBKgk281 N3IIHQUeZa+6/aBN8Nr5NPyUCoK0g+mC5OOe/PeqbJ0UYHhrXgbWFhcs/GaV73BMxMEb vkFaOActBzwNwQSPvL0NvqjXZO0v1A2sK1ORVGwyDIOQlPY8kX7ZSxOYo1ZEodrEaE7c eVaRlM8167icLXUWHTIQ6r3IGFyHvpnuVD+pipkqJ3LzhVRgLNxaCTtvkXSFVnHUsjbY 9WNVnQCjRM1wK6QrfDrApLdeHJmqXgn/giRywKEwgFWTuiiYdPHMVTI5L/WsvgA/E89Q sRFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=khXYrXboyx3QH1WBZ/mJZbVwxRFH3071/vUReyzgwNg=; b=fVACNb6X2bP3UlqR6Aakc7VgrMc1vO0CX4S4/wvfNmul4qERRSPGFqXevqbRHw2Pza 7IuRhAxn6zvTSr8CjwRwQf0ZzI2FT+HJ3hl4ZsmCn4KgtP1m55Fj3Bd5Xrxu3ucyZmmn EtE9I26G0tmhnOfAasQmTqBiVWj+pa8cMvALvgxaDMzE003OhMceylt3+yPePZRTPWPl BvPjtP2a0tI3nz5PgeVxxaBlHVZZh/jCajTfD6Ffa4yr8IrnvQ4vX2C2F3Gn568ZJncm hXRvf45Nowdq0KycSPcY8CRj3ODYULhF79aAVL8vwJo/Ny5EV0cr0CXwPGu1Cw3H9n5E EqRg== X-Gm-Message-State: APt69E3xdnvsmdoj9GynmjkfBFwZtySfOsJk8K8bdy74rPpwYTkhg7eM OdtKH2UmTo0cremebHL6ryjYwJIDkA0= X-Google-Smtp-Source: AAOMgpf/uyb4wN2jYdh0RfghJq6oO2jIZpO6fn0kqQhPQzg2LFgkfsXzoPWh7eJt3tFO/Yjkrnfm5g== X-Received: by 2002:a2e:9dc7:: with SMTP id x7-v6mr8163507ljj.142.1531381249225; Thu, 12 Jul 2018 00:40:49 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id p20-v6sm3367058lji.37.2018.07.12.00.40.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 12 Jul 2018 00:40:48 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, hannah@marvell.com, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com Date: Thu, 12 Jul 2018 09:39:56 +0200 Message-Id: <1531381201-5022-2-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1531381201-5022-1-git-send-email-mw@semihalf.com> References: <1531381201-5022-1-git-send-email-mw@semihalf.com> Subject: [platforms: PATCH 1/6] Marvell/Armada70x0Db: Set correct CP110 count X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jul 2018 07:40:51 -0000 As a preparation for adding the ICU (Interrupt Consolidation Unit) library implementation a correct CP110 count is required. Do it for Armada70x0Db and fix depending XHCI/AHCI PCD's accordingly. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc index 5ccee1b..2240a57 100644 --- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc +++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc @@ -53,6 +53,9 @@ # ################################################################################ [PcdsFixedAtBuild.common] + #CP110 count + gMarvellTokenSpaceGuid.PcdMaxCpCount|1 + #MPP gMarvellTokenSpaceGuid.PcdMppChipCount|2 @@ -129,8 +132,8 @@ gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1 } #PciEmulation - gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x0 } + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1 } gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } #RTC -- 2.7.4