From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4864:20::242; helo=mail-lj1-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org Received: from mail-lj1-x242.google.com (mail-lj1-x242.google.com [IPv6:2a00:1450:4864:20::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2EC2C209831EA for ; Fri, 13 Jul 2018 01:12:28 -0700 (PDT) Received: by mail-lj1-x242.google.com with SMTP id 203-v6so12887803ljj.13 for ; Fri, 13 Jul 2018 01:12:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1WMFvMKgds8sS2w71W2m+LjNzNUfOiKqEulmDq+dk9w=; b=QLL+6FcM5z600K4el+cZHT0ooUw4hVnnNEUImFEKm+XkIx4w3/LrjVWUa9DggRjhHe 8jrShRKz6c7lxzLTcebjQ1Tdm0stKbU6jnIk/arZp5kFiB2iTAvUCZUjf4EB3ck5uzn6 sVg8xzsXzKo02bmGZ5ufyxZbxJpAvLY3l9DFObXhxoZzLjVGWCy+YJt9S2FpYja7nuTJ WnAOfQErI18vHboq/C1qPxVbg5lfOXPJKnUIRutMxUSiENFQ04iwIdf52y2FtOLmzMEe jHsj72CqUzCM5kxl8ltQKsvQ8h3Yf6/6LGBU8EbIT5YvVpGJ7RmFOmPgYBu5qOshAnYQ SNaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1WMFvMKgds8sS2w71W2m+LjNzNUfOiKqEulmDq+dk9w=; b=GP85i56e90JPBVSej1SsILPV+nGlkMbr7xtOj+fM6Byn3IJV7UanOLX+qVwsRC0Qfa kIy1odmdrKeolgqKBN2iRWv4dYs4aVtfWR2J7ppMR5j+6vTwjAiQSPpCDdH1855jXLE0 9kvmE/z0acoX88vNUBkGJjsrGRceFahc979H9AmElUk8/YQpBk5vbkDp61c2S5j15+pK wmiOtsaCgzmuHW7asISIJnhe/p6tcZmmmzRavaBm/s3YByyrNzMhNkZMa2vjO0DZHAs1 PIpw4mtLz73YKP+qz6KXWdZV4lPPaPTpQwCnq9mHMlaY04kvR0JsnZ5PHRQQiL+mq5dN 2KTg== X-Gm-Message-State: AOUpUlEZR7vv6bQH+gt7mqnRNGfGMWA1/z1yRtEpLhdgmxqy/c5mXg4b pH/szmmz2r8mD3cY+hIElWOFp1Pmw90= X-Google-Smtp-Source: AAOMgpfyxCIUDFzVBwvSRAgF6GpGTvkFHOEgc1nwcWRJrwTw8u764qk1f4P2ZpPrIUGeiJUuzhWrrw== X-Received: by 2002:a2e:9d0e:: with SMTP id t14-v6mr2526205lji.112.1531469545459; Fri, 13 Jul 2018 01:12:25 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id m29-v6sm6485484lfj.45.2018.07.13.01.12.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 13 Jul 2018 01:12:24 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, hannah@marvell.com, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com Date: Fri, 13 Jul 2018 10:12:08 +0200 Message-Id: <1531469533-31787-2-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1531469533-31787-1-git-send-email-mw@semihalf.com> References: <1531469533-31787-1-git-send-email-mw@semihalf.com> Subject: [platforms: PATCH v2 1/6] Marvell/Armada70x0Db: Set correct CP110 count X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Jul 2018 08:12:28 -0000 As a preparation for adding the ICU (Interrupt Consolidation Unit) library implementation a correct CP110 count is required. Do it for Armada70x0Db and fix depending XHCI/AHCI PCD's accordingly. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc index 5ccee1b..2240a57 100644 --- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc +++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc @@ -53,6 +53,9 @@ # ################################################################################ [PcdsFixedAtBuild.common] + #CP110 count + gMarvellTokenSpaceGuid.PcdMaxCpCount|1 + #MPP gMarvellTokenSpaceGuid.PcdMppChipCount|2 @@ -129,8 +132,8 @@ gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1 } #PciEmulation - gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x0 } + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1 } gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } #RTC -- 2.7.4