From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4864:20::22a; helo=mail-lj1-x22a.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org Received: from mail-lj1-x22a.google.com (mail-lj1-x22a.google.com [IPv6:2a00:1450:4864:20::22a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 02DCE209884BE for ; Fri, 13 Jul 2018 07:11:23 -0700 (PDT) Received: by mail-lj1-x22a.google.com with SMTP id l15-v6so4506478lji.6 for ; Fri, 13 Jul 2018 07:11:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=e6dfWrqTQvs+MIgAX6TmhVMV+1OfJjVukDdtQLqWsQg=; b=F/P3uHG7c7EF6j/PS07f/PJ4Fd7V0DCMyu3w7PalAX27hFbrq4sOSAmGtjAiKf4zeg FCloQ+4nfEuhX1LAHYj6xmzLRzywbCMJHWy9lBtKpbDTZym5hEdd2My/RFEeHusW3XjZ YA7SmuyNAHtyUUpYv/3Rdu8YNDAi2BuKpstKGM/J1YqkeTuYvYnRW4uGVe6qmUnKxeKr 3kRBlzRWOpY6UQrYjK3OoLB7ygyehUqIfoWOSPim/8fThMQYwoWV/Edlr97+gnVHasNj 6AQCdR/jjJ4+Eeab9j798MNw7dPDlkEQQ4YgcjGulSiaZDJQaKPcthbv+jNlWUfzs4ce I8cA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=e6dfWrqTQvs+MIgAX6TmhVMV+1OfJjVukDdtQLqWsQg=; b=lYVuHrmMf7l5PyCFeXoVPPCqM1E4oVKojH0Egj7ocDjj9WY5eFpLqjof2lCh3axvI1 ECBd+mAyu8n0zeUunimoh6KoWZ8QslbU4L30gEu2w/n/LWDJpjP2nrH6m2dq4o0u5WvF ok+SHOY2lPicrDaUP8QePd95txFSUUOVdII1djms1QBc41PYydARnXOTsoneI2y+e3lf d5qkztYeKUJ71dbFBLKJMD25YtCr8i/AhVL3a1CK4f0KVBm96xwrkgIOiS50/FBEjxA9 5hNjD0Np0R26BGwXs2V+vITwEgP0amDw1Dnw8nd/9lpdqCsBTJQl4LjoiyewtxXVHwpF iliQ== X-Gm-Message-State: AOUpUlE0yXVtX8l6CbOFKcMn5+cBkCmYmRs/TIIbYzb0u5IMcQtTVsQP UHs9RoQ4buywW46zl/ERje6lkhmkHuE= X-Google-Smtp-Source: AAOMgpeLxWg+s/MaNIAMVP1RyMPVUG9KBr5Czib4eJXfg2GQ59FxBqxLcG60M3AdDVWgK0qqEt78OA== X-Received: by 2002:a2e:8514:: with SMTP id j20-v6mr3772144lji.10.1531491081810; Fri, 13 Jul 2018 07:11:21 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id h7-v6sm451750ljk.27.2018.07.13.07.11.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 13 Jul 2018 07:11:21 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com Date: Fri, 13 Jul 2018 16:09:42 +0200 Message-Id: <1531490984-32491-5-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1531490984-32491-1-git-send-email-mw@semihalf.com> References: <1531490984-32491-1-git-send-email-mw@semihalf.com> Subject: [platforms: PATCH 4/6] Marvell/Library: ComPhyLib: Configure USB in ARM-TF X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Jul 2018 14:11:24 -0000 From: Grzegorz Jaszczyk Replace the comphy initialization for USB with appropriate SMC call, so the firmware will execute required serdes configuration. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c | 167 +------------------- 1 file changed, 4 insertions(+), 163 deletions(-) diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c index c46cad1..35ac459 100755 --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c @@ -100,168 +100,6 @@ COMPHY_MUX_DATA Cp110ComPhyPipeMuxData[] = { STATIC VOID -ComPhyUsb3RFUConfiguration ( - IN EFI_PHYSICAL_ADDRESS ComPhyAddr -) -{ - UINT32 Mask, Data; - - /* RFU configurations - hard reset ComPhy */ - Mask = COMMON_PHY_CFG1_PWR_UP_MASK; - Data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; - Mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; - Data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; - Mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; - Data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; - Mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; - Data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; - Mask |= COMMON_PHY_PHY_MODE_MASK; - Data |= 0x1 << COMMON_PHY_PHY_MODE_OFFSET; - RegSet (ComPhyAddr + COMMON_PHY_CFG1_REG, Data, Mask); - - /* Release from hard reset */ - Mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK; - Data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; - Mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; - Data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; - RegSet (ComPhyAddr + COMMON_PHY_CFG1_REG, Data, Mask); - - /* Wait 1ms - until band gap and ref clock ready */ - MicroSecondDelay (1000); - MemoryFence (); -} - -STATIC -VOID -ComPhyUsb3PhyConfiguration ( - IN EFI_PHYSICAL_ADDRESS HpipeAddr -) -{ - UINT32 Mask, Data; - - /* Set PIPE soft reset */ - Mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK; - Data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET; - - /* Set PHY Datapath width mode for V0 */ - Mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK; - Data |= 0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET; - - /* Set Data bus width USB mode for V0 */ - Mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK; - Data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET; - - /* Set CORE_CLK output frequency for 250Mhz */ - Mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK; - Data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET; - RegSet (HpipeAddr + HPIPE_RST_CLK_CTRL_REG, Data, Mask); - - /* Set PLL ready delay for 0x2 */ - RegSet (HpipeAddr + HPIPE_CLK_SRC_LO_REG, - 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET, - HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK); - - /* Set reference clock to come from group 1 - 25Mhz */ - RegSet (HpipeAddr + HPIPE_MISC_REG, 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET, - HPIPE_MISC_REFCLK_SEL_MASK); - - /* Set reference frequcency select - 0x2 */ - Mask = HPIPE_PWR_PLL_REF_FREQ_MASK; - Data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; - - /* Set PHY mode to USB - 0x5 */ - Mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; - Data |= 0x5 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; - RegSet (HpipeAddr + HPIPE_PWR_PLL_REG, Data, Mask); - - /* Set the amount of time spent in the LoZ state - set for 0x7 */ - RegSet (HpipeAddr + HPIPE_GLOBAL_PM_CTRL, - 0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET, - HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK); - - /* Set max PHY generation setting - 5Gbps */ - RegSet (HpipeAddr + HPIPE_INTERFACE_REG, - 0x1 << HPIPE_INTERFACE_GEN_MAX_OFFSET, HPIPE_INTERFACE_GEN_MAX_MASK); - - /* Set select Data width 20Bit (SEL_BITS[2:0]) */ - RegSet (HpipeAddr + HPIPE_LOOPBACK_REG, - 0x1 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK); -} - -STATIC -VOID -ComPhyUsb3SetAnalogParameters ( - IN EFI_PHYSICAL_ADDRESS HpipeAddr -) -{ - UINT32 Data, Mask; - - /* Set Pin DFE_PAT_DIS -> Bit[1]: PIN_DFE_PAT_DIS = 0x0 */ - Mask = HPIPE_LANE_CFG4_DFE_CTRL_MASK; - Data = 0x1 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET; - - /* Set Override PHY DFE control pins for 0x1 */ - Mask |= HPIPE_LANE_CFG4_DFE_OVER_MASK; - Data |= 0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET; - - /* Set Spread Spectrum Clock Enable fot 0x1 */ - Mask |= HPIPE_LANE_CFG4_SSC_CTRL_MASK; - Data |= 0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET; - RegSet (HpipeAddr + HPIPE_LANE_CFG4_REG, Data, Mask); -} - -STATIC -UINTN -ComphyUsb3PowerUp ( - UINT32 Lane, - EFI_PHYSICAL_ADDRESS HpipeBase, - EFI_PHYSICAL_ADDRESS ComPhyBase - ) -{ - EFI_STATUS Status = EFI_SUCCESS; - UINT32 Data; - EFI_PHYSICAL_ADDRESS HpipeAddr = HPIPE_ADDR(HpipeBase, Lane); - EFI_PHYSICAL_ADDRESS ComPhyAddr = COMPHY_ADDR(ComPhyBase, Lane); - - DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset ComPhy\n")); - - ComPhyUsb3RFUConfiguration (ComPhyAddr); - - /* Start ComPhy Configuration */ - DEBUG((DEBUG_INFO, "stage: Comphy configuration\n")); - - ComPhyUsb3PhyConfiguration (HpipeAddr); - - /* Start analog paramters from ETP(HW) */ - DEBUG((DEBUG_INFO, "ComPhy: stage: Analog paramters from ETP(HW)\n")); - - ComPhyUsb3SetAnalogParameters (HpipeAddr); - - DEBUG((DEBUG_INFO, "ComPhy: stage: Comphy power up\n")); - - /* Release from PIPE soft reset */ - RegSet (HpipeAddr + HPIPE_RST_CLK_CTRL_REG, - 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET, - HPIPE_RST_CLK_CTRL_PIPE_RST_MASK); - - /* Wait 15ms - for ComPhy calibration done */ - MicroSecondDelay (15000); - MemoryFence (); - - DEBUG((DEBUG_INFO, "ComPhy: stage: Check PLL\n")); - - /* Read Lane status */ - Data = MmioRead32 (HpipeAddr + HPIPE_LANE_STATUS0_REG); - if ((Data & HPIPE_LANE_STATUS0_PCLK_EN_MASK) == 0) { - DEBUG((DEBUG_ERROR, "ComPhy: HPIPE_LANE_STATUS0_PCLK_EN_MASK is 0\n")); - Status = EFI_D_ERROR; - } - - return Status; -} - -STATIC -VOID ComPhySataMacPowerDown ( IN EFI_PHYSICAL_ADDRESS SataBase ) @@ -528,7 +366,10 @@ ComPhyCp110Init ( break; case COMPHY_TYPE_USB3_HOST0: case COMPHY_TYPE_USB3_HOST1: - Status = ComphyUsb3PowerUp(Lane, HpipeBaseAddr, ComPhyBaseAddr); + Status = ComPhySmc (MV_SIP_COMPHY_POWER_ON, + PtrChipCfg->ComPhyBaseAddr, + Lane, + COMPHY_FW_MODE_FORMAT (COMPHY_USB3H_MODE)); break; case COMPHY_TYPE_SGMII0: case COMPHY_TYPE_SGMII1: -- 2.7.4