[platforms: PATCH 6/6] Marvell/Library: ComPhyLib: Remove both PHY and PIPE selector config

[Marcin Wojtas <mw@semihalf.com>]

From: Grzegorz Jaszczyk <jaz@semihalf.com>

Now the ComPhy configuration is handled in ARM-TF, therefore there is no
need to configure PHY or PIPE selector in UEFI. Remove unused code.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
 Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf |   1 -
 Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h   |   7 --
 Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c |  97 --------------
 Silicon/Marvell/Library/ComPhyLib/ComPhyMux.c   | 132 --------------------
 4 files changed, 237 deletions(-)
 delete mode 100644 Silicon/Marvell/Library/ComPhyLib/ComPhyMux.c

diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf
index 7a72203..36f498b 100644
--- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf
+++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf
@@ -58,7 +58,6 @@
 [Sources.common]
   ComPhyLib.c
   ComPhyCp110.c
-  ComPhyMux.c
 
 [Protocols]
   gMarvellBoardDescProtocolGuid  ## CONSUMES
diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
index 4bb9c95..76d033d 100644
--- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
+++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
@@ -188,13 +188,6 @@ struct _CHIP_COMPHY_CONFIG {
 };
 
 VOID
-ComPhyMuxInit (
-  IN CHIP_COMPHY_CONFIG *PtrChipCfg,
-  IN COMPHY_MAP *ComPhyMapData,
-  IN EFI_PHYSICAL_ADDRESS SelectorBase
-  );
-
-VOID
 ComPhyCp110Init (
   IN CHIP_COMPHY_CONFIG * First
   );
diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
index 35ac459..2abb006 100755
--- a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
+++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
@@ -46,58 +46,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #define HPIPE_ADDR(base, Lane)      (SD_ADDR(base, Lane) + HPIPE_ADDR_OFFSET)
 #define COMPHY_ADDR(base, Lane)     (base + COMPHY_ADDR_LANE_WIDTH * Lane)
 
-/*
- * For CP-110 we have 2 Selector registers "PHY Selectors"
- * and " PIPE Selectors".
- * PIPE selector include USB and PCIe options.
- * PHY selector include the Ethernet and SATA options, every Ethernet option
- * has different options, for example: serdes Lane2 have option Eth_port_0
- * that include (SGMII0, RXAUI0, SFI)
- */
-COMPHY_MUX_DATA Cp110ComPhyMuxData[] = {
-  /* Lane 0 */
-  {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII1, 0x1},
-       {COMPHY_TYPE_SATA1, 0x4}, {COMPHY_TYPE_SATA3, 0x4}}},
-  /* Lane 1 */
-  {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1},
-       {COMPHY_TYPE_SATA0, 0x4}, {COMPHY_TYPE_SATA2, 0x4}}},
-  /* Lane 2 */
-  {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x1},
-       {COMPHY_TYPE_RXAUI0, 0x1}, {COMPHY_TYPE_SFI, 0x1},
-       {COMPHY_TYPE_SATA0, 0x4}, {COMPHY_TYPE_SATA2, 0x4}}},
-  /* Lane 3 */
-  {8, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_RXAUI1, 0x1},
-       {COMPHY_TYPE_SGMII1, 0x2}, {COMPHY_TYPE_SATA1, 0x4},
-       {COMPHY_TYPE_SATA3, 0x4}}},
-  /* Lane 4 */
-  {7, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x2},
-       {COMPHY_TYPE_RXAUI0, 0x2}, {COMPHY_TYPE_SFI, 0x2},
-       {COMPHY_TYPE_SGMII1, 0x1}}},
-  /* Lane 5 */
-  {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1},
-       {COMPHY_TYPE_RXAUI1, 0x2}, {COMPHY_TYPE_SATA1, 0x4},
-       {COMPHY_TYPE_SATA3, 0x4}}},
-};
-
-COMPHY_MUX_DATA Cp110ComPhyPipeMuxData[] = {
-  /* Lane 0 */
-  {2, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_PCIE0, 0x4}}},
-  /* Lane 1 */
-  {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_USB3_HOST0, 0x1},
-       {COMPHY_TYPE_USB3_DEVICE, 0x2}, {COMPHY_TYPE_PCIE0, 0x4}}},
-  /* Lane 2 */
-  {3, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_USB3_HOST0, 0x1},
-       {COMPHY_TYPE_PCIE0, 0x4}}},
-  /* Lane 3 */
-  {3, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_USB3_HOST1, 0x1},
-       {COMPHY_TYPE_PCIE0, 0x4}}},
-  /* Lane 4 */
-  {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_USB3_HOST1, 0x1},
-       {COMPHY_TYPE_USB3_DEVICE, 0x2}, {COMPHY_TYPE_PCIE1, 0x4}}},
-  /* Lane 5 */
-  {2, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_PCIE2, 0x4}}},
-};
-
 STATIC
 VOID
 ComPhySataMacPowerDown (
@@ -240,48 +188,6 @@ ComPhySataPowerUp (
   return Status;
 }
 
-STATIC
-VOID
-ComPhyMuxCp110 (
-  IN CHIP_COMPHY_CONFIG *PtrChipCfg,
-  IN COMPHY_MAP *SerdesMap
-  )
-{
-  EFI_PHYSICAL_ADDRESS ComPhyBaseAddr;
-  COMPHY_MAP ComPhyMapPipeData[MAX_LANE_OPTIONS];
-  COMPHY_MAP ComPhyMapPhyData[MAX_LANE_OPTIONS];
-  UINT32 Lane, ComPhyMaxCount;
-
-  ComPhyMaxCount = PtrChipCfg->LanesCount;
-  ComPhyBaseAddr = PtrChipCfg->ComPhyBaseAddr;
-
-  /*
-   * Copy the SerDes map configuration for PIPE map and PHY map.
-   * The ComPhyMuxInit modifies the Type of the Lane if the Type is not valid.
-   * Because we have 2 selectors, run the ComPhyMuxInit twice and after
-   * that, update the original SerdesMap.
-   */
-  for (Lane = 0; Lane < ComPhyMaxCount; Lane++) {
-    ComPhyMapPipeData[Lane].Type = SerdesMap[Lane].Type;
-    ComPhyMapPipeData[Lane].Speed = SerdesMap[Lane].Speed;
-    ComPhyMapPhyData[Lane].Type = SerdesMap[Lane].Type;
-    ComPhyMapPhyData[Lane].Speed = SerdesMap[Lane].Speed;
-  }
-  PtrChipCfg->MuxData = Cp110ComPhyMuxData;
-  ComPhyMuxInit(PtrChipCfg, ComPhyMapPhyData, ComPhyBaseAddr +
-    COMMON_SELECTOR_PHY_OFFSET);
-
-  PtrChipCfg->MuxData = Cp110ComPhyPipeMuxData;
-  ComPhyMuxInit(PtrChipCfg, ComPhyMapPipeData, ComPhyBaseAddr +
-    COMMON_SELECTOR_PIPE_OFFSET);
-
-  /* Fix the Type after check the PHY and PIPE configuration */
-  for (Lane = 0; Lane < ComPhyMaxCount; Lane++)
-    if ((ComPhyMapPipeData[Lane].Type == COMPHY_TYPE_UNCONNECTED) &&
-        (ComPhyMapPhyData[Lane].Type == COMPHY_TYPE_UNCONNECTED))
-      SerdesMap[Lane].Type = COMPHY_TYPE_UNCONNECTED;
-}
-
 VOID
 ComPhyCp110Init (
   IN CHIP_COMPHY_CONFIG *PtrChipCfg
@@ -302,9 +208,6 @@ ComPhyCp110Init (
   SerdesMap = PtrChipCfg->MapData;
   ChipId = PtrChipCfg->ChipId;
 
-  /* Config Comphy mux configuration */
-  ComPhyMuxCp110(PtrChipCfg, SerdesMap);
-
   /* Check if the first 4 Lanes configured as By-4 */
   for (Lane = 0, PtrComPhyMap = SerdesMap; Lane < 4; Lane++, PtrComPhyMap++) {
     if (PtrComPhyMap->Type != COMPHY_TYPE_PCIE0) {
diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyMux.c b/Silicon/Marvell/Library/ComPhyLib/ComPhyMux.c
deleted file mode 100644
index 6589fec..0000000
--- a/Silicon/Marvell/Library/ComPhyLib/ComPhyMux.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/********************************************************************************
-Copyright (C) 2016 Marvell International Ltd.
-
-Marvell BSD License Option
-
-If you received this File from Marvell, you may opt to use, redistribute and/or
-modify this File under the following licensing terms.
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice,
-  this list of conditions and the following disclaimer.
-
-* Redistributions in binary form must reproduce the above copyright
-  notice, this list of conditions and the following disclaimer in the
-  documentation and/or other materials provided with the distribution.
-
-* Neither the name of Marvell nor the names of its contributors may be
-  used to endorse or promote products derived from this software without
-  specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-#include "ComPhyLib.h"
-
-STATIC
-VOID
-ComPhyMuxCheckConfig (
-  IN COMPHY_MUX_DATA *MuxData,
-  IN COMPHY_MAP *ComPhyMapData,
-  IN UINTN ComPhyMaxLanes
-  )
-{
-  COMPHY_MUX_OPTIONS *PtrMuxOpt;
-  UINTN Lane, Opt, Valid;
-
-  for (Lane = 0; Lane < ComPhyMaxLanes; Lane++, ComPhyMapData++, MuxData++) {
-    PtrMuxOpt = MuxData->MuxValues;
-    for (Opt = 0, Valid = 0; Opt < MuxData->MaxLaneValues; Opt++, PtrMuxOpt++) {
-      if (PtrMuxOpt->Type == ComPhyMapData->Type) {
-        Valid = 1;
-        break;
-      }
-    }
-    if (Valid == 0) {
-      DEBUG((DEBUG_INFO, "Lane number %d, had invalid Type %d\n", Lane,
-        ComPhyMapData->Type));
-      DEBUG((DEBUG_INFO, "Set Lane %d as Type %d\n", Lane,
-        COMPHY_TYPE_UNCONNECTED));
-      ComPhyMapData->Type = COMPHY_TYPE_UNCONNECTED;
-    } else {
-      DEBUG((DEBUG_INFO, "Lane number %d, has Type %d\n", Lane,
-        ComPhyMapData->Type));
-    }
-  }
-}
-
-STATIC
-UINT32
-ComPhyMuxGetMuxValue (
-  IN COMPHY_MUX_DATA *MuxData,
-  IN UINT32 Type,
-  IN UINTN Lane
-  )
-{
-  COMPHY_MUX_OPTIONS *PtrMuxOpt;
-  UINTN Opt;
-  UINT32 Value = 0;
-
-  PtrMuxOpt = MuxData->MuxValues;
-  for (Opt = 0 ; Opt < MuxData->MaxLaneValues; Opt++, PtrMuxOpt++)
-    if (PtrMuxOpt->Type == Type) {
-      Value = PtrMuxOpt->MuxValue;
-      break;
-    }
-
-  return Value;
-}
-
-STATIC
-VOID
-ComPhyMuxRegWrite (
-  IN COMPHY_MUX_DATA *MuxData,
-  IN COMPHY_MAP *ComPhyMapData,
-  IN UINTN ComPhyMaxLanes,
-  IN EFI_PHYSICAL_ADDRESS SelectorBase,
-  IN UINT32 BitCount
-  )
-{
-  UINT32 Lane, Value, Offset, Mask;
-
-  for (Lane = 0; Lane < ComPhyMaxLanes; Lane++, ComPhyMapData++, MuxData++) {
-    Offset = Lane * BitCount;
-    Mask = (((1 << BitCount) - 1) << Offset);
-    Value = (ComPhyMuxGetMuxValue (MuxData, ComPhyMapData->Type, Lane) <<
-      Offset);
-    RegSet (SelectorBase, Value, Mask);
-  }
-}
-
-VOID
-ComPhyMuxInit (
-  IN CHIP_COMPHY_CONFIG *PtrChipCfg,
-  IN COMPHY_MAP *ComPhyMapData,
-  IN EFI_PHYSICAL_ADDRESS SelectorBase
-  )
-{
-  COMPHY_MUX_DATA *MuxData;
-  UINT32 MuxBitCount;
-  UINT32 ComPhyMaxLanes;
-
-  ComPhyMaxLanes = PtrChipCfg->LanesCount;
-  MuxData = PtrChipCfg->MuxData;
-  MuxBitCount = PtrChipCfg->MuxBitCount;
-
-  /* Check if the configuration is valid */
-  ComPhyMuxCheckConfig (MuxData, ComPhyMapData, ComPhyMaxLanes);
-  /* Init COMPHY selectors */
-  ComPhyMuxRegWrite (MuxData, ComPhyMapData, ComPhyMaxLanes, SelectorBase,
-    MuxBitCount);
-}
-- 
2.7.4