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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id o74-v6sm81596lfg.31.2018.07.26.00.21.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 26 Jul 2018 00:21:55 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com Date: Thu, 26 Jul 2018 09:21:32 +0200 Message-Id: <1532589696-16902-3-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1532589696-16902-1-git-send-email-mw@semihalf.com> References: <1532589696-16902-1-git-send-email-mw@semihalf.com> Subject: [platforms: PATCH v2 2/6] Marvell/Library: ComPhyLib: Configure PCIE in ARM-TF X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Jul 2018 07:21:59 -0000 From: Grzegorz Jaszczyk Replace the ComPhy initialization for PCIE with appropriate SMC call, so the ARM-TF will execute required serdes configuration. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.h | 22 - Silicon/Marvell/Include/Library/SampleAtResetLib.h | 7 - Silicon/Marvell/Library/ComPhyLib/ComPhySipSvc.h | 2 + Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.c | 19 - Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c | 491 +------------------- 5 files changed, 8 insertions(+), 533 deletions(-) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.h index 323399f..e47396d 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.h +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.h @@ -44,18 +44,6 @@ SAR - Sample At Reset #define CP110_SAR_BASE(_CpIndex) (0xf2000000 + (0x2000000 * (_CpIndex)) + 0x400200) -#define MAX_CP_COUNT 2 -#define MAX_PCIE_CLK_TYPE_COUNT 2 - -#define CP0_PCIE0_CLK_OFFSET 2 -#define CP0_PCIE1_CLK_OFFSET 3 -#define CP1_PCIE0_CLK_OFFSET 0 -#define CP1_PCIE1_CLK_OFFSET 1 -#define CP0_PCIE0_CLK_MASK (1 << CP0_PCIE0_CLK_OFFSET) -#define CP0_PCIE1_CLK_MASK (1 << CP0_PCIE1_CLK_OFFSET) -#define CP1_PCIE0_CLK_MASK (1 << CP1_PCIE0_CLK_OFFSET) -#define CP1_PCIE1_CLK_MASK (1 << CP1_PCIE1_CLK_OFFSET) - typedef enum { CPU_2000_DDR_1200_RCLK_1200 = 0x0, CPU_2000_DDR_1050_RCLK_1050 = 0x1, @@ -97,13 +85,3 @@ STATIC CONST PLL_FREQUENCY_DESCRIPTION PllFrequencyTable[SAR_MAX_OPTIONS] = { {800 , 800 , 800 , CPU_800_DDR_800_RCLK_800}, {1000, 800 , 800 , CPU_1000_DDR_800_RCLK_800} }; - -STATIC CONST UINT32 PcieClockMask[MAX_CP_COUNT][MAX_PCIE_CLK_TYPE_COUNT] = { - {CP0_PCIE0_CLK_MASK, CP0_PCIE1_CLK_MASK}, - {CP1_PCIE0_CLK_MASK, CP1_PCIE1_CLK_MASK} -}; - -STATIC CONST UINT32 PcieClockOffset[MAX_CP_COUNT][MAX_PCIE_CLK_TYPE_COUNT] = { - {CP0_PCIE0_CLK_OFFSET, CP0_PCIE1_CLK_OFFSET}, - {CP1_PCIE0_CLK_OFFSET, CP1_PCIE1_CLK_OFFSET} -}; diff --git a/Silicon/Marvell/Include/Library/SampleAtResetLib.h b/Silicon/Marvell/Include/Library/SampleAtResetLib.h index 1be3a6a..1e7b27c 100644 --- a/Silicon/Marvell/Include/Library/SampleAtResetLib.h +++ b/Silicon/Marvell/Include/Library/SampleAtResetLib.h @@ -47,11 +47,4 @@ SampleAtResetGetDramFrequency ( VOID ); -UINT32 -EFIAPI -SampleAtResetGetPcieClockDirection ( - IN UINT32 CpIndex, - IN UINT32 PcieIndex - ); - #endif /* __SAMPLE_AT_RESET_LIB_H__ */ diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhySipSvc.h b/Silicon/Marvell/Library/ComPhyLib/ComPhySipSvc.h index 67787a6..33ab3a6 100644 --- a/Silicon/Marvell/Library/ComPhyLib/ComPhySipSvc.h +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhySipSvc.h @@ -47,6 +47,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define COMPHY_FW_FORMAT(mode, idx, speeds) \ ((mode << 12) | (idx << 8) | (speeds << 2)) +#define COMPHY_FW_PCIE_FORMAT(pcie_width, mode, speeds) \ + ((pcie_width << 18) | COMPHY_FW_FORMAT (mode, 0, speeds)) /* Comphy speed */ #define COMPHY_SPEED_1_25G 0 diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.c index 3ebff56..5a9a5f9 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.c @@ -90,22 +90,3 @@ SampleAtResetGetDramFrequency ( return PllFrequencies->DdrFrequency; } - -UINT32 -EFIAPI -SampleAtResetGetPcieClockDirection ( - IN UINT32 CpIndex, - IN UINT32 PcieIndex - ) -{ - UINT32 ClockDirection; - - ASSERT (CpIndex < MAX_CP_COUNT); - ASSERT (PcieIndex < MAX_PCIE_CLK_TYPE_COUNT); - - ClockDirection = MmioAnd32 (CP110_SAR_BASE (CpIndex), - PcieClockMask[CpIndex][PcieIndex] >> - PcieClockOffset[CpIndex][PcieIndex]); - - return ClockDirection; -} diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c index 4b8b27a..6cefee9 100755 --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c @@ -46,9 +46,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define HPIPE_ADDR(base, Lane) (SD_ADDR(base, Lane) + HPIPE_ADDR_OFFSET) #define COMPHY_ADDR(base, Lane) (base + COMPHY_ADDR_LANE_WIDTH * Lane) -#define CP110_PCIE_REF_CLK_TYPE0 0 -#define CP110_PCIE_REF_CLK_TYPE12 1 - /* * For CP-110 we have 2 Selector registers "PHY Selectors" * and " PIPE Selectors". @@ -103,487 +100,6 @@ COMPHY_MUX_DATA Cp110ComPhyPipeMuxData[] = { STATIC VOID -ComPhyPcieRFUConfiguration ( - IN UINT32 Lane, - IN UINT32 PcieWidth, - IN EFI_PHYSICAL_ADDRESS ComPhyAddr -) -{ - UINT32 Mask, Data; - - /* Enable PCIe by4 and by2 */ - if (Lane == 0) { - if (PcieWidth == 4) { - RegSet (ComPhyAddr + COMMON_PHY_SD_CTRL1, - COMMON_PHY_SD_CTRL1_PCIE_X4_EN, - COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK); - } else if (PcieWidth == 2) { - RegSet (ComPhyAddr + COMMON_PHY_SD_CTRL1, - COMMON_PHY_SD_CTRL1_PCIE_X2_EN, - COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK); - } - } - - /* RFU configurations - hard reset ComPhy */ - Mask = COMMON_PHY_CFG1_PWR_UP_MASK; - Data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; - Mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; - Data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; - Mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; - Data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; - Mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; - Data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; - Mask |= COMMON_PHY_PHY_MODE_MASK; - Data |= 0x0 << COMMON_PHY_PHY_MODE_OFFSET; - RegSet (ComPhyAddr + COMMON_PHY_CFG1_REG, Data, Mask); - - /* Release from hard reset */ - Mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK; - Data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; - Mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; - Data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; - RegSet (ComPhyAddr + COMMON_PHY_CFG1_REG, Data, Mask); - - /* Wait 1ms - until band gap and ref clock ready */ - MicroSecondDelay (1000); - MemoryFence (); -} - -STATIC -VOID -ComPhyPciePhyConfiguration ( - IN UINT32 Lane, - IN UINT32 PcieWidth, - IN UINT32 PcieClk, - IN EFI_PHYSICAL_ADDRESS ComPhyAddr, - IN EFI_PHYSICAL_ADDRESS HpipeAddr -) -{ - UINT32 Mask, Data; - - /* Set PIPE soft reset */ - Mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK; - Data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET; - - /* Set PHY Datapath width mode for V0 */ - Mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK; - Data |= 0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET; - - /* Set Data bus width USB mode for V0 */ - Mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK; - Data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET; - - /* Set CORE_CLK output frequency for 250Mhz */ - Mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK; - Data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET; - RegSet (HpipeAddr + HPIPE_RST_CLK_CTRL_REG, Data, Mask); - - /* Set PLL ready delay for 0x2 */ - Data = HPIPE_CLK_SRC_LO_PLL_RDY_DL_DEFAULT; - Mask = HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK; - if (PcieWidth != 1) { - Data |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_DEFAULT | - HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_DEFAULT; - Mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK | - HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK; - } - RegSet (HpipeAddr + HPIPE_CLK_SRC_LO_REG, Data, Mask); - - /* Set PIPE mode interface to PCIe3 - 0x1 */ - Data = HPIPE_CLK_SRC_HI_MODE_PIPE_EN; - Mask = HPIPE_CLK_SRC_HI_MODE_PIPE_MASK; - if (PcieWidth != 1) { - Mask |= HPIPE_CLK_SRC_HI_LANE_STRT_MASK | - HPIPE_CLK_SRC_HI_LANE_MASTER_MASK | - HPIPE_CLK_SRC_HI_LANE_BREAK_MASK; - if (Lane == 0) { - Data |= HPIPE_CLK_SRC_HI_LANE_STRT_EN | - HPIPE_CLK_SRC_HI_LANE_MASTER_EN; - } else if (Lane == (PcieWidth - 1)) { - Data |= HPIPE_CLK_SRC_HI_LANE_BREAK_EN; - } - } - RegSet (HpipeAddr + HPIPE_CLK_SRC_HI_REG, Data, Mask); - - /* Config update polarity equalization */ - RegSet (HpipeAddr + HPIPE_LANE_EQ_CFG1_REG, - 0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET, HPIPE_CFG_UPDATE_POLARITY_MASK); - - /* Set PIPE version 4 to mode enable */ - RegSet (HpipeAddr + HPIPE_DFE_CTRL_28_REG, - 0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET, HPIPE_DFE_CTRL_28_PIPE4_MASK); - - /* Set PIN_TXDCLK_2X Clock Frequency Selection for outputs 500MHz clock */ - Mask = HPIPE_MISC_TXDCLK_2X_MASK; - Data = HPIPE_MISC_TXDCLK_2X_500MHZ; - - /* Enable 500MHz Clock */ - Mask |= HPIPE_MISC_CLK500_EN_MASK; - Data |= 0x1 << HPIPE_MISC_CLK500_EN_OFFSET; - - if (PcieClk) { - /* - * Enable PIN clock 100M_125M - * Only if clock is output, configure the clock-source mux - */ - Mask |= HPIPE_MISC_CLK100M_125M_MASK; - Data |= HPIPE_MISC_CLK100M_125M_EN; - /* Set reference clock comes from group 1 */ - Mask |= HPIPE_MISC_REFCLK_SEL_MASK; - Data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET; - } else { - /* Set reference clock comes from group 2 */ - Mask |= HPIPE_MISC_REFCLK_SEL_MASK; - Data |= 0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET; - } - - /* Force ICP */ - Mask |= HPIPE_MISC_ICP_FORCE_MASK; - Data |= 0x1 << HPIPE_MISC_ICP_FORCE_OFFSET; - RegSet (HpipeAddr + HPIPE_MISC_REG, Data, Mask); - - if (PcieClk) { - /* Set reference frequcency select - 0x2 for 25MHz*/ - Mask = HPIPE_PWR_PLL_REF_FREQ_MASK; - Data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; - } else { - /* Set reference frequcency select - 0x0 for 100MHz*/ - Mask = HPIPE_PWR_PLL_REF_FREQ_MASK; - Data = 0x0 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; - } - - /* Set PHY mode to PCIe */ - Mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; - Data |= 0x3 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; - RegSet (HpipeAddr + HPIPE_PWR_PLL_REG, Data, Mask); - - /* Ref clock alignment */ - if (PcieWidth != 1) { - RegSet (HpipeAddr + HPIPE_LANE_ALIGN_REG, - HPIPE_LANE_ALIGN_OFF, - HPIPE_LANE_ALIGN_OFF_MASK); - } - - /* - * Set the amount of time spent in the LoZ state - set - * for 0x7 only if the PCIe clock is output - */ - if (PcieClk) - RegSet (HpipeAddr + HPIPE_GLOBAL_PM_CTRL, - 0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET, - HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK); - - /* Set Maximal PHY Generation Setting (8Gbps) */ - Mask = HPIPE_INTERFACE_GEN_MAX_MASK; - Data = 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET; - /* Bypass frame detection and sync detection for RX DATA */ - Mask |= HPIPE_INTERFACE_DET_BYPASS_MASK; - Data |= 0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET; - /* Set Link Train Mode (Tx training control pins are used) */ - Mask |= HPIPE_INTERFACE_LINK_TRAIN_MASK; - Data |= 0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET; - RegSet (HpipeAddr + HPIPE_INTERFACE_REG, Data, Mask); - - /* Set Idle_sync enable */ - Mask = HPIPE_PCIE_IDLE_SYNC_MASK; - Data = 0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET; - - /* Select bits for PCIE Gen3(32bit) */ - Mask |= HPIPE_PCIE_SEL_BITS_MASK; - Data |= 0x2 << HPIPE_PCIE_SEL_BITS_OFFSET; - RegSet (HpipeAddr + HPIPE_PCIE_REG0, Data, Mask); - - /* Enable Tx_adapt_g1 */ - Mask = HPIPE_TX_TRAIN_CTRL_G1_MASK; - Data = 0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET; - - /* Enable Tx_adapt_gn1 */ - Mask |= HPIPE_TX_TRAIN_CTRL_GN1_MASK; - Data |= 0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET; - - /* Disable Tx_adapt_g0 */ - Mask |= HPIPE_TX_TRAIN_CTRL_G0_MASK; - Data |= 0x0 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET; - RegSet (HpipeAddr + HPIPE_TX_TRAIN_CTRL_REG, Data, Mask); - - /* Set reg_tx_train_chk_init */ - Mask = HPIPE_TX_TRAIN_CHK_INIT_MASK; - Data = 0x0 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET; - - /* Enable TX_COE_FM_PIN_PCIE3_EN */ - Mask |= HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK; - Data |= 0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET; - RegSet (HpipeAddr + HPIPE_TX_TRAIN_REG, Data, Mask); -} - -STATIC -VOID -ComPhyPcieSetAnalogParameters ( - IN EFI_PHYSICAL_ADDRESS HpipeAddr -) -{ - UINT32 Data, Mask; - - /* Set preset sweep configurations */ - Mask = HPIPE_TX_TX_STATUS_CHECK_MODE_MASK | - HPIPE_TX_NUM_OF_PRESET_MASK | - HPIPE_TX_SWEEP_PRESET_EN_MASK; - Data = (0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET) | - (0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET) | - (0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET); - MmioAndThenOr32 (HpipeAddr + HPIPE_TX_TRAIN_CTRL_11_REG, ~Mask, Data); - - /* Tx train start configuration */ - Mask = HPIPE_TX_TRAIN_START_SQ_EN_MASK | - HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK | - HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK | - HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK; - Data = (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET) | - (0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET); - MmioAndThenOr32 (HpipeAddr + HPIPE_TX_TRAIN_CTRL_5_REG, ~Mask, Data); - - /* Enable Tx train P2P */ - MmioOr32 (HpipeAddr + HPIPE_TX_TRAIN_CTRL_0_REG, HPIPE_TX_TRAIN_P2P_HOLD_MASK); - - /* Configure Tx train timeout */ - MmioAndThenOr32 ( - HpipeAddr + HPIPE_TX_TRAIN_CTRL_4_REG, - ~HPIPE_TRX_TRAIN_TIMER_MASK, - 0x17 << HPIPE_TRX_TRAIN_TIMER_OFFSET - ); - - /* Disable G0/G1/GN1 adaptation */ - MmioAnd32 ( - HpipeAddr + HPIPE_TX_TRAIN_CTRL_REG, - ~(HPIPE_TX_TRAIN_CTRL_G1_MASK | HPIPE_TX_TRAIN_CTRL_GN1_MASK | HPIPE_TX_TRAIN_CTRL_G0_OFFSET) - ); - - /* Disable DTL frequency loop */ - MmioAnd32 (HpipeAddr + HPIPE_PWR_CTR_DTL_REG, ~HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK); - - /* Configure Generation 3 DFE */ - MmioAndThenOr32 ( - HpipeAddr + HPIPE_G3_SET4_REG, - ~HPIPE_GX_SET4_DFE_RES_MASK, - 0x3 << HPIPE_GX_SET4_DFE_RES_OFFSET - ); - - /* Use TX/RX training result for DFE */ - MmioAnd32 (HpipeAddr + HPIPE_DFE_REG0, ~HPIPE_DFE_RES_FORCE_MASK); - - /* Configure initial and final coefficient value for receiver */ - MmioAndThenOr32 (HpipeAddr + HPIPE_G3_SET1_REG, ~Mask, Data); - Mask = HPIPE_GX_SET1_RX_SELMUPI_MASK | - HPIPE_GX_SET1_RX_SELMUPP_MASK | - HPIPE_GX_SET1_SAMPLER_INPAIRX2_EN_MASK; - Data = 0x1 | (0x1 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET); - MmioAndThenOr32 (HpipeAddr + HPIPE_G3_SET1_REG, ~Mask, Data); - - /* Trigger sampler 5us enable pulse */ - MmioAndThenOr32 ( - HpipeAddr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, - ~HPIPE_SAMPLER_MASK, - 0x1 << HPIPE_SAMPLER_OFFSET - ); - MicroSecondDelay (5); - MmioAnd32 ( - HpipeAddr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, - ~HPIPE_SAMPLER_MASK - ); - - /* FFE resistor tuning for different bandwidth */ - Mask = HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_MASK | - HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_MASK; - Data = (0x1 << HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_OFFSET) | - (0x3 << HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_OFFSET); - MmioAndThenOr32 (HpipeAddr + HPIPE_G3_SET3_REG, ~Mask, Data); - - /* Pattern lock lost timeout disable */ - MmioAnd32 (HpipeAddr + HPIPE_FRAME_DETECT_CTRL_3_REG, ~HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK); - - /* Configure DFE adaptations */ - MmioAndThenOr32 ( - HpipeAddr + HPIPE_CDR_CONTROL_REG, - ~(HPIPE_CDR_MAX_DFE_ADAPT_1_MASK | HPIPE_CDR_MAX_DFE_ADAPT_0_MASK | HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK), - 0x1 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET - ); - MmioAnd32 (HpipeAddr + HPIPE_DFE_CONTROL_REG, ~HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK); - - /* Hpipe Generation 2 setting 1*/ - MmioAndThenOr32 ( - HpipeAddr + HPIPE_G2_SET1_REG, - ~(HPIPE_GX_SET1_RX_SELMUPI_MASK | HPIPE_GX_SET1_RX_SELMUPP_MASK | HPIPE_GX_SET1_RX_SELMUFI_MASK), - 0x1 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET - ); - - /* DFE enable */ - MmioAndThenOr32 ( - HpipeAddr + HPIPE_G2_SET4_REG, - ~HPIPE_GX_SET4_DFE_RES_MASK, - 0x3 << HPIPE_GX_SET4_DFE_RES_OFFSET - ); - - /* Configure DFE Resolution */ - MmioAndThenOr32 ( - HpipeAddr + HPIPE_LANE_CFG4_REG, - ~HPIPE_LANE_CFG4_DFE_EN_SEL_MASK, - 0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET - ); - - /* VDD calibration control */ - MmioAndThenOr32 ( - HpipeAddr + HPIPE_VDD_CAL_CTRL_REG, - ~HPIPE_EXT_SELLV_RXSAMPL_MASK, - 0x16 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET - ); - - /* Set PLL Charge-pump Current Control */ - MmioAndThenOr32 (HpipeAddr + HPIPE_G3_SET5_REG, ~HPIPE_GX_SET5_ICP_MASK, 0x4); - - /* Set lane rqualization remote setting */ - Mask = HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK | - HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK | - HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK; - Data = (0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET) | - (0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET) | - (HPIPE_LANE_CFG_FOM_PRESET_VECTOR_DEFAULT); - MmioAndThenOr32 (HpipeAddr + HPIPE_LANE_EQ_REMOTE_SETTING_REG, ~Mask, Data); - - /* Set phy in root complex mode */ - MmioOr32 (HpipeAddr + HPIPE_LANE_EQU_CONFIG_0_REG, HPIPE_CFG_PHY_RC_EP_MASK); -} - -STATIC -EFI_STATUS -ComPhyPciePhyPowerUp ( - IN UINT32 Lane, - IN UINT32 PcieWidth, - IN EFI_PHYSICAL_ADDRESS ComPhyBase, - IN EFI_PHYSICAL_ADDRESS HpipeBase -) -{ - EFI_STATUS Status = EFI_SUCCESS; - UINT8 StartLane, EndLane, Loop; - UINT32 Data; - - /* - * For PCIe by4 or by2 - release from reset only after finish to - * configure all lanes - */ - if ((PcieWidth == 1) || (Lane == (PcieWidth - 1))) { - if (PcieWidth != 1) { - /* Allows writing to all lanes in one write */ - RegSet (ComPhyBase + COMMON_PHY_SD_CTRL1, - COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_WR_ENABLE, - COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK); - StartLane = 0; - EndLane = PcieWidth; - - /* - * Release from PIPE soft reset - * for PCIe by4 or by2 - release from soft reset - * all lanes - can't use read modify write - */ - RegSet (HPIPE_ADDR (HpipeBase, 0) + HPIPE_RST_CLK_CTRL_REG, - HPIPE_RST_CLK_CTRL_FIXED_PCLK_WIDTH_8 | HPIPE_RST_CLK_CTRL_MODE_REFDIV_4, - HPIPE_RST_CLK_CTRL_CLR_ALL_MASK); - } else { - StartLane = Lane; - EndLane = Lane + 1; - - /* - * Release from PIPE soft reset - * for PCIe by4 or by2 - release from soft reset - * all lanes - */ - RegSet (HPIPE_ADDR (HpipeBase, Lane) + HPIPE_RST_CLK_CTRL_REG, - HPIPE_RST_CLK_CTRL_PIPE_RST_DISABLE, - HPIPE_RST_CLK_CTRL_PIPE_RST_MASK); - } - - if (PcieWidth != 1) { - /* Disable writing to all lanes with one write */ - RegSet (ComPhyBase + COMMON_PHY_SD_CTRL1, - COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_WR_DISABLE, - COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK); - } - MemoryFence (); - - /* Wait 20ms until status of all lanes stabilize */ - MicroSecondDelay (20000); - - /* Make sure all lanes are UP */ - for (Loop = StartLane; Loop < EndLane; Loop++) { - Data = MmioRead32 (HPIPE_ADDR (HpipeBase, Loop) + HPIPE_LANE_STATUS0_REG); - - if ((Data & HPIPE_LANE_STATUS0_PCLK_EN_MASK) == 0) { - DEBUG ((DEBUG_ERROR, - "%a: Read from lane%d, reg = %p - value = 0x%x\n", - __FUNCTION__, - Loop, - HPIPE_ADDR (HpipeBase, Loop) + HPIPE_LANE_STATUS0_REG, - Data)); - DEBUG ((DEBUG_ERROR, - "%a: HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n", - __FUNCTION__)); - Status = EFI_D_ERROR; - break; - } - } - } - - return Status; -} - -STATIC -EFI_STATUS -ComPhyPciePowerUp ( - IN UINT8 ChipId, - IN UINT32 Lane, - IN UINT32 PcieWidth, - IN EFI_PHYSICAL_ADDRESS HpipeBase, - IN EFI_PHYSICAL_ADDRESS ComPhyBase - ) -{ - EFI_STATUS Status = EFI_SUCCESS; - EFI_PHYSICAL_ADDRESS HpipeAddr = HPIPE_ADDR(HpipeBase, Lane); - EFI_PHYSICAL_ADDRESS ComPhyAddr = COMPHY_ADDR(ComPhyBase, Lane); - UINT32 PcieClk; - - /* - * Obtain clock direction from sample-at-reset configuration. - * 4th and 5th SerDes lanes can belong only to PCIE Port1 and - * Port2, which use different clock type specifier than Port0. - */ - if (Lane == 4 || Lane == 5) { - PcieClk = SampleAtResetGetPcieClockDirection (ChipId, CP110_PCIE_REF_CLK_TYPE12); - } else { - PcieClk = SampleAtResetGetPcieClockDirection (ChipId, CP110_PCIE_REF_CLK_TYPE0); - } - - DEBUG ((DEBUG_INFO, "%a: ChipId: %d PcieClk:%d\n", __FUNCTION__, ChipId, PcieClk)); - - DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset ComPhy\n")); - - ComPhyPcieRFUConfiguration (Lane, PcieWidth, ComPhyAddr); - - DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy configuration\n")); - - ComPhyPciePhyConfiguration (Lane, PcieWidth, PcieClk, ComPhyAddr, HpipeAddr); - - DEBUG((DEBUG_INFO, "ComPhy: stage: Set analog paramters\n")); - - ComPhyPcieSetAnalogParameters (HpipeAddr); - - DEBUG ((DEBUG_INFO, "%a: stage: ComPhy power up and check PLL\n", __FUNCTION__)); - - Status = ComPhyPciePhyPowerUp (Lane, PcieWidth, ComPhyBase, HpipeBase); - - return Status; -} - -STATIC -VOID ComPhyUsb3RFUConfiguration ( IN EFI_PHYSICAL_ADDRESS ComPhyAddr ) @@ -1229,7 +745,12 @@ ComPhyCp110Init ( case COMPHY_TYPE_PCIE1: case COMPHY_TYPE_PCIE2: case COMPHY_TYPE_PCIE3: - Status = ComPhyPciePowerUp (ChipId, Lane, PcieWidth, HpipeBaseAddr, ComPhyBaseAddr); + Status = ComPhySmc (MV_SIP_COMPHY_POWER_ON, + PtrChipCfg->ComPhyBaseAddr, + Lane, + COMPHY_FW_PCIE_FORMAT (PcieWidth, + COMPHY_PCIE_MODE, + PtrComPhyMap->Speed)); break; case COMPHY_TYPE_SATA0: case COMPHY_TYPE_SATA1: -- 2.7.4