[platforms: PATCH v2 3/6] Marvell/Library: ComPhyLib: Configure RXAUI in ARM-TF

[Marcin Wojtas <mw@semihalf.com>]

From: Grzegorz Jaszczyk <jaz@semihalf.com>

Replace the comphy initialization for RXAUI with appropriate SMC call,
so the ARM-TF will execute required serdes configuration.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
 Silicon/Marvell/Library/ComPhyLib/ComPhySipSvc.h |   1 +
 Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c  | 257 +-------------------
 2 files changed, 5 insertions(+), 253 deletions(-)

diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhySipSvc.h b/Silicon/Marvell/Library/ComPhyLib/ComPhySipSvc.h
index 33ab3a6..d156af6 100644
--- a/Silicon/Marvell/Library/ComPhyLib/ComPhySipSvc.h
+++ b/Silicon/Marvell/Library/ComPhyLib/ComPhySipSvc.h
@@ -45,6 +45,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #define MV_SIP_COMPHY_POWER_OFF     0x82000002
 #define MV_SIP_COMPHY_PLL_LOCK      0x82000003
 
+#define COMPHY_FW_MODE_FORMAT(mode) (mode << 12)
 #define COMPHY_FW_FORMAT(mode, idx, speeds) \
                                     ((mode << 12) | (idx << 8) | (speeds << 2))
 #define COMPHY_FW_PCIE_FORMAT(pcie_width, mode, speeds) \
diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
index 6cefee9..c46cad1 100755
--- a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
+++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
@@ -261,27 +261,6 @@ ComphyUsb3PowerUp (
 }
 
 STATIC
-UINT32
-PollingWithTimeout (
-  IN EFI_PHYSICAL_ADDRESS Addr,
-  IN UINT32 Val,
-  IN UINT32 Mask,
-  IN UINT64 Usec_timeout
-  )
-{
-  UINT32 Data;
-
-  do {
-    MicroSecondDelay(1);
-    Data = MmioRead32(Addr) & Mask;
-  } while (Data != Val  && --Usec_timeout > 0);
-
-  if (Usec_timeout == 0)
-    return Data;
-  return 0;
-}
-
-STATIC
 VOID
 ComPhySataMacPowerDown (
   IN EFI_PHYSICAL_ADDRESS SataBase
@@ -424,237 +403,6 @@ ComPhySataPowerUp (
 }
 
 STATIC
-EFI_STATUS
-ComPhyEthCommonRFUPowerUp (
-  IN EFI_PHYSICAL_ADDRESS SdIpAddr
-)
-{
-  EFI_STATUS Status = EFI_SUCCESS;
-  UINT32 Mask, Data;
-  EFI_PHYSICAL_ADDRESS Addr;
-
-  /* SerDes External Configuration */
-  Mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
-  Data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
-  Mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
-  Data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
-  Mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
-  Data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
-  RegSet (SdIpAddr + SD_EXTERNAL_CONFIG0_REG, Data, Mask);
-
-  /* Check PLL rx & tx ready */
-  Addr = SdIpAddr + SD_EXTERNAL_STATUS0_REG;
-  Data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | SD_EXTERNAL_STATUS0_PLL_TX_MASK;
-  Mask = Data;
-  Data = PollingWithTimeout (Addr, Data, Mask, 15000);
-  if (Data != 0) {
-    DEBUG((DEBUG_ERROR, "ComPhy: Read from reg = %p - value = 0x%x\n",
-      SdIpAddr + SD_EXTERNAL_STATUS0_REG, Data));
-    DEBUG((DEBUG_ERROR, "ComPhy: SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n",
-      (Data & SD_EXTERNAL_STATUS0_PLL_RX_MASK),
-      (Data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)));
-    Status = EFI_D_ERROR;
-  }
-
-  /* RX init */
-  Mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
-  Data = 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
-  RegSet (SdIpAddr + SD_EXTERNAL_CONFIG1_REG, Data, Mask);
-
-  /* Check that RX init done */
-  Addr = SdIpAddr + SD_EXTERNAL_STATUS0_REG;
-  Data = SD_EXTERNAL_STATUS0_RX_INIT_MASK;
-  Mask = Data;
-  Data = PollingWithTimeout (Addr, Data, Mask, 100);
-  if (Data != 0) {
-    DEBUG((DEBUG_ERROR, "ComPhy: Read from reg = %p - value = 0x%x\n",
-      SdIpAddr + SD_EXTERNAL_STATUS0_REG, Data));
-    DEBUG((DEBUG_ERROR, "ComPhy: SD_EXTERNAL_STATUS0_RX_INIT is 0\n"));
-    Status = EFI_D_ERROR;
-  }
-  Mask =  SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
-  Data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
-  Mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
-  Data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
-  RegSet (SdIpAddr + SD_EXTERNAL_CONFIG1_REG, Data, Mask);
-
-  return Status;
-}
-
-STATIC
-EFI_STATUS
-ComPhyRxauiRFUConfiguration (
-  IN UINT32 Lane,
-  IN EFI_PHYSICAL_ADDRESS ComPhyAddr,
-  IN EFI_PHYSICAL_ADDRESS SdIpAddr
-)
-{
-  UINT32 Mask, Data;
-
-  MmioAndThenOr32 (
-          ComPhyAddr + COMMON_PHY_CFG1_REG,
-          ~(COMMON_PHY_CFG1_PWR_UP_MASK | COMMON_PHY_CFG1_PIPE_SELECT_MASK),
-          COMMON_PHY_CFG1_PWR_UP_MASK
-          );
-
-  switch (Lane) {
-  case 2:
-  case 4:
-    MmioOr32 (ComPhyAddr + COMMON_PHY_SD_CTRL1, COMMON_PHY_SD_CTRL1_RXAUI0_MASK);
-  case 3:
-  case 5:
-    MmioOr32 (ComPhyAddr + COMMON_PHY_SD_CTRL1, COMMON_PHY_SD_CTRL1_RXAUI1_MASK);
-    break;
-  default:
-    DEBUG ((DEBUG_ERROR, "RXAUI used on invalid lane %d\n", Lane));
-    return EFI_INVALID_PARAMETER;
-  }
-
-  /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */
-  Mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK |
-         SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK |
-         SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK |
-         SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK |
-         SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK |
-         SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK |
-         SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK;
-  Data = (0xb << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET) |
-         (0xb << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET) |
-         (0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET);
-  MmioAndThenOr32 (SdIpAddr + SD_EXTERNAL_CONFIG0_REG, ~Mask, Data);
-
-  /* Release from hard reset */
-  Mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK |
-         SD_EXTERNAL_CONFIG1_RESET_CORE_MASK |
-         SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
-  Data = SD_EXTERNAL_CONFIG1_RESET_IN_MASK |
-         SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
-  MmioAndThenOr32 (SdIpAddr + SD_EXTERNAL_CONFIG1_REG, ~Mask, Data);
-
-  /* Wait 1ms - until band gap and ref clock are ready */
-  MicroSecondDelay (1000);
-  MemoryFence ();
-
-  return EFI_SUCCESS;
-}
-
-STATIC
-VOID
-ComPhyRxauiPhyConfiguration (
-  IN EFI_PHYSICAL_ADDRESS HpipeAddr
-)
-{
-  /* Set reference clock */
-  MmioAnd32 (HpipeAddr + HPIPE_MISC_REG, ~HPIPE_MISC_REFCLK_SEL_MASK);
-
-  /* Power and PLL Control */
-  MmioAndThenOr32 (
-          HpipeAddr + HPIPE_PWR_PLL_REG,
-          ~(HPIPE_PWR_PLL_REF_FREQ_MASK | HPIPE_PWR_PLL_PHY_MODE_MASK),
-          0x1 | (0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET)
-          );
-
-  /* Loopback register */
-  MmioAndThenOr32 (
-          HpipeAddr + HPIPE_LOOPBACK_REG,
-          ~HPIPE_LOOPBACK_SEL_MASK,
-          0x1 << HPIPE_LOOPBACK_SEL_OFFSET
-          );
-
-  /* Rx control 1 */
-  MmioOr32 (
-          HpipeAddr + HPIPE_RX_CONTROL_1_REG,
-          HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK | HPIPE_RX_CONTROL_1_CLK8T_EN_MASK
-          );
-
-  /* DTL Control */
-  MmioAnd32 (HpipeAddr + HPIPE_PWR_CTR_DTL_REG, ~HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK);
-}
-
-STATIC
-VOID
-ComPhyRxauiSetAnalogParameters (
-  IN EFI_PHYSICAL_ADDRESS HpipeAddr,
-  IN EFI_PHYSICAL_ADDRESS SdIpAddr
-)
-{
-  UINT32 Mask, Data;
-
-  /* SERDES External Configuration 2 */
-  MmioOr32 (SdIpAddr + SD_EXTERNAL_CONFIG2_REG, SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK);
-
-  /* DFE Resolution control */
-  MmioOr32 (HpipeAddr + HPIPE_DFE_REG0, HPIPE_DFE_RES_FORCE_MASK);
-
-  /* Generation 1 setting_0 */
-  MmioAndThenOr32 (
-          HpipeAddr + HPIPE_G1_SET0_REG,
-          ~HPIPE_GX_SET0_TX_EMPH1_MASK,
-          0xe << HPIPE_GX_SET0_TX_EMPH1_OFFSET
-          );
-
-  /* Generation 1 setting 1 */
-  Mask = HPIPE_GX_SET1_RX_SELMUPI_MASK |
-         HPIPE_GX_SET1_RX_SELMUPP_MASK |
-         HPIPE_GX_SET1_RX_DFE_EN_MASK;
-  Data = 0x1 |
-         (0x1 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET) |
-         (0x1 << HPIPE_GX_SET1_RX_DFE_EN_OFFSET);
-  MmioAndThenOr32 (HpipeAddr + HPIPE_G1_SET1_REG, ~Mask, Data);
-
-  /* DFE F3-F5 Coefficient Control */
-  MmioAnd32 (
-          HpipeAddr + HPIPE_DFE_F3_F5_REG,
-          ~(HPIPE_DFE_F3_F5_DFE_EN_MASK | HPIPE_DFE_F3_F5_DFE_CTRL_MASK)
-          );
-
-  /* Configure Generation 1 setting 4 (DFE) */
-  MmioAndThenOr32 (
-          HpipeAddr + HPIPE_G1_SET4_REG,
-          ~HPIPE_GX_SET4_DFE_RES_MASK,
-          0x1 << HPIPE_GX_SET4_DFE_RES_OFFSET
-          );
-
-  /* Generation 1 setting 3 */
-  MmioOr32 (HpipeAddr + HPIPE_G1_SET3_REG, HPIPE_GX_SET3_FBCK_SEL_MASK);
-}
-
-STATIC
-EFI_STATUS
-ComPhyRxauiPowerUp (
-  IN UINT32 Lane,
-  IN EFI_PHYSICAL_ADDRESS HpipeBase,
-  IN EFI_PHYSICAL_ADDRESS ComPhyBase
-  )
-{
-  EFI_STATUS Status;
-  EFI_PHYSICAL_ADDRESS HpipeAddr = HPIPE_ADDR(HpipeBase, Lane);
-  EFI_PHYSICAL_ADDRESS SdIpAddr = SD_ADDR(HpipeBase, Lane);
-  EFI_PHYSICAL_ADDRESS ComPhyAddr = COMPHY_ADDR(ComPhyBase, Lane);
-
-  DEBUG ((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset ComPhy\n"));
-
-  Status = ComPhyRxauiRFUConfiguration (Lane, ComPhyAddr, SdIpAddr);
-  if (EFI_ERROR(Status)) {
-    return Status;
-  }
-
-  DEBUG ((DEBUG_INFO, "ComPhy: stage: ComPhy configuration\n"));
-
-  ComPhyRxauiPhyConfiguration (HpipeAddr);
-
-  DEBUG ((DEBUG_INFO, "ComPhy: stage: Set analog paramters\n"));
-
-  ComPhyRxauiSetAnalogParameters (HpipeAddr, SdIpAddr);
-
-  DEBUG ((DEBUG_INFO, "ComPhy: stage: RFU configurations - Power Up PLL,Tx,Rx\n"));
-
-  Status = ComPhyEthCommonRFUPowerUp (SdIpAddr);
-
-  return Status;
-}
-
-STATIC
 VOID
 ComPhyMuxCp110 (
   IN CHIP_COMPHY_CONFIG *PtrChipCfg,
@@ -803,7 +551,10 @@ ComPhyCp110Init (
       break;
     case COMPHY_TYPE_RXAUI0:
     case COMPHY_TYPE_RXAUI1:
-      Status = ComPhyRxauiPowerUp(Lane, HpipeBaseAddr, ComPhyBaseAddr);
+      Status = ComPhySmc (MV_SIP_COMPHY_POWER_ON,
+                 PtrChipCfg->ComPhyBaseAddr,
+                 Lane,
+                 COMPHY_FW_MODE_FORMAT (COMPHY_RXAUI_MODE));
       break;
     default:
       DEBUG((DEBUG_ERROR, "Unknown SerDes Type, skip initialize SerDes %d\n",
-- 
2.7.4