From: Marcin Wojtas <mw@semihalf.com>
To: edk2-devel@lists.01.org
Cc: feng.tian@intel.com, michael.d.kinney@intel.com,
liming.gao@intel.com, leif.lindholm@linaro.org,
ard.biesheuvel@linaro.org, nadavh@marvell.com, mw@semihalf.com,
jsd@semihalf.com
Subject: [PATCH] ArmPkg/GenericWatchdogDxe: Split 64bit register write to 2x32bit
Date: Thu, 2 Aug 2018 16:49:56 +0200 [thread overview]
Message-ID: <1533221396-11620-1-git-send-email-mw@semihalf.com> (raw)
EDK2 code uses a single 64bit write to update SBSA watchdog
compare registers, however an access to mmio registers should
be 32bit for some SoCs. Current usage of MmioWrite64 resulted
in an unpredicted behavior. Fix this by modifying
WatchdogWriteCompareRegister routine to use two consecutive
32bit writes to Watchdog Compare Register Low and High.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c
index 3180f01..b25d210 100644
--- a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c
+++ b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c
@@ -56,7 +56,11 @@ WatchdogWriteCompareRegister (
UINT64 Value
)
{
- MmioWrite64 (GENERIC_WDOG_COMPARE_VALUE_REG, Value);
+ MmioWrite32 (GENERIC_WDOG_COMPARE_VALUE_REG, Value & MAX_UINT32);
+ MmioWrite32 (
+ GENERIC_WDOG_COMPARE_VALUE_REG + sizeof (UINT32),
+ (Value >> 32) & MAX_UINT32
+ );
}
VOID
--
2.7.4
next reply other threads:[~2018-08-02 14:50 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-02 14:49 Marcin Wojtas [this message]
2018-08-02 14:59 ` [PATCH] ArmPkg/GenericWatchdogDxe: Split 64bit register write to 2x32bit Ard Biesheuvel
2018-08-02 15:12 ` Marcin Wojtas
2018-08-02 18:32 ` Ard Biesheuvel
2018-08-02 20:14 ` Leif Lindholm
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