From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c01::242; helo=mail-pl0-x242.google.com; envelope-from=sumit.garg@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pl0-x242.google.com (mail-pl0-x242.google.com [IPv6:2607:f8b0:400e:c01::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1722E210C4DB5 for ; Thu, 2 Aug 2018 23:42:19 -0700 (PDT) Received: by mail-pl0-x242.google.com with SMTP id f6-v6so2142789plo.1 for ; Thu, 02 Aug 2018 23:42:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dMI5JYo7UNUCX7qhQtXmYq5671fFvNLWtuZcCv+dwBc=; b=JftK4RYg9IImG2cuhBPpV7nrr7grUeOsHlaT5RTsI4fTDzKDMJr2UfqLcN9oaULfZV BiCPMO6sefcgxgePUgGrBhybmteJKX6RJTOYwuVIhr9Y8KPYSJuL7O5ydWaSJq4uFfvB Dc5oA/B4FWA2oLokacL1KFN0mfuOiXG9H96eo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dMI5JYo7UNUCX7qhQtXmYq5671fFvNLWtuZcCv+dwBc=; b=Px2eYSSxUabzfpWlz1E8NYJVEHxzHG/q5GcCeSunupCiyh20kJFwhOMl/EipBPBJvt sVoogLJ+/PWPgcXcP5uzIFv30TXPUJfRngjBTyaECxWRb04LR3hKCFSs/Bs1EPXiIeYl LlYuT2V+vJOB7pkJCIA4280CiV/1+RhwjdQ+S+k3t0NVq75MbPtQBUJzi91NYeIc8RPE JQPbZpEJT/JZvzJsIvwqRUqGL9GwB7pZgzTczCI8tK1ZjPg4txRZMrWOOo0ff5Fmxm30 FKlG4FAiWyUZ1q4v22P+NipoENvGBj1xevTTndip4mLmOp6MZvGTJ7ArY8bRar1Jj2tx +Tpg== X-Gm-Message-State: AOUpUlEZ1dpijz7KaY5GiYol6TAMGc4WdTVBya9Z7bq48mLQQooKgfEb +AOHBIIRG101SM+zcWLSCpNU303Dbwc= X-Google-Smtp-Source: AAOMgpe4qCFyOXhVJvdvAPuyEdlOR3oJf3MJGpHevKb/P3Jv8m3YJbYOhdaaYNEU9NXbHucnyPNGEg== X-Received: by 2002:a17:902:7683:: with SMTP id m3-v6mr2275777pll.255.1533278538399; Thu, 02 Aug 2018 23:42:18 -0700 (PDT) Received: from localhost.localdomain ([117.197.43.141]) by smtp.gmail.com with ESMTPSA id t88-v6sm10505465pfg.10.2018.08.02.23.42.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 02 Aug 2018 23:42:17 -0700 (PDT) From: Sumit Garg To: edk2-devel@lists.01.org Date: Fri, 3 Aug 2018 12:11:35 +0530 Message-Id: <1533278495-25323-3-git-send-email-sumit.garg@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533278495-25323-1-git-send-email-sumit.garg@linaro.org> References: <1533278495-25323-1-git-send-email-sumit.garg@linaro.org> Subject: [PATCH edk2-platforms 2/2] Silicon/SynQuacer: Add status property in PCIe & SDHC DT nodes X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 03 Aug 2018 06:42:19 -0000 Add status = "disabled" property by default for PCIe and SDHC DT nodes. If required, update them at runtime with status = "okay". Using this method we don't need extra DTB_PADDING. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sumit Garg Cc: Leif Lindholm Reviewed-by: Ard Biesheuvel --- .../Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 3 ++ .../SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c | 40 ++++------------------ 2 files changed, 10 insertions(+), 33 deletions(-) diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index d6a5f013e58c..003e21bd6f85 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -473,6 +473,7 @@ msi-map = <0x000 &its 0x0 0x7f00>; dma-coherent; + status = "disabled"; }; pcie1: pcie@70000000 { @@ -492,6 +493,7 @@ msi-map = <0x0 &its 0x10000 0x7f00>; dma-coherent; + status = "disabled"; }; gpio: gpio@51000000 { @@ -537,6 +539,7 @@ clocks = <&clk_alw_c_0 &clk_alw_b_0>; clock-names = "core", "iface"; dma-coherent; + status = "disabled"; }; clk_alw_1_8: spi_ihclk { diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c index 77db30c204fe..96090c20502c 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c @@ -22,32 +22,6 @@ #include #include -// add enough space for three instances of 'status = "disabled"' -#define DTB_PADDING 64 - -STATIC -VOID -DisableDtNode ( - IN VOID *Dtb, - IN CONST CHAR8 *NodePath - ) -{ - INT32 Node; - INT32 Rc; - - Node = fdt_path_offset (Dtb, NodePath); - if (Node < 0) { - DEBUG ((DEBUG_ERROR, "%a: failed to locate DT path '%a': %a\n", - __FUNCTION__, NodePath, fdt_strerror (Node))); - return; - } - Rc = fdt_setprop_string (Dtb, Node, "status", "disabled"); - if (Rc < 0) { - DEBUG ((DEBUG_ERROR, "%a: failed to set status to 'disabled' on '%a': %a\n", - __FUNCTION__, NodePath, fdt_strerror (Rc))); - } -} - STATIC VOID EnableDtNode ( @@ -105,7 +79,7 @@ DtPlatformLoadDtb ( return EFI_NOT_FOUND; } - CopyDtbSize = OrigDtbSize + DTB_PADDING; + CopyDtbSize = OrigDtbSize; CopyDtb = AllocatePool (CopyDtbSize); if (CopyDtb == NULL) { return EFI_OUT_OF_RESOURCES; @@ -118,17 +92,17 @@ DtPlatformLoadDtb ( return EFI_NOT_FOUND; } - if (!(PcdGet8 (PcdPcieEnableMask) & BIT0)) { - DisableDtNode (CopyDtb, "/pcie@60000000"); + if (PcdGet8 (PcdPcieEnableMask) & BIT0) { + EnableDtNode (CopyDtb, "/pcie@60000000"); } - if (!(PcdGet8 (PcdPcieEnableMask) & BIT1)) { - DisableDtNode (CopyDtb, "/pcie@70000000"); + if (PcdGet8 (PcdPcieEnableMask) & BIT1) { + EnableDtNode (CopyDtb, "/pcie@70000000"); } SettingsVal = PcdGet64 (PcdPlatformSettings); Settings = (SYNQUACER_PLATFORM_VARSTORE_DATA *)&SettingsVal; - if (Settings->EnableEmmc == EMMC_DISABLED) { - DisableDtNode (CopyDtb, "/sdhci@52300000"); + if (Settings->EnableEmmc == EMMC_ENABLED) { + EnableDtNode (CopyDtb, "/sdhci@52300000"); } if (IsOpteePresent()) { -- 2.7.4