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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id w27-v6sm181697lfk.5.2018.08.07.02.00.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 07 Aug 2018 02:00:15 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com Date: Tue, 7 Aug 2018 10:58:10 +0200 Message-Id: <1533632298-4981-2-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533632298-4981-1-git-send-email-mw@semihalf.com> References: <1533632298-4981-1-git-send-email-mw@semihalf.com> Subject: [platforms: PATCH v2 1/9] Marvell/Armada7k8k: Import device tree X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 07 Aug 2018 09:00:20 -0000 Add a device tree description of the Armada7k8k SoCs, whose sources are aligned to the Linux v4.18-rc7. Enablement for each board will be done in the follow-up commits. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi | 16 + Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts | 267 +++++++++++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi | 16 + Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi | 64 +++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi | 26 + Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts | 336 +++++++++++++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts | 371 +++++++++++++++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi | 25 + Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi | 108 +++++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi | 31 ++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi | 43 ++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi | 264 ++++++++++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi | 10 + Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi | 503 ++++++++++++++++++++ 14 files changed, 2080 insertions(+) create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi new file mode 100644 index 0000000..e2edc26 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for the Armada 7020 SoC, made of an AP806 Dual and + * one CP110. + */ + +#include "armada-ap806-dual.dtsi" +#include "armada-70x0.dtsi" + +/ { + model = "Marvell Armada 7020"; + compatible = "marvell,armada7020", "marvell,armada-ap806-dual", + "marvell,armada-ap806"; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts new file mode 100644 index 0000000..6b28bbe --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts @@ -0,0 +1,267 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for Marvell Armada 7040 Development board platform + */ + +#include "armada-7040.dtsi" + +#define GPIO_ACTIVE_HIGH 0 +#define GPIO_ACTIVE_LOW 1 + +/ { + model = "Marvell Armada 7040 DB board"; + compatible = "marvell,armada7040-db", "marvell,armada7040", + "marvell,armada-ap806-quad", "marvell,armada-ap806"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + aliases { + ethernet0 = &cp0_eth0; + ethernet1 = &cp0_eth1; + ethernet2 = &cp0_eth2; + }; + + cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb3h0-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&expander0 0 GPIO_ACTIVE_HIGH>; + }; + + cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb3h1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&expander0 1 GPIO_ACTIVE_HIGH>; + }; + + cp0_usb3_0_phy: cp0-usb3-0-phy { + compatible = "usb-nop-xceiv"; + vcc-supply = <&cp0_reg_usb3_0_vbus>; + }; + + cp0_usb3_1_phy: cp0-usb3-1-phy { + compatible = "usb-nop-xceiv"; + vcc-supply = <&cp0_reg_usb3_1_vbus>; + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; +}; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0 0x200000>; + }; + partition@400000 { + label = "Filesystem"; + reg = <0x200000 0xce0000>; + }; + }; + }; +}; + +&uart0 { + status = "okay"; + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; +}; + + +&cp0_pcie2 { + status = "okay"; +}; + +&cp0_i2c0 { + status = "okay"; + clock-frequency = <100000>; + + expander0: pca9555@21 { + compatible = "nxp,pca9555"; + pinctrl-names = "default"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x21>; + /* + * IO0_0: USB3_PWR_EN0 IO1_0: USB_3_1_Dev_Detect + * IO0_1: USB3_PWR_EN1 IO1_1: USB2_1_current_limit + * IO0_2: DDR3_4_Detect IO1_2: Hcon_IO_RstN + * IO0_3: USB2_DEVICE_DETECT + * IO0_4: GPIO_0 IO1_4: SD_Status + * IO0_5: GPIO_1 IO1_5: LDO_5V_Enable + * IO0_6: IHB_5V_Enable IO1_6: PWR_EN_eMMC + * IO0_7: IO1_7: SDIO_Vcntrl + */ + }; +}; + +&cp0_nand_controller { + /* + * SPI on CPM and NAND have common pins on this board. We can + * use only one at a time. To enable the NAND (which will + * disable the SPI), the "status = "okay";" line have to be + * added here. + */ + pinctrl-0 = <&nand_pins>, <&nand_rb>; + pinctrl-names = "default"; + + nand@0 { + reg = <0>; + label = "pxa3xx_nand-0"; + nand-rb = <0>; + nand-on-flash-bbt; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0 0x200000>; + }; + + partition@200000 { + label = "Linux"; + reg = <0x200000 0xe00000>; + }; + + partition@1000000 { + label = "Filesystem"; + reg = <0x1000000 0x3f000000>; + }; + + }; + }; +}; + +&cp0_spi1 { + status = "okay"; + + spi-flash@0 { + #address-cells = <0x1>; + #size-cells = <0x1>; + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <20000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0x0 0x200000>; + }; + + partition@400000 { + label = "Filesystem"; + reg = <0x200000 0xe00000>; + }; + }; + }; +}; + +&cp0_sata0 { + status = "okay"; +}; + +&cp0_usb3_0 { + usb-phy = <&cp0_usb3_0_phy>; + status = "okay"; +}; + +&cp0_usb3_1 { + usb-phy = <&cp0_usb3_1_phy>; + status = "okay"; +}; + +&ap_sdhci0 { + status = "okay"; + bus-width = <4>; + no-1-8-v; + non-removable; +}; + +&cp0_sdhci0 { + status = "okay"; + bus-width = <4>; + no-1-8-v; + cd-gpios = <&expander0 12 GPIO_ACTIVE_LOW>; +}; + +&cp0_mdio { + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&cp0_ethernet { + status = "okay"; +}; + +&cp0_eth0 { + status = "okay"; + /* Network PHY */ + phy-mode = "10gbase-kr"; + /* Generic PHY, providing serdes lanes */ + phys = <&cp0_comphy2 0>; + + fixed-link { + speed = <10000>; + full-duplex; + }; +}; + +&cp0_eth1 { + status = "okay"; + /* Network PHY */ + phy = <&phy0>; + phy-mode = "sgmii"; + /* Generic PHY, providing serdes lanes */ + phys = <&cp0_comphy0 1>; +}; + +&cp0_eth2 { + status = "okay"; + phy = <&phy1>; + phy-mode = "rgmii-id"; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi new file mode 100644 index 0000000..03109b2 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for the Armada 7040 SoC, made of an AP806 Quad and + * one CP110. + */ + +#include "armada-ap806-quad.dtsi" +#include "armada-70x0.dtsi" + +/ { + model = "Marvell Armada 7040"; + compatible = "marvell,armada7040", "marvell,armada-ap806-quad", + "marvell,armada-ap806"; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi new file mode 100644 index 0000000..78f9d87 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2017 Marvell Technology Group Ltd. + * + * Device Tree file for the Armada 70x0 SoC + */ + +/ { + aliases { + gpio1 = &cp0_gpio1; + gpio2 = &cp0_gpio2; + spi1 = &cp0_spi0; + spi2 = &cp0_spi1; + }; +}; + +/* + * Instantiate the CP110 + */ +#define CP110_NAME cp0 +#define CP110_BASE f2000000 +#define CP110_PCIE_IO_BASE 0xf9000000 +#define CP110_PCIE_MEM_BASE 0xf6000000 +#define CP110_PCIE0_BASE f2600000 +#define CP110_PCIE1_BASE f2620000 +#define CP110_PCIE2_BASE f2640000 + +#include "armada-cp110.dtsi" + +#undef CP110_NAME +#undef CP110_BASE +#undef CP110_PCIE_IO_BASE +#undef CP110_PCIE_MEM_BASE +#undef CP110_PCIE0_BASE +#undef CP110_PCIE1_BASE +#undef CP110_PCIE2_BASE + +&cp0_gpio1 { + status = "okay"; +}; + +&cp0_gpio2 { + status = "okay"; +}; + +&cp0_syscon0 { + cp0_pinctrl: pinctrl { + compatible = "marvell,armada-7k-pinctrl"; + + nand_pins: nand-pins { + marvell,pins = + "mpp15", "mpp16", "mpp17", "mpp18", + "mpp19", "mpp20", "mpp21", "mpp22", + "mpp23", "mpp24", "mpp25", "mpp26", + "mpp27"; + marvell,function = "dev"; + }; + + nand_rb: nand-rb { + marvell,pins = "mpp13"; + marvell,function = "nf"; + }; + }; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi new file mode 100644 index 0000000..5d76345 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for the Armada 8020 SoC, made of an AP806 Dual and + * two CP110. + */ + +#include "armada-ap806-dual.dtsi" +#include "armada-80x0.dtsi" + +/ { + model = "Marvell Armada 8020"; + compatible = "marvell,armada8020", "marvell,armada-ap806-dual", + "marvell,armada-ap806"; +}; + +/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock + * in CP master is not connected (by package) to the oscillator. So + * disable it. However, the RTC clock in CP slave is connected to the + * oscillator so this one is let enabled. + */ + +&cp0_rtc { + status = "disabled"; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts new file mode 100644 index 0000000..7518029 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts @@ -0,0 +1,336 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for Marvell Armada 8040 Development board platform + */ + +#include "armada-8040.dtsi" + +#define GPIO_ACTIVE_HIGH 0 +#define GPIO_ACTIVE_LOW 1 + +/ { + model = "Marvell Armada 8040 DB board"; + compatible = "marvell,armada8040-db", "marvell,armada8040", + "marvell,armada-ap806-quad", "marvell,armada-ap806"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + aliases { + ethernet0 = &cp0_eth0; + ethernet1 = &cp0_eth2; + ethernet2 = &cp1_eth0; + ethernet3 = &cp1_eth1; + }; + + cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus { + compatible = "regulator-fixed"; + regulator-name = "cp0-usb3h0-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&expander0 0 GPIO_ACTIVE_HIGH>; + }; + + cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus { + compatible = "regulator-fixed"; + regulator-name = "cp0-usb3h1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&expander0 1 GPIO_ACTIVE_HIGH>; + }; + + cp0_usb3_0_phy: cp0-usb3-0-phy { + compatible = "usb-nop-xceiv"; + vcc-supply = <&cp0_reg_usb3_0_vbus>; + }; + + cp0_usb3_1_phy: cp0-usb3-1-phy { + compatible = "usb-nop-xceiv"; + vcc-supply = <&cp0_reg_usb3_1_vbus>; + }; + + cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus { + compatible = "regulator-fixed"; + regulator-name = "cp1-usb3h0-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&expander1 0 GPIO_ACTIVE_HIGH>; + }; + + cp1_usb3_0_phy: cp1-usb3-0-phy { + compatible = "usb-nop-xceiv"; + vcc-supply = <&cp1_reg_usb3_0_vbus>; + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; +}; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0 0x200000>; + }; + partition@400000 { + label = "Filesystem"; + reg = <0x200000 0xce0000>; + }; + }; + }; +}; + +/* Accessible over the mini-USB CON9 connector on the main board */ +&uart0 { + status = "okay"; + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; +}; + +/* CON6 on CP0 expansion */ +&cp0_pcie0 { + status = "okay"; +}; + +/* CON5 on CP0 expansion */ +&cp0_pcie2 { + status = "okay"; +}; + +&cp0_i2c0 { + status = "okay"; + clock-frequency = <100000>; + + /* U31 */ + expander0: pca9555@21 { + compatible = "nxp,pca9555"; + pinctrl-names = "default"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x21>; + }; + + /* U25 */ + expander1: pca9555@25 { + compatible = "nxp,pca9555"; + pinctrl-names = "default"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x25>; + }; + +}; + +/* CON4 on CP0 expansion */ +&cp0_sata0 { + status = "okay"; +}; + +/* CON9 on CP0 expansion */ +&cp0_usb3_0 { + usb-phy = <&cp0_usb3_0_phy>; + status = "okay"; +}; + +/* CON10 on CP0 expansion */ +&cp0_usb3_1 { + usb-phy = <&cp0_usb3_1_phy>; + status = "okay"; +}; + +&cp0_mdio { + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&cp0_ethernet { + status = "okay"; +}; + +&cp0_eth0 { + status = "okay"; + phy-mode = "10gbase-kr"; + + fixed-link { + speed = <10000>; + full-duplex; + }; +}; + +&cp0_eth2 { + status = "okay"; + phy = <&phy1>; + phy-mode = "rgmii-id"; +}; + +/* CON6 on CP1 expansion */ +&cp1_pcie0 { + status = "okay"; +}; + +/* CON7 on CP1 expansion */ +&cp1_pcie1 { + status = "okay"; +}; + +/* CON5 on CP1 expansion */ +&cp1_pcie2 { + status = "okay"; +}; + +&cp1_i2c0 { + status = "okay"; + clock-frequency = <100000>; +}; + +&cp1_spi1 { + status = "okay"; + + spi-flash@0 { + #address-cells = <0x1>; + #size-cells = <0x1>; + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <20000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "Boot"; + reg = <0x0 0x200000>; + }; + partition@200000 { + label = "Filesystem"; + reg = <0x200000 0xd00000>; + }; + partition@f00000 { + label = "Boot_2nd"; + reg = <0xf00000 0x100000>; + }; + }; + }; +}; + +/* + * Proper NAND usage will require DPR-76 to be in position 1-2, which disables + * MDIO signal of CP1. + */ +&cp1_nand_controller { + pinctrl-0 = <&nand_pins>, <&nand_rb>; + pinctrl-names = "default"; + + nand@0 { + reg = <0>; + nand-rb = <0>; + nand-on-flash-bbt; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0 0x200000>; + }; + partition@200000 { + label = "Linux"; + reg = <0x200000 0xe00000>; + }; + partition@1000000 { + label = "Filesystem"; + reg = <0x1000000 0x3f000000>; + }; + }; + }; +}; + +/* CON4 on CP1 expansion */ +&cp1_sata0 { + status = "okay"; +}; + +/* CON9 on CP1 expansion */ +&cp1_usb3_0 { + usb-phy = <&cp1_usb3_0_phy>; + status = "okay"; +}; + +/* CON10 on CP1 expansion */ +&cp1_usb3_1 { + status = "okay"; +}; + +&cp1_mdio { + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&cp1_ethernet { + status = "okay"; +}; + +&cp1_eth0 { + status = "okay"; + phy-mode = "10gbase-kr"; + + fixed-link { + speed = <10000>; + full-duplex; + }; +}; + +&cp1_eth1 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; +}; + +&ap_sdhci0 { + status = "okay"; + bus-width = <4>; + non-removable; +}; + +&cp0_sdhci0 { + status = "okay"; + bus-width = <8>; + non-removable; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts new file mode 100644 index 0000000..0e20e70 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts @@ -0,0 +1,371 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for MACCHIATOBin Armada 8040 community board platform + */ + +#include "armada-8040.dtsi" + +#define GPIO_ACTIVE_HIGH 0 +#define GPIO_ACTIVE_LOW 1 + +/ { + model = "Marvell 8040 MACCHIATOBin"; + compatible = "marvell,armada8040-mcbin", "marvell,armada8040", + "marvell,armada-ap806-quad", "marvell,armada-ap806"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + aliases { + ethernet0 = &cp0_eth0; + ethernet1 = &cp1_eth0; + ethernet2 = &cp1_eth1; + ethernet3 = &cp1_eth2; + }; + + /* Regulator labels correspond with schematics */ + v_3_3: regulator-3-3v { + compatible = "regulator-fixed"; + regulator-name = "v_3_3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + status = "okay"; + }; + + v_vddo_h: regulator-1-8v { + compatible = "regulator-fixed"; + regulator-name = "v_vddo_h"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + status = "okay"; + }; + + v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cp0_xhci_vbus_pins>; + regulator-name = "v_5v0_usb3_hst_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + status = "okay"; + }; + + usb3h0_phy: usb3_phy0 { + compatible = "usb-nop-xceiv"; + vcc-supply = <&v_5v0_usb3_hst_vbus>; + }; + + sfp_eth0: sfp-eth0 { + /* CON15,16 - CPM lane 4 */ + compatible = "sff,sfp"; + i2c-bus = <&sfpp0_i2c>; + los-gpio = <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>; + mod-def0-gpio = <&cp1_gpio1 27 GPIO_ACTIVE_LOW>; + tx-disable-gpio = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>; + tx-fault-gpio = <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cp1_sfpp0_pins>; + }; + + sfp_eth1: sfp-eth1 { + /* CON17,18 - CPS lane 4 */ + compatible = "sff,sfp"; + i2c-bus = <&sfpp1_i2c>; + los-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>; + mod-def0-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>; + tx-disable-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_HIGH>; + tx-fault-gpio = <&cp0_gpio2 30 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cp1_sfpp1_pins &cp0_sfpp1_pins>; + }; + + sfp_eth3: sfp-eth3 { + /* CON3,4 - CPS lane 5 */ + compatible = "sff,sfp"; + i2c-bus = <&sfp_1g_i2c>; + los-gpio = <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>; + mod-def0-gpio = <&cp0_gpio2 21 GPIO_ACTIVE_LOW>; + tx-disable-gpio = <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>; + tx-fault-gpio = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cp0_sfp_1g_pins &cp1_sfp_1g_pins>; + }; +}; + +&uart0 { + status = "okay"; + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; +}; + +&ap_sdhci0 { + bus-width = <8>; + /* + * Not stable in HS modes - phy needs "more calibration", so add + * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes. + */ + marvell,xenon-phy-slow-mode; + no-1-8-v; + no-sd; + no-sdio; + non-removable; + status = "okay"; + vqmmc-supply = <&v_vddo_h>; +}; + +&cp0_i2c0 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&cp0_i2c0_pins>; + status = "okay"; +}; + +&cp0_i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&cp0_i2c1_pins>; + status = "okay"; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + sfpp0_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + sfpp1_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + sfp_1g_i2c: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + }; +}; + +/* J25 UART header */ +&cp0_uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&cp0_uart1_pins>; + status = "okay"; +}; + +&cp0_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&cp0_ge_mdio_pins>; + status = "okay"; + + ge_phy: ethernet-phy@0 { + reg = <0>; + }; +}; + +&cp0_pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&cp0_pcie_pins>; + num-lanes = <4>; + num-viewport = <8>; + reset-gpio = <&cp0_gpio1 20 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&cp0_pinctrl { + cp0_ge_mdio_pins: ge-mdio-pins { + marvell,pins = "mpp32", "mpp34"; + marvell,function = "ge"; + }; + cp0_i2c1_pins: i2c1-pins { + marvell,pins = "mpp35", "mpp36"; + marvell,function = "i2c1"; + }; + cp0_i2c0_pins: i2c0-pins { + marvell,pins = "mpp37", "mpp38"; + marvell,function = "i2c0"; + }; + cp0_uart1_pins: uart1-pins { + marvell,pins = "mpp40", "mpp41"; + marvell,function = "uart1"; + }; + cp0_xhci_vbus_pins: xhci0-vbus-pins { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + cp0_sfp_1g_pins: sfp-1g-pins { + marvell,pins = "mpp51", "mpp53", "mpp54"; + marvell,function = "gpio"; + }; + cp0_pcie_pins: pcie-pins { + marvell,pins = "mpp52"; + marvell,function = "gpio"; + }; + cp0_sdhci_pins: sdhci-pins { + marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59", + "mpp60", "mpp61"; + marvell,function = "sdio"; + }; + cp0_sfpp1_pins: sfpp1-pins { + marvell,pins = "mpp62"; + marvell,function = "gpio"; + }; +}; + +&cp0_xmdio { + status = "okay"; + + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0>; + sfp = <&sfp_eth0>; + }; + + phy8: ethernet-phy@8 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <8>; + sfp = <&sfp_eth1>; + }; +}; + +&cp0_ethernet { + status = "okay"; +}; + +&cp0_eth0 { + status = "okay"; + /* Network PHY */ + phy = <&phy0>; + phy-mode = "10gbase-kr"; + /* Generic PHY, providing serdes lanes */ + phys = <&cp0_comphy4 0>; +}; + +&cp0_sata0 { + /* CPM Lane 0 - U29 */ + status = "okay"; +}; + +&cp0_sdhci0 { + /* U6 */ + broken-cd; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&cp0_sdhci_pins>; + status = "okay"; + vqmmc-supply = <&v_3_3>; +}; + +&cp0_usb3_0 { + /* J38? - USB2.0 only */ + status = "okay"; +}; + +&cp0_usb3_1 { + /* J38? - USB2.0 only */ + status = "okay"; +}; + +&cp1_ethernet { + status = "okay"; +}; + +&cp1_eth0 { + status = "okay"; + /* Network PHY */ + phy = <&phy8>; + phy-mode = "10gbase-kr"; + /* Generic PHY, providing serdes lanes */ + phys = <&cp1_comphy4 0>; +}; + +&cp1_eth1 { + /* CPS Lane 0 - J5 (Gigabit RJ45) */ + status = "okay"; + /* Network PHY */ + phy = <&ge_phy>; + phy-mode = "sgmii"; + /* Generic PHY, providing serdes lanes */ + phys = <&cp1_comphy0 1>; +}; + +&cp1_eth2 { + /* CPS Lane 5 */ + status = "okay"; + /* Network PHY */ + phy-mode = "2500base-x"; + managed = "in-band-status"; + /* Generic PHY, providing serdes lanes */ + phys = <&cp1_comphy5 2>; + sfp = <&sfp_eth3>; +}; + +&cp1_pinctrl { + cp1_sfpp1_pins: sfpp1-pins { + marvell,pins = "mpp8", "mpp10", "mpp11"; + marvell,function = "gpio"; + }; + cp1_spi1_pins: spi1-pins { + marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16"; + marvell,function = "spi1"; + }; + cp1_uart0_pins: uart0-pins { + marvell,pins = "mpp6", "mpp7"; + marvell,function = "uart0"; + }; + cp1_sfp_1g_pins: sfp-1g-pins { + marvell,pins = "mpp24"; + marvell,function = "gpio"; + }; + cp1_sfpp0_pins: sfpp0-pins { + marvell,pins = "mpp26", "mpp27", "mpp28", "mpp29"; + marvell,function = "gpio"; + }; +}; + +/* J27 UART header */ +&cp1_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&cp1_uart0_pins>; + status = "okay"; +}; + +&cp1_sata0 { + /* CPS Lane 1 - U32 */ + /* CPS Lane 3 - U31 */ + status = "okay"; +}; + +&cp1_spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&cp1_spi1_pins>; + status = "okay"; + + spi-flash@0 { + compatible = "st,w25q32"; + spi-max-frequency = <50000000>; + reg = <0>; + }; +}; + +&cp1_usb3_0 { + /* CPS Lane 2 - CON7 */ + usb-phy = <&usb3h0_phy>; + status = "okay"; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi new file mode 100644 index 0000000..784ef3f --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for the Armada 8040 SoC, made of an AP806 Quad and + * two CP110. + */ + +#include "armada-ap806-quad.dtsi" +#include "armada-80x0.dtsi" + +/ { + model = "Marvell Armada 8040"; + compatible = "marvell,armada8040", "marvell,armada-ap806-quad", + "marvell,armada-ap806"; +}; + +/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock + * in CP master is not connected (by package) to the oscillator. So + * disable it. However, the RTC clock in CP slave is connected to the + * oscillator so this one is let enabled. + */ +&cp0_rtc { + status = "disabled"; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi new file mode 100644 index 0000000..81967e2 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2017 Marvell Technology Group Ltd. + * + * Device Tree file for the Armada 80x0 SoC family + */ + +/ { + aliases { + gpio1 = &cp1_gpio1; + gpio2 = &cp0_gpio2; + spi1 = &cp0_spi0; + spi2 = &cp0_spi1; + spi3 = &cp1_spi0; + spi4 = &cp1_spi1; + }; +}; + +/* + * Instantiate the master CP110 + */ +#define CP110_NAME cp0 +#define CP110_BASE f2000000 +#define CP110_PCIE_IO_BASE 0xf9000000 +#define CP110_PCIE_MEM_BASE 0xf6000000 +#define CP110_PCIE0_BASE f2600000 +#define CP110_PCIE1_BASE f2620000 +#define CP110_PCIE2_BASE f2640000 + +#include "armada-cp110.dtsi" + +#undef CP110_NAME +#undef CP110_BASE +#undef CP110_PCIE_IO_BASE +#undef CP110_PCIE_MEM_BASE +#undef CP110_PCIE0_BASE +#undef CP110_PCIE1_BASE +#undef CP110_PCIE2_BASE + +/* + * Instantiate the slave CP110 + */ +#define CP110_NAME cp1 +#define CP110_BASE f4000000 +#define CP110_PCIE_IO_BASE 0xfd000000 +#define CP110_PCIE_MEM_BASE 0xfa000000 +#define CP110_PCIE0_BASE f4600000 +#define CP110_PCIE1_BASE f4620000 +#define CP110_PCIE2_BASE f4640000 + +#include "armada-cp110.dtsi" + +#undef CP110_NAME +#undef CP110_BASE +#undef CP110_PCIE_IO_BASE +#undef CP110_PCIE_MEM_BASE +#undef CP110_PCIE0_BASE +#undef CP110_PCIE1_BASE +#undef CP110_PCIE2_BASE + +/* The 80x0 has two CP blocks, but uses only one block from each. */ +&cp1_gpio1 { + status = "okay"; +}; + +&cp0_gpio2 { + status = "okay"; +}; + +&cp0_syscon0 { + cp0_pinctrl: pinctrl { + compatible = "marvell,armada-8k-cpm-pinctrl"; + }; +}; + +&cp1_syscon0 { + cp1_pinctrl: pinctrl { + compatible = "marvell,armada-8k-cps-pinctrl"; + + nand_pins: nand-pins { + marvell,pins = + "mpp0", "mpp1", "mpp2", "mpp3", + "mpp4", "mpp5", "mpp6", "mpp7", + "mpp8", "mpp9", "mpp10", "mpp11", + "mpp15", "mpp16", "mpp17", "mpp18", + "mpp19", "mpp20", "mpp21", "mpp22", + "mpp23", "mpp24", "mpp25", "mpp26", + "mpp27"; + marvell,function = "dev"; + }; + + nand_rb: nand-rb { + marvell,pins = "mpp13", "mpp12"; + marvell,function = "nf"; + }; + }; +}; + +&cp1_crypto { + /* + * The cryptographic engine found on the cp110 + * master is enabled by default at the SoC + * level. Because it is not possible as of now + * to enable two cryptographic engines in + * parallel, disable this one by default. + */ + status = "disabled"; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi new file mode 100644 index 0000000..5985843 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for Marvell Armada AP806. + */ + +#include "armada-ap806.dtsi" + +/ { + model = "Marvell Armada AP806 Dual"; + compatible = "marvell,armada-ap806-dual", "marvell,armada-ap806"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x000>; + enable-method = "psci"; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x001>; + enable-method = "psci"; + }; + }; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi new file mode 100644 index 0000000..bae0ed9 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for Marvell Armada AP806. + */ + +#include "armada-ap806.dtsi" + +/ { + model = "Marvell Armada AP806 Quad"; + compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x000>; + enable-method = "psci"; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x001>; + enable-method = "psci"; + }; + cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x100>; + enable-method = "psci"; + }; + cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x101>; + enable-method = "psci"; + }; + }; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi new file mode 100644 index 0000000..66124bf --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi @@ -0,0 +1,264 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for Marvell Armada AP806. + */ + +#define IRQ_TYPE_LEVEL_HIGH (1 << 2) +#define IRQ_TYPE_LEVEL_LOW (1 << 3) + +#define GIC_SPI 0 +#define GIC_PPI 1 + +#define GIC_CPU_MASK_RAW(x) ((x) << 8) +#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1) + +/dts-v1/; + +/ { + model = "Marvell Armada AP806"; + compatible = "marvell,armada-ap806"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + gpio0 = &ap_gpio; + spi0 = &spi0; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + ap806 { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + config-space@f0000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x0 0x0 0xf0000000 0x1000000>; + + gic: interrupt-controller@210000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-controller; + interrupts = ; + reg = <0x210000 0x10000>, + <0x220000 0x20000>, + <0x240000 0x20000>, + <0x260000 0x20000>; + + gic_v2m0: v2m@280000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x280000 0x1000>; + arm,msi-base-spi = <160>; + arm,msi-num-spis = <32>; + }; + gic_v2m1: v2m@290000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x290000 0x1000>; + arm,msi-base-spi = <192>; + arm,msi-num-spis = <32>; + }; + gic_v2m2: v2m@2a0000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x2a0000 0x1000>; + arm,msi-base-spi = <224>; + arm,msi-num-spis = <32>; + }; + gic_v2m3: v2m@2b0000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x2b0000 0x1000>; + arm,msi-base-spi = <256>; + arm,msi-num-spis = <32>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,cortex-a72-pmu"; + interrupt-parent = <&pic>; + interrupts = <17>; + }; + + odmi: odmi@300000 { + compatible = "marvell,odmi-controller"; + interrupt-controller; + msi-controller; + marvell,odmi-frames = <4>; + reg = <0x300000 0x4000>, + <0x304000 0x4000>, + <0x308000 0x4000>, + <0x30C000 0x4000>; + marvell,spi-base = <128>, <136>, <144>, <152>; + }; + + gicp: gicp@3f0040 { + compatible = "marvell,ap806-gicp"; + reg = <0x3f0040 0x10>; + marvell,spi-ranges = <64 64>, <288 64>; + msi-controller; + }; + + pic: interrupt-controller@3f0100 { + compatible = "marvell,armada-8k-pic"; + reg = <0x3f0100 0x10>; + #interrupt-cells = <1>; + interrupt-controller; + interrupts = ; + }; + + xor@400000 { + compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; + reg = <0x400000 0x1000>, + <0x410000 0x1000>; + msi-parent = <&gic_v2m0>; + clocks = <&ap_clk 3>; + dma-coherent; + }; + + xor@420000 { + compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; + reg = <0x420000 0x1000>, + <0x430000 0x1000>; + msi-parent = <&gic_v2m0>; + clocks = <&ap_clk 3>; + dma-coherent; + }; + + xor@440000 { + compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; + reg = <0x440000 0x1000>, + <0x450000 0x1000>; + msi-parent = <&gic_v2m0>; + clocks = <&ap_clk 3>; + dma-coherent; + }; + + xor@460000 { + compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; + reg = <0x460000 0x1000>, + <0x470000 0x1000>; + msi-parent = <&gic_v2m0>; + clocks = <&ap_clk 3>; + dma-coherent; + }; + + spi0: spi@510600 { + compatible = "marvell,armada-380-spi"; + reg = <0x510600 0x50>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&ap_clk 3>; + status = "disabled"; + }; + + i2c0: i2c@511000 { + compatible = "marvell,mv78230-i2c"; + reg = <0x511000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + timeout-ms = <1000>; + clocks = <&ap_clk 3>; + status = "disabled"; + }; + + uart0: serial@512000 { + compatible = "snps,dw-apb-uart"; + reg = <0x512000 0x100>; + reg-shift = <2>; + interrupts = ; + reg-io-width = <1>; + clocks = <&ap_clk 3>; + status = "disabled"; + }; + + uart1: serial@512100 { + compatible = "snps,dw-apb-uart"; + reg = <0x512100 0x100>; + reg-shift = <2>; + interrupts = ; + reg-io-width = <1>; + clocks = <&ap_clk 3>; + status = "disabled"; + + }; + + watchdog: watchdog@610000 { + compatible = "arm,sbsa-gwdt"; + reg = <0x610000 0x1000>, <0x600000 0x1000>; + interrupts = ; + }; + + ap_sdhci0: sdhci@6e0000 { + compatible = "marvell,armada-ap806-sdhci"; + reg = <0x6e0000 0x300>; + interrupts = ; + clock-names = "core"; + clocks = <&ap_clk 4>; + dma-coherent; + marvell,xenon-phy-slow-mode; + status = "disabled"; + }; + + ap_syscon: system-controller@6f4000 { + compatible = "syscon", "simple-mfd"; + reg = <0x6f4000 0x2000>; + + ap_clk: clock { + compatible = "marvell,ap806-clock"; + #clock-cells = <1>; + }; + + ap_pinctrl: pinctrl { + compatible = "marvell,ap806-pinctrl"; + + uart0_pins: uart0-pins { + marvell,pins = "mpp11", "mpp19"; + marvell,function = "uart0"; + }; + }; + + ap_gpio: gpio@1040 { + compatible = "marvell,armada-8k-gpio"; + offset = <0x1040>; + ngpios = <20>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&ap_pinctrl 0 0 20>; + }; + }; + + ap_thermal: thermal@6f808c { + compatible = "marvell,armada-ap806-thermal"; + reg = <0x6f808c 0x4>, + <0x6f8084 0x8>; + }; + }; + }; +}; diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi new file mode 100644 index 0000000..8b610fd --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + */ + +/* Common definitions used by Armada 7K/8K DTs */ +#define PASTER(x, y) x ## y +#define EVALUATOR(x, y) PASTER(x, y) +#define CP110_LABEL(name) EVALUATOR(CP110_NAME, EVALUATOR(_, name)) +#define ADDRESSIFY(addr) EVALUATOR(0x, addr) diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi new file mode 100644 index 0000000..b9504a3 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi @@ -0,0 +1,503 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for Marvell Armada CP110. + */ + +#include "armada-common.dtsi" + +#define ICU_GRP_NSR 0x0 +#define ICU_GRP_SR 0x1 +#define ICU_GRP_SEI 0x4 +#define ICU_GRP_REI 0x5 + +#define CP110_PCIEx_IO_BASE(iface) (CP110_PCIE_IO_BASE + (iface * 0x10000)) +#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIE_MEM_BASE + (iface * 0x1000000)) +#define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) + 0xf00000) + +/ { + /* + * The contents of the node are defined below, in order to + * save one indentation level + */ + CP110_NAME: CP110_NAME { }; +}; + +&CP110_NAME { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + interrupt-parent = <&CP110_LABEL(icu)>; + ranges; + + config-space@CP110_BASE { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>; + + CP110_LABEL(ethernet): ethernet@0 { + compatible = "marvell,armada-7k-pp22"; + reg = <0x0 0x100000>, <0x129000 0xb000>; + clocks = <&CP110_LABEL(clk) 1 3>, <&CP110_LABEL(clk) 1 9>, + <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>, + <&CP110_LABEL(clk) 1 18>; + clock-names = "pp_clk", "gop_clk", + "mg_clk", "mg_core_clk", "axi_clk"; + marvell,system-controller = <&CP110_LABEL(syscon0)>; + status = "disabled"; + dma-coherent; + + CP110_LABEL(eth0): eth0 { + interrupts = , + , + , + , + , + ; + interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", + "tx-cpu3", "rx-shared", "link"; + port-id = <0>; + gop-port-id = <0>; + status = "disabled"; + }; + + CP110_LABEL(eth1): eth1 { + interrupts = , + , + , + , + , + ; + interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", + "tx-cpu3", "rx-shared", "link"; + port-id = <1>; + gop-port-id = <2>; + status = "disabled"; + }; + + CP110_LABEL(eth2): eth2 { + interrupts = , + , + , + , + , + ; + interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", + "tx-cpu3", "rx-shared", "link"; + port-id = <2>; + gop-port-id = <3>; + status = "disabled"; + }; + }; + + CP110_LABEL(comphy): phy@120000 { + compatible = "marvell,comphy-cp110"; + reg = <0x120000 0x6000>; + marvell,system-controller = <&CP110_LABEL(syscon0)>; + #address-cells = <1>; + #size-cells = <0>; + + CP110_LABEL(comphy0): phy@0 { + reg = <0>; + #phy-cells = <1>; + }; + + CP110_LABEL(comphy1): phy@1 { + reg = <1>; + #phy-cells = <1>; + }; + + CP110_LABEL(comphy2): phy@2 { + reg = <2>; + #phy-cells = <1>; + }; + + CP110_LABEL(comphy3): phy@3 { + reg = <3>; + #phy-cells = <1>; + }; + + CP110_LABEL(comphy4): phy@4 { + reg = <4>; + #phy-cells = <1>; + }; + + CP110_LABEL(comphy5): phy@5 { + reg = <5>; + #phy-cells = <1>; + }; + }; + + CP110_LABEL(mdio): mdio@12a200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "marvell,orion-mdio"; + reg = <0x12a200 0x10>; + clocks = <&CP110_LABEL(clk) 1 9>, <&CP110_LABEL(clk) 1 5>, + <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>; + status = "disabled"; + }; + + CP110_LABEL(xmdio): mdio@12a600 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "marvell,xmdio"; + reg = <0x12a600 0x10>; + clocks = <&CP110_LABEL(clk) 1 5>, + <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>; + status = "disabled"; + }; + + CP110_LABEL(icu): interrupt-controller@1e0000 { + compatible = "marvell,cp110-icu"; + reg = <0x1e0000 0x440>; + #interrupt-cells = <3>; + interrupt-controller; + msi-parent = <&gicp>; + }; + + CP110_LABEL(rtc): rtc@284000 { + compatible = "marvell,armada-8k-rtc"; + reg = <0x284000 0x20>, <0x284080 0x24>; + reg-names = "rtc", "rtc-soc"; + interrupts = ; + }; + + CP110_LABEL(thermal): thermal@400078 { + compatible = "marvell,armada-cp110-thermal"; + reg = <0x400078 0x4>, + <0x400070 0x8>; + }; + + CP110_LABEL(syscon0): system-controller@440000 { + compatible = "syscon", "simple-mfd"; + reg = <0x440000 0x2000>; + + CP110_LABEL(clk): clock { + compatible = "marvell,cp110-clock"; + #clock-cells = <2>; + }; + + CP110_LABEL(gpio1): gpio@100 { + compatible = "marvell,armada-8k-gpio"; + offset = <0x100>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>; + interrupt-controller; + interrupts = , + , + , + ; + status = "disabled"; + }; + + CP110_LABEL(gpio2): gpio@140 { + compatible = "marvell,armada-8k-gpio"; + offset = <0x140>; + ngpios = <31>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&CP110_LABEL(pinctrl) 0 32 31>; + interrupt-controller; + interrupts = , + , + , + ; + status = "disabled"; + }; + }; + + CP110_LABEL(usb3_0): usb3@500000 { + compatible = "marvell,armada-8k-xhci", + "generic-xhci"; + reg = <0x500000 0x4000>; + dma-coherent; + interrupts = ; + clock-names = "core", "reg"; + clocks = <&CP110_LABEL(clk) 1 22>, + <&CP110_LABEL(clk) 1 16>; + status = "disabled"; + }; + + CP110_LABEL(usb3_1): usb3@510000 { + compatible = "marvell,armada-8k-xhci", + "generic-xhci"; + reg = <0x510000 0x4000>; + dma-coherent; + interrupts = ; + clock-names = "core", "reg"; + clocks = <&CP110_LABEL(clk) 1 23>, + <&CP110_LABEL(clk) 1 16>; + status = "disabled"; + }; + + CP110_LABEL(sata0): sata@540000 { + compatible = "marvell,armada-8k-ahci", + "generic-ahci"; + reg = <0x540000 0x30000>; + dma-coherent; + interrupts = ; + clocks = <&CP110_LABEL(clk) 1 15>, + <&CP110_LABEL(clk) 1 16>; + status = "disabled"; + }; + + CP110_LABEL(xor0): xor@6a0000 { + compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; + reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>; + dma-coherent; + msi-parent = <&gic_v2m0>; + clock-names = "core", "reg"; + clocks = <&CP110_LABEL(clk) 1 8>, + <&CP110_LABEL(clk) 1 14>; + }; + + CP110_LABEL(xor1): xor@6c0000 { + compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; + reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>; + dma-coherent; + msi-parent = <&gic_v2m0>; + clock-names = "core", "reg"; + clocks = <&CP110_LABEL(clk) 1 7>, + <&CP110_LABEL(clk) 1 14>; + }; + + CP110_LABEL(spi0): spi@700600 { + compatible = "marvell,armada-380-spi"; + reg = <0x700600 0x50>; + #address-cells = <0x1>; + #size-cells = <0x0>; + clock-names = "core", "axi"; + clocks = <&CP110_LABEL(clk) 1 21>, + <&CP110_LABEL(clk) 1 17>; + status = "disabled"; + }; + + CP110_LABEL(spi1): spi@700680 { + compatible = "marvell,armada-380-spi"; + reg = <0x700680 0x50>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "core", "axi"; + clocks = <&CP110_LABEL(clk) 1 21>, + <&CP110_LABEL(clk) 1 17>; + status = "disabled"; + }; + + CP110_LABEL(i2c0): i2c@701000 { + compatible = "marvell,mv78230-i2c"; + reg = <0x701000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "core", "reg"; + clocks = <&CP110_LABEL(clk) 1 21>, + <&CP110_LABEL(clk) 1 17>; + status = "disabled"; + }; + + CP110_LABEL(i2c1): i2c@701100 { + compatible = "marvell,mv78230-i2c"; + reg = <0x701100 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "core", "reg"; + clocks = <&CP110_LABEL(clk) 1 21>, + <&CP110_LABEL(clk) 1 17>; + status = "disabled"; + }; + + CP110_LABEL(uart0): serial@702000 { + compatible = "snps,dw-apb-uart"; + reg = <0x702000 0x100>; + reg-shift = <2>; + interrupts = ; + reg-io-width = <1>; + clock-names = "baudclk", "apb_pclk"; + clocks = <&CP110_LABEL(clk) 1 21>, + <&CP110_LABEL(clk) 1 17>; + status = "disabled"; + }; + + CP110_LABEL(uart1): serial@702100 { + compatible = "snps,dw-apb-uart"; + reg = <0x702100 0x100>; + reg-shift = <2>; + interrupts = ; + reg-io-width = <1>; + clock-names = "baudclk", "apb_pclk"; + clocks = <&CP110_LABEL(clk) 1 21>, + <&CP110_LABEL(clk) 1 17>; + status = "disabled"; + }; + + CP110_LABEL(uart2): serial@702200 { + compatible = "snps,dw-apb-uart"; + reg = <0x702200 0x100>; + reg-shift = <2>; + interrupts = ; + reg-io-width = <1>; + clock-names = "baudclk", "apb_pclk"; + clocks = <&CP110_LABEL(clk) 1 21>, + <&CP110_LABEL(clk) 1 17>; + status = "disabled"; + }; + + CP110_LABEL(uart3): serial@702300 { + compatible = "snps,dw-apb-uart"; + reg = <0x702300 0x100>; + reg-shift = <2>; + interrupts = ; + reg-io-width = <1>; + clock-names = "baudclk", "apb_pclk"; + clocks = <&CP110_LABEL(clk) 1 21>, + <&CP110_LABEL(clk) 1 17>; + status = "disabled"; + }; + + CP110_LABEL(nand_controller): nand@720000 { + /* + * Due to the limitation of the pins available + * this controller is only usable on the CPM + * for A7K and on the CPS for A8K. + */ + compatible = "marvell,armada-8k-nand-controller", + "marvell,armada370-nand-controller"; + reg = <0x720000 0x54>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "core", "reg"; + clocks = <&CP110_LABEL(clk) 1 2>, + <&CP110_LABEL(clk) 1 17>; + marvell,system-controller = <&CP110_LABEL(syscon0)>; + status = "disabled"; + }; + + CP110_LABEL(trng): trng@760000 { + compatible = "marvell,armada-8k-rng", + "inside-secure,safexcel-eip76"; + reg = <0x760000 0x7d>; + interrupts = ; + clock-names = "core", "reg"; + clocks = <&CP110_LABEL(clk) 1 25>, + <&CP110_LABEL(clk) 1 17>; + status = "okay"; + }; + + CP110_LABEL(sdhci0): sdhci@780000 { + compatible = "marvell,armada-cp110-sdhci"; + reg = <0x780000 0x300>; + interrupts = ; + clock-names = "core", "axi"; + clocks = <&CP110_LABEL(clk) 1 4>, <&CP110_LABEL(clk) 1 18>; + dma-coherent; + status = "disabled"; + }; + + CP110_LABEL(crypto): crypto@800000 { + compatible = "inside-secure,safexcel-eip197"; + reg = <0x800000 0x200000>; + interrupts = , + , + , + , + , + ; + interrupt-names = "mem", "ring0", "ring1", + "ring2", "ring3", "eip"; + clock-names = "core", "reg"; + clocks = <&CP110_LABEL(clk) 1 26>, + <&CP110_LABEL(clk) 1 17>; + dma-coherent; + }; + }; + + CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE { + compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; + reg = <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>, + <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>; + reg-names = "ctrl", "config"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + dma-coherent; + msi-parent = <&gic_v2m0>; + + bus-range = <0 0xff>; + ranges = + /* downstream I/O */ + <0x81000000 0 CP110_PCIEx_IO_BASE(0) 0 CP110_PCIEx_IO_BASE(0) 0 0x10000 + /* non-prefetchable memory */ + 0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BASE(0) 0 0xf00000>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; + num-lanes = <1>; + clock-names = "core", "reg"; + clocks = <&CP110_LABEL(clk) 1 13>, <&CP110_LABEL(clk) 1 14>; + status = "disabled"; + }; + + CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE { + compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; + reg = <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>, + <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>; + reg-names = "ctrl", "config"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + dma-coherent; + msi-parent = <&gic_v2m0>; + + bus-range = <0 0xff>; + ranges = + /* downstream I/O */ + <0x81000000 0 CP110_PCIEx_IO_BASE(1) 0 CP110_PCIEx_IO_BASE(1) 0 0x10000 + /* non-prefetchable memory */ + 0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BASE(1) 0 0xf00000>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; + + num-lanes = <1>; + clock-names = "core", "reg"; + clocks = <&CP110_LABEL(clk) 1 11>, <&CP110_LABEL(clk) 1 14>; + status = "disabled"; + }; + + CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE { + compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; + reg = <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>, + <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>; + reg-names = "ctrl", "config"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + dma-coherent; + msi-parent = <&gic_v2m0>; + + bus-range = <0 0xff>; + ranges = + /* downstream I/O */ + <0x81000000 0 CP110_PCIEx_IO_BASE(2) 0 CP110_PCIEx_IO_BASE(2) 0 0x10000 + /* non-prefetchable memory */ + 0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BASE(2) 0 0xf00000>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; + + num-lanes = <1>; + clock-names = "core", "reg"; + clocks = <&CP110_LABEL(clk) 1 12>, <&CP110_LABEL(clk) 1 14>; + status = "disabled"; + }; +}; -- 2.7.4