* [platforms: PATCH v2 1/9] Marvell/Armada7k8k: Import device tree
2018-08-07 8:58 [platforms: PATCH v2 0/9] Armada7k8k DT/ACPI support Marcin Wojtas
@ 2018-08-07 8:58 ` Marcin Wojtas
2018-08-07 8:58 ` [platforms: PATCH v2 2/9] Marvell/Armada7k8k: Enable including additional DXE FV components Marcin Wojtas
` (8 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Marcin Wojtas @ 2018-08-07 8:58 UTC (permalink / raw)
To: edk2-devel; +Cc: leif.lindholm, ard.biesheuvel, nadavh, mw, jsd, jaz
Add a device tree description of the Armada7k8k SoCs,
whose sources are aligned to the Linux v4.18-rc7.
Enablement for each board will be done in the follow-up
commits.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Silicon/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi | 16 +
Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts | 267 +++++++++++
Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi | 16 +
Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi | 64 +++
Silicon/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi | 26 +
Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts | 336 +++++++++++++
Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts | 371 +++++++++++++++
Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi | 25 +
Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi | 108 +++++
Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi | 31 ++
Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi | 43 ++
Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi | 264 ++++++++++
Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi | 10 +
Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi | 503 ++++++++++++++++++++
14 files changed, 2080 insertions(+)
create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi
create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts
create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi
create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi
create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi
create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts
create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts
create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi
create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi
create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi
create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi
create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi
create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi
create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi
new file mode 100644
index 0000000..e2edc26
--- /dev/null
+++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ *
+ * Device Tree file for the Armada 7020 SoC, made of an AP806 Dual and
+ * one CP110.
+ */
+
+#include "armada-ap806-dual.dtsi"
+#include "armada-70x0.dtsi"
+
+/ {
+ model = "Marvell Armada 7020";
+ compatible = "marvell,armada7020", "marvell,armada-ap806-dual",
+ "marvell,armada-ap806";
+};
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts
new file mode 100644
index 0000000..6b28bbe
--- /dev/null
+++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts
@@ -0,0 +1,267 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ *
+ * Device Tree file for Marvell Armada 7040 Development board platform
+ */
+
+#include "armada-7040.dtsi"
+
+#define GPIO_ACTIVE_HIGH 0
+#define GPIO_ACTIVE_LOW 1
+
+/ {
+ model = "Marvell Armada 7040 DB board";
+ compatible = "marvell,armada7040-db", "marvell,armada7040",
+ "marvell,armada-ap806-quad", "marvell,armada-ap806";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ aliases {
+ ethernet0 = &cp0_eth0;
+ ethernet1 = &cp0_eth1;
+ ethernet2 = &cp0_eth2;
+ };
+
+ cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb3h0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb3h1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ cp0_usb3_0_phy: cp0-usb3-0-phy {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cp0_reg_usb3_0_vbus>;
+ };
+
+ cp0_usb3_1_phy: cp0-usb3-1-phy {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cp0_reg_usb3_1_vbus>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+&spi0 {
+ status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0 0x200000>;
+ };
+ partition@400000 {
+ label = "Filesystem";
+ reg = <0x200000 0xce0000>;
+ };
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+ pinctrl-0 = <&uart0_pins>;
+ pinctrl-names = "default";
+};
+
+
+&cp0_pcie2 {
+ status = "okay";
+};
+
+&cp0_i2c0 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ expander0: pca9555@21 {
+ compatible = "nxp,pca9555";
+ pinctrl-names = "default";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x21>;
+ /*
+ * IO0_0: USB3_PWR_EN0 IO1_0: USB_3_1_Dev_Detect
+ * IO0_1: USB3_PWR_EN1 IO1_1: USB2_1_current_limit
+ * IO0_2: DDR3_4_Detect IO1_2: Hcon_IO_RstN
+ * IO0_3: USB2_DEVICE_DETECT
+ * IO0_4: GPIO_0 IO1_4: SD_Status
+ * IO0_5: GPIO_1 IO1_5: LDO_5V_Enable
+ * IO0_6: IHB_5V_Enable IO1_6: PWR_EN_eMMC
+ * IO0_7: IO1_7: SDIO_Vcntrl
+ */
+ };
+};
+
+&cp0_nand_controller {
+ /*
+ * SPI on CPM and NAND have common pins on this board. We can
+ * use only one at a time. To enable the NAND (which will
+ * disable the SPI), the "status = "okay";" line have to be
+ * added here.
+ */
+ pinctrl-0 = <&nand_pins>, <&nand_rb>;
+ pinctrl-names = "default";
+
+ nand@0 {
+ reg = <0>;
+ label = "pxa3xx_nand-0";
+ nand-rb = <0>;
+ nand-on-flash-bbt;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0 0x200000>;
+ };
+
+ partition@200000 {
+ label = "Linux";
+ reg = <0x200000 0xe00000>;
+ };
+
+ partition@1000000 {
+ label = "Filesystem";
+ reg = <0x1000000 0x3f000000>;
+ };
+
+ };
+ };
+};
+
+&cp0_spi1 {
+ status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-max-frequency = <20000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0x0 0x200000>;
+ };
+
+ partition@400000 {
+ label = "Filesystem";
+ reg = <0x200000 0xe00000>;
+ };
+ };
+ };
+};
+
+&cp0_sata0 {
+ status = "okay";
+};
+
+&cp0_usb3_0 {
+ usb-phy = <&cp0_usb3_0_phy>;
+ status = "okay";
+};
+
+&cp0_usb3_1 {
+ usb-phy = <&cp0_usb3_1_phy>;
+ status = "okay";
+};
+
+&ap_sdhci0 {
+ status = "okay";
+ bus-width = <4>;
+ no-1-8-v;
+ non-removable;
+};
+
+&cp0_sdhci0 {
+ status = "okay";
+ bus-width = <4>;
+ no-1-8-v;
+ cd-gpios = <&expander0 12 GPIO_ACTIVE_LOW>;
+};
+
+&cp0_mdio {
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&cp0_ethernet {
+ status = "okay";
+};
+
+&cp0_eth0 {
+ status = "okay";
+ /* Network PHY */
+ phy-mode = "10gbase-kr";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp0_comphy2 0>;
+
+ fixed-link {
+ speed = <10000>;
+ full-duplex;
+ };
+};
+
+&cp0_eth1 {
+ status = "okay";
+ /* Network PHY */
+ phy = <&phy0>;
+ phy-mode = "sgmii";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp0_comphy0 1>;
+};
+
+&cp0_eth2 {
+ status = "okay";
+ phy = <&phy1>;
+ phy-mode = "rgmii-id";
+};
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi
new file mode 100644
index 0000000..03109b2
--- /dev/null
+++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ *
+ * Device Tree file for the Armada 7040 SoC, made of an AP806 Quad and
+ * one CP110.
+ */
+
+#include "armada-ap806-quad.dtsi"
+#include "armada-70x0.dtsi"
+
+/ {
+ model = "Marvell Armada 7040";
+ compatible = "marvell,armada7040", "marvell,armada-ap806-quad",
+ "marvell,armada-ap806";
+};
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi
new file mode 100644
index 0000000..78f9d87
--- /dev/null
+++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2017 Marvell Technology Group Ltd.
+ *
+ * Device Tree file for the Armada 70x0 SoC
+ */
+
+/ {
+ aliases {
+ gpio1 = &cp0_gpio1;
+ gpio2 = &cp0_gpio2;
+ spi1 = &cp0_spi0;
+ spi2 = &cp0_spi1;
+ };
+};
+
+/*
+ * Instantiate the CP110
+ */
+#define CP110_NAME cp0
+#define CP110_BASE f2000000
+#define CP110_PCIE_IO_BASE 0xf9000000
+#define CP110_PCIE_MEM_BASE 0xf6000000
+#define CP110_PCIE0_BASE f2600000
+#define CP110_PCIE1_BASE f2620000
+#define CP110_PCIE2_BASE f2640000
+
+#include "armada-cp110.dtsi"
+
+#undef CP110_NAME
+#undef CP110_BASE
+#undef CP110_PCIE_IO_BASE
+#undef CP110_PCIE_MEM_BASE
+#undef CP110_PCIE0_BASE
+#undef CP110_PCIE1_BASE
+#undef CP110_PCIE2_BASE
+
+&cp0_gpio1 {
+ status = "okay";
+};
+
+&cp0_gpio2 {
+ status = "okay";
+};
+
+&cp0_syscon0 {
+ cp0_pinctrl: pinctrl {
+ compatible = "marvell,armada-7k-pinctrl";
+
+ nand_pins: nand-pins {
+ marvell,pins =
+ "mpp15", "mpp16", "mpp17", "mpp18",
+ "mpp19", "mpp20", "mpp21", "mpp22",
+ "mpp23", "mpp24", "mpp25", "mpp26",
+ "mpp27";
+ marvell,function = "dev";
+ };
+
+ nand_rb: nand-rb {
+ marvell,pins = "mpp13";
+ marvell,function = "nf";
+ };
+ };
+};
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi
new file mode 100644
index 0000000..5d76345
--- /dev/null
+++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ *
+ * Device Tree file for the Armada 8020 SoC, made of an AP806 Dual and
+ * two CP110.
+ */
+
+#include "armada-ap806-dual.dtsi"
+#include "armada-80x0.dtsi"
+
+/ {
+ model = "Marvell Armada 8020";
+ compatible = "marvell,armada8020", "marvell,armada-ap806-dual",
+ "marvell,armada-ap806";
+};
+
+/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock
+ * in CP master is not connected (by package) to the oscillator. So
+ * disable it. However, the RTC clock in CP slave is connected to the
+ * oscillator so this one is let enabled.
+ */
+
+&cp0_rtc {
+ status = "disabled";
+};
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts
new file mode 100644
index 0000000..7518029
--- /dev/null
+++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts
@@ -0,0 +1,336 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ *
+ * Device Tree file for Marvell Armada 8040 Development board platform
+ */
+
+#include "armada-8040.dtsi"
+
+#define GPIO_ACTIVE_HIGH 0
+#define GPIO_ACTIVE_LOW 1
+
+/ {
+ model = "Marvell Armada 8040 DB board";
+ compatible = "marvell,armada8040-db", "marvell,armada8040",
+ "marvell,armada-ap806-quad", "marvell,armada-ap806";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ aliases {
+ ethernet0 = &cp0_eth0;
+ ethernet1 = &cp0_eth2;
+ ethernet2 = &cp1_eth0;
+ ethernet3 = &cp1_eth1;
+ };
+
+ cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "cp0-usb3h0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "cp0-usb3h1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ cp0_usb3_0_phy: cp0-usb3-0-phy {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cp0_reg_usb3_0_vbus>;
+ };
+
+ cp0_usb3_1_phy: cp0-usb3-1-phy {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cp0_reg_usb3_1_vbus>;
+ };
+
+ cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "cp1-usb3h0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&expander1 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ cp1_usb3_0_phy: cp1-usb3-0-phy {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cp1_reg_usb3_0_vbus>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+&spi0 {
+ status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0 0x200000>;
+ };
+ partition@400000 {
+ label = "Filesystem";
+ reg = <0x200000 0xce0000>;
+ };
+ };
+ };
+};
+
+/* Accessible over the mini-USB CON9 connector on the main board */
+&uart0 {
+ status = "okay";
+ pinctrl-0 = <&uart0_pins>;
+ pinctrl-names = "default";
+};
+
+/* CON6 on CP0 expansion */
+&cp0_pcie0 {
+ status = "okay";
+};
+
+/* CON5 on CP0 expansion */
+&cp0_pcie2 {
+ status = "okay";
+};
+
+&cp0_i2c0 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ /* U31 */
+ expander0: pca9555@21 {
+ compatible = "nxp,pca9555";
+ pinctrl-names = "default";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x21>;
+ };
+
+ /* U25 */
+ expander1: pca9555@25 {
+ compatible = "nxp,pca9555";
+ pinctrl-names = "default";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x25>;
+ };
+
+};
+
+/* CON4 on CP0 expansion */
+&cp0_sata0 {
+ status = "okay";
+};
+
+/* CON9 on CP0 expansion */
+&cp0_usb3_0 {
+ usb-phy = <&cp0_usb3_0_phy>;
+ status = "okay";
+};
+
+/* CON10 on CP0 expansion */
+&cp0_usb3_1 {
+ usb-phy = <&cp0_usb3_1_phy>;
+ status = "okay";
+};
+
+&cp0_mdio {
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&cp0_ethernet {
+ status = "okay";
+};
+
+&cp0_eth0 {
+ status = "okay";
+ phy-mode = "10gbase-kr";
+
+ fixed-link {
+ speed = <10000>;
+ full-duplex;
+ };
+};
+
+&cp0_eth2 {
+ status = "okay";
+ phy = <&phy1>;
+ phy-mode = "rgmii-id";
+};
+
+/* CON6 on CP1 expansion */
+&cp1_pcie0 {
+ status = "okay";
+};
+
+/* CON7 on CP1 expansion */
+&cp1_pcie1 {
+ status = "okay";
+};
+
+/* CON5 on CP1 expansion */
+&cp1_pcie2 {
+ status = "okay";
+};
+
+&cp1_i2c0 {
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+&cp1_spi1 {
+ status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-max-frequency = <20000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "Boot";
+ reg = <0x0 0x200000>;
+ };
+ partition@200000 {
+ label = "Filesystem";
+ reg = <0x200000 0xd00000>;
+ };
+ partition@f00000 {
+ label = "Boot_2nd";
+ reg = <0xf00000 0x100000>;
+ };
+ };
+ };
+};
+
+/*
+ * Proper NAND usage will require DPR-76 to be in position 1-2, which disables
+ * MDIO signal of CP1.
+ */
+&cp1_nand_controller {
+ pinctrl-0 = <&nand_pins>, <&nand_rb>;
+ pinctrl-names = "default";
+
+ nand@0 {
+ reg = <0>;
+ nand-rb = <0>;
+ nand-on-flash-bbt;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0 0x200000>;
+ };
+ partition@200000 {
+ label = "Linux";
+ reg = <0x200000 0xe00000>;
+ };
+ partition@1000000 {
+ label = "Filesystem";
+ reg = <0x1000000 0x3f000000>;
+ };
+ };
+ };
+};
+
+/* CON4 on CP1 expansion */
+&cp1_sata0 {
+ status = "okay";
+};
+
+/* CON9 on CP1 expansion */
+&cp1_usb3_0 {
+ usb-phy = <&cp1_usb3_0_phy>;
+ status = "okay";
+};
+
+/* CON10 on CP1 expansion */
+&cp1_usb3_1 {
+ status = "okay";
+};
+
+&cp1_mdio {
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+&cp1_ethernet {
+ status = "okay";
+};
+
+&cp1_eth0 {
+ status = "okay";
+ phy-mode = "10gbase-kr";
+
+ fixed-link {
+ speed = <10000>;
+ full-duplex;
+ };
+};
+
+&cp1_eth1 {
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+};
+
+&ap_sdhci0 {
+ status = "okay";
+ bus-width = <4>;
+ non-removable;
+};
+
+&cp0_sdhci0 {
+ status = "okay";
+ bus-width = <8>;
+ non-removable;
+};
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts
new file mode 100644
index 0000000..0e20e70
--- /dev/null
+++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts
@@ -0,0 +1,371 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ *
+ * Device Tree file for MACCHIATOBin Armada 8040 community board platform
+ */
+
+#include "armada-8040.dtsi"
+
+#define GPIO_ACTIVE_HIGH 0
+#define GPIO_ACTIVE_LOW 1
+
+/ {
+ model = "Marvell 8040 MACCHIATOBin";
+ compatible = "marvell,armada8040-mcbin", "marvell,armada8040",
+ "marvell,armada-ap806-quad", "marvell,armada-ap806";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ aliases {
+ ethernet0 = &cp0_eth0;
+ ethernet1 = &cp1_eth0;
+ ethernet2 = &cp1_eth1;
+ ethernet3 = &cp1_eth2;
+ };
+
+ /* Regulator labels correspond with schematics */
+ v_3_3: regulator-3-3v {
+ compatible = "regulator-fixed";
+ regulator-name = "v_3_3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ status = "okay";
+ };
+
+ v_vddo_h: regulator-1-8v {
+ compatible = "regulator-fixed";
+ regulator-name = "v_vddo_h";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ status = "okay";
+ };
+
+ v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_xhci_vbus_pins>;
+ regulator-name = "v_5v0_usb3_hst_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ status = "okay";
+ };
+
+ usb3h0_phy: usb3_phy0 {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&v_5v0_usb3_hst_vbus>;
+ };
+
+ sfp_eth0: sfp-eth0 {
+ /* CON15,16 - CPM lane 4 */
+ compatible = "sff,sfp";
+ i2c-bus = <&sfpp0_i2c>;
+ los-gpio = <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&cp1_gpio1 27 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_sfpp0_pins>;
+ };
+
+ sfp_eth1: sfp-eth1 {
+ /* CON17,18 - CPS lane 4 */
+ compatible = "sff,sfp";
+ i2c-bus = <&sfpp1_i2c>;
+ los-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&cp0_gpio2 30 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_sfpp1_pins &cp0_sfpp1_pins>;
+ };
+
+ sfp_eth3: sfp-eth3 {
+ /* CON3,4 - CPS lane 5 */
+ compatible = "sff,sfp";
+ i2c-bus = <&sfp_1g_i2c>;
+ los-gpio = <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&cp0_gpio2 21 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_sfp_1g_pins &cp1_sfp_1g_pins>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+ pinctrl-0 = <&uart0_pins>;
+ pinctrl-names = "default";
+};
+
+&ap_sdhci0 {
+ bus-width = <8>;
+ /*
+ * Not stable in HS modes - phy needs "more calibration", so add
+ * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes.
+ */
+ marvell,xenon-phy-slow-mode;
+ no-1-8-v;
+ no-sd;
+ no-sdio;
+ non-removable;
+ status = "okay";
+ vqmmc-supply = <&v_vddo_h>;
+};
+
+&cp0_i2c0 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_i2c0_pins>;
+ status = "okay";
+};
+
+&cp0_i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_i2c1_pins>;
+ status = "okay";
+
+ i2c-switch@70 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x70>;
+
+ sfpp0_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ sfpp1_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ sfp_1g_i2c: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ };
+};
+
+/* J25 UART header */
+&cp0_uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_uart1_pins>;
+ status = "okay";
+};
+
+&cp0_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_ge_mdio_pins>;
+ status = "okay";
+
+ ge_phy: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+&cp0_pcie0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_pcie_pins>;
+ num-lanes = <4>;
+ num-viewport = <8>;
+ reset-gpio = <&cp0_gpio1 20 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&cp0_pinctrl {
+ cp0_ge_mdio_pins: ge-mdio-pins {
+ marvell,pins = "mpp32", "mpp34";
+ marvell,function = "ge";
+ };
+ cp0_i2c1_pins: i2c1-pins {
+ marvell,pins = "mpp35", "mpp36";
+ marvell,function = "i2c1";
+ };
+ cp0_i2c0_pins: i2c0-pins {
+ marvell,pins = "mpp37", "mpp38";
+ marvell,function = "i2c0";
+ };
+ cp0_uart1_pins: uart1-pins {
+ marvell,pins = "mpp40", "mpp41";
+ marvell,function = "uart1";
+ };
+ cp0_xhci_vbus_pins: xhci0-vbus-pins {
+ marvell,pins = "mpp47";
+ marvell,function = "gpio";
+ };
+ cp0_sfp_1g_pins: sfp-1g-pins {
+ marvell,pins = "mpp51", "mpp53", "mpp54";
+ marvell,function = "gpio";
+ };
+ cp0_pcie_pins: pcie-pins {
+ marvell,pins = "mpp52";
+ marvell,function = "gpio";
+ };
+ cp0_sdhci_pins: sdhci-pins {
+ marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59",
+ "mpp60", "mpp61";
+ marvell,function = "sdio";
+ };
+ cp0_sfpp1_pins: sfpp1-pins {
+ marvell,pins = "mpp62";
+ marvell,function = "gpio";
+ };
+};
+
+&cp0_xmdio {
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0>;
+ sfp = <&sfp_eth0>;
+ };
+
+ phy8: ethernet-phy@8 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <8>;
+ sfp = <&sfp_eth1>;
+ };
+};
+
+&cp0_ethernet {
+ status = "okay";
+};
+
+&cp0_eth0 {
+ status = "okay";
+ /* Network PHY */
+ phy = <&phy0>;
+ phy-mode = "10gbase-kr";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp0_comphy4 0>;
+};
+
+&cp0_sata0 {
+ /* CPM Lane 0 - U29 */
+ status = "okay";
+};
+
+&cp0_sdhci0 {
+ /* U6 */
+ broken-cd;
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_sdhci_pins>;
+ status = "okay";
+ vqmmc-supply = <&v_3_3>;
+};
+
+&cp0_usb3_0 {
+ /* J38? - USB2.0 only */
+ status = "okay";
+};
+
+&cp0_usb3_1 {
+ /* J38? - USB2.0 only */
+ status = "okay";
+};
+
+&cp1_ethernet {
+ status = "okay";
+};
+
+&cp1_eth0 {
+ status = "okay";
+ /* Network PHY */
+ phy = <&phy8>;
+ phy-mode = "10gbase-kr";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp1_comphy4 0>;
+};
+
+&cp1_eth1 {
+ /* CPS Lane 0 - J5 (Gigabit RJ45) */
+ status = "okay";
+ /* Network PHY */
+ phy = <&ge_phy>;
+ phy-mode = "sgmii";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp1_comphy0 1>;
+};
+
+&cp1_eth2 {
+ /* CPS Lane 5 */
+ status = "okay";
+ /* Network PHY */
+ phy-mode = "2500base-x";
+ managed = "in-band-status";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp1_comphy5 2>;
+ sfp = <&sfp_eth3>;
+};
+
+&cp1_pinctrl {
+ cp1_sfpp1_pins: sfpp1-pins {
+ marvell,pins = "mpp8", "mpp10", "mpp11";
+ marvell,function = "gpio";
+ };
+ cp1_spi1_pins: spi1-pins {
+ marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16";
+ marvell,function = "spi1";
+ };
+ cp1_uart0_pins: uart0-pins {
+ marvell,pins = "mpp6", "mpp7";
+ marvell,function = "uart0";
+ };
+ cp1_sfp_1g_pins: sfp-1g-pins {
+ marvell,pins = "mpp24";
+ marvell,function = "gpio";
+ };
+ cp1_sfpp0_pins: sfpp0-pins {
+ marvell,pins = "mpp26", "mpp27", "mpp28", "mpp29";
+ marvell,function = "gpio";
+ };
+};
+
+/* J27 UART header */
+&cp1_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_uart0_pins>;
+ status = "okay";
+};
+
+&cp1_sata0 {
+ /* CPS Lane 1 - U32 */
+ /* CPS Lane 3 - U31 */
+ status = "okay";
+};
+
+&cp1_spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_spi1_pins>;
+ status = "okay";
+
+ spi-flash@0 {
+ compatible = "st,w25q32";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ };
+};
+
+&cp1_usb3_0 {
+ /* CPS Lane 2 - CON7 */
+ usb-phy = <&usb3h0_phy>;
+ status = "okay";
+};
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi
new file mode 100644
index 0000000..784ef3f
--- /dev/null
+++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ *
+ * Device Tree file for the Armada 8040 SoC, made of an AP806 Quad and
+ * two CP110.
+ */
+
+#include "armada-ap806-quad.dtsi"
+#include "armada-80x0.dtsi"
+
+/ {
+ model = "Marvell Armada 8040";
+ compatible = "marvell,armada8040", "marvell,armada-ap806-quad",
+ "marvell,armada-ap806";
+};
+
+/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock
+ * in CP master is not connected (by package) to the oscillator. So
+ * disable it. However, the RTC clock in CP slave is connected to the
+ * oscillator so this one is let enabled.
+ */
+&cp0_rtc {
+ status = "disabled";
+};
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi
new file mode 100644
index 0000000..81967e2
--- /dev/null
+++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi
@@ -0,0 +1,108 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2017 Marvell Technology Group Ltd.
+ *
+ * Device Tree file for the Armada 80x0 SoC family
+ */
+
+/ {
+ aliases {
+ gpio1 = &cp1_gpio1;
+ gpio2 = &cp0_gpio2;
+ spi1 = &cp0_spi0;
+ spi2 = &cp0_spi1;
+ spi3 = &cp1_spi0;
+ spi4 = &cp1_spi1;
+ };
+};
+
+/*
+ * Instantiate the master CP110
+ */
+#define CP110_NAME cp0
+#define CP110_BASE f2000000
+#define CP110_PCIE_IO_BASE 0xf9000000
+#define CP110_PCIE_MEM_BASE 0xf6000000
+#define CP110_PCIE0_BASE f2600000
+#define CP110_PCIE1_BASE f2620000
+#define CP110_PCIE2_BASE f2640000
+
+#include "armada-cp110.dtsi"
+
+#undef CP110_NAME
+#undef CP110_BASE
+#undef CP110_PCIE_IO_BASE
+#undef CP110_PCIE_MEM_BASE
+#undef CP110_PCIE0_BASE
+#undef CP110_PCIE1_BASE
+#undef CP110_PCIE2_BASE
+
+/*
+ * Instantiate the slave CP110
+ */
+#define CP110_NAME cp1
+#define CP110_BASE f4000000
+#define CP110_PCIE_IO_BASE 0xfd000000
+#define CP110_PCIE_MEM_BASE 0xfa000000
+#define CP110_PCIE0_BASE f4600000
+#define CP110_PCIE1_BASE f4620000
+#define CP110_PCIE2_BASE f4640000
+
+#include "armada-cp110.dtsi"
+
+#undef CP110_NAME
+#undef CP110_BASE
+#undef CP110_PCIE_IO_BASE
+#undef CP110_PCIE_MEM_BASE
+#undef CP110_PCIE0_BASE
+#undef CP110_PCIE1_BASE
+#undef CP110_PCIE2_BASE
+
+/* The 80x0 has two CP blocks, but uses only one block from each. */
+&cp1_gpio1 {
+ status = "okay";
+};
+
+&cp0_gpio2 {
+ status = "okay";
+};
+
+&cp0_syscon0 {
+ cp0_pinctrl: pinctrl {
+ compatible = "marvell,armada-8k-cpm-pinctrl";
+ };
+};
+
+&cp1_syscon0 {
+ cp1_pinctrl: pinctrl {
+ compatible = "marvell,armada-8k-cps-pinctrl";
+
+ nand_pins: nand-pins {
+ marvell,pins =
+ "mpp0", "mpp1", "mpp2", "mpp3",
+ "mpp4", "mpp5", "mpp6", "mpp7",
+ "mpp8", "mpp9", "mpp10", "mpp11",
+ "mpp15", "mpp16", "mpp17", "mpp18",
+ "mpp19", "mpp20", "mpp21", "mpp22",
+ "mpp23", "mpp24", "mpp25", "mpp26",
+ "mpp27";
+ marvell,function = "dev";
+ };
+
+ nand_rb: nand-rb {
+ marvell,pins = "mpp13", "mpp12";
+ marvell,function = "nf";
+ };
+ };
+};
+
+&cp1_crypto {
+ /*
+ * The cryptographic engine found on the cp110
+ * master is enabled by default at the SoC
+ * level. Because it is not possible as of now
+ * to enable two cryptographic engines in
+ * parallel, disable this one by default.
+ */
+ status = "disabled";
+};
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi
new file mode 100644
index 0000000..5985843
--- /dev/null
+++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ *
+ * Device Tree file for Marvell Armada AP806.
+ */
+
+#include "armada-ap806.dtsi"
+
+/ {
+ model = "Marvell Armada AP806 Dual";
+ compatible = "marvell,armada-ap806-dual", "marvell,armada-ap806";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x000>;
+ enable-method = "psci";
+ };
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x001>;
+ enable-method = "psci";
+ };
+ };
+};
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi
new file mode 100644
index 0000000..bae0ed9
--- /dev/null
+++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ *
+ * Device Tree file for Marvell Armada AP806.
+ */
+
+#include "armada-ap806.dtsi"
+
+/ {
+ model = "Marvell Armada AP806 Quad";
+ compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x000>;
+ enable-method = "psci";
+ };
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x001>;
+ enable-method = "psci";
+ };
+ cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x100>;
+ enable-method = "psci";
+ };
+ cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x101>;
+ enable-method = "psci";
+ };
+ };
+};
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi
new file mode 100644
index 0000000..66124bf
--- /dev/null
+++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi
@@ -0,0 +1,264 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ *
+ * Device Tree file for Marvell Armada AP806.
+ */
+
+#define IRQ_TYPE_LEVEL_HIGH (1 << 2)
+#define IRQ_TYPE_LEVEL_LOW (1 << 3)
+
+#define GIC_SPI 0
+#define GIC_PPI 1
+
+#define GIC_CPU_MASK_RAW(x) ((x) << 8)
+#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1)
+
+/dts-v1/;
+
+/ {
+ model = "Marvell Armada AP806";
+ compatible = "marvell,armada-ap806";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ gpio0 = &ap_gpio;
+ spi0 = &spi0;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ ap806 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ config-space@f0000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0x0 0xf0000000 0x1000000>;
+
+ gic: interrupt-controller@210000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ reg = <0x210000 0x10000>,
+ <0x220000 0x20000>,
+ <0x240000 0x20000>,
+ <0x260000 0x20000>;
+
+ gic_v2m0: v2m@280000 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0x280000 0x1000>;
+ arm,msi-base-spi = <160>;
+ arm,msi-num-spis = <32>;
+ };
+ gic_v2m1: v2m@290000 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0x290000 0x1000>;
+ arm,msi-base-spi = <192>;
+ arm,msi-num-spis = <32>;
+ };
+ gic_v2m2: v2m@2a0000 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0x2a0000 0x1000>;
+ arm,msi-base-spi = <224>;
+ arm,msi-num-spis = <32>;
+ };
+ gic_v2m3: v2m@2b0000 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0x2b0000 0x1000>;
+ arm,msi-base-spi = <256>;
+ arm,msi-num-spis = <32>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a72-pmu";
+ interrupt-parent = <&pic>;
+ interrupts = <17>;
+ };
+
+ odmi: odmi@300000 {
+ compatible = "marvell,odmi-controller";
+ interrupt-controller;
+ msi-controller;
+ marvell,odmi-frames = <4>;
+ reg = <0x300000 0x4000>,
+ <0x304000 0x4000>,
+ <0x308000 0x4000>,
+ <0x30C000 0x4000>;
+ marvell,spi-base = <128>, <136>, <144>, <152>;
+ };
+
+ gicp: gicp@3f0040 {
+ compatible = "marvell,ap806-gicp";
+ reg = <0x3f0040 0x10>;
+ marvell,spi-ranges = <64 64>, <288 64>;
+ msi-controller;
+ };
+
+ pic: interrupt-controller@3f0100 {
+ compatible = "marvell,armada-8k-pic";
+ reg = <0x3f0100 0x10>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ xor@400000 {
+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+ reg = <0x400000 0x1000>,
+ <0x410000 0x1000>;
+ msi-parent = <&gic_v2m0>;
+ clocks = <&ap_clk 3>;
+ dma-coherent;
+ };
+
+ xor@420000 {
+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+ reg = <0x420000 0x1000>,
+ <0x430000 0x1000>;
+ msi-parent = <&gic_v2m0>;
+ clocks = <&ap_clk 3>;
+ dma-coherent;
+ };
+
+ xor@440000 {
+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+ reg = <0x440000 0x1000>,
+ <0x450000 0x1000>;
+ msi-parent = <&gic_v2m0>;
+ clocks = <&ap_clk 3>;
+ dma-coherent;
+ };
+
+ xor@460000 {
+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+ reg = <0x460000 0x1000>,
+ <0x470000 0x1000>;
+ msi-parent = <&gic_v2m0>;
+ clocks = <&ap_clk 3>;
+ dma-coherent;
+ };
+
+ spi0: spi@510600 {
+ compatible = "marvell,armada-380-spi";
+ reg = <0x510600 0x50>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ap_clk 3>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@511000 {
+ compatible = "marvell,mv78230-i2c";
+ reg = <0x511000 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ timeout-ms = <1000>;
+ clocks = <&ap_clk 3>;
+ status = "disabled";
+ };
+
+ uart0: serial@512000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x512000 0x100>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ clocks = <&ap_clk 3>;
+ status = "disabled";
+ };
+
+ uart1: serial@512100 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x512100 0x100>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ clocks = <&ap_clk 3>;
+ status = "disabled";
+
+ };
+
+ watchdog: watchdog@610000 {
+ compatible = "arm,sbsa-gwdt";
+ reg = <0x610000 0x1000>, <0x600000 0x1000>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ ap_sdhci0: sdhci@6e0000 {
+ compatible = "marvell,armada-ap806-sdhci";
+ reg = <0x6e0000 0x300>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core";
+ clocks = <&ap_clk 4>;
+ dma-coherent;
+ marvell,xenon-phy-slow-mode;
+ status = "disabled";
+ };
+
+ ap_syscon: system-controller@6f4000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x6f4000 0x2000>;
+
+ ap_clk: clock {
+ compatible = "marvell,ap806-clock";
+ #clock-cells = <1>;
+ };
+
+ ap_pinctrl: pinctrl {
+ compatible = "marvell,ap806-pinctrl";
+
+ uart0_pins: uart0-pins {
+ marvell,pins = "mpp11", "mpp19";
+ marvell,function = "uart0";
+ };
+ };
+
+ ap_gpio: gpio@1040 {
+ compatible = "marvell,armada-8k-gpio";
+ offset = <0x1040>;
+ ngpios = <20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&ap_pinctrl 0 0 20>;
+ };
+ };
+
+ ap_thermal: thermal@6f808c {
+ compatible = "marvell,armada-ap806-thermal";
+ reg = <0x6f808c 0x4>,
+ <0x6f8084 0x8>;
+ };
+ };
+ };
+};
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi
new file mode 100644
index 0000000..8b610fd
--- /dev/null
+++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ */
+
+/* Common definitions used by Armada 7K/8K DTs */
+#define PASTER(x, y) x ## y
+#define EVALUATOR(x, y) PASTER(x, y)
+#define CP110_LABEL(name) EVALUATOR(CP110_NAME, EVALUATOR(_, name))
+#define ADDRESSIFY(addr) EVALUATOR(0x, addr)
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi
new file mode 100644
index 0000000..b9504a3
--- /dev/null
+++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi
@@ -0,0 +1,503 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ *
+ * Device Tree file for Marvell Armada CP110.
+ */
+
+#include "armada-common.dtsi"
+
+#define ICU_GRP_NSR 0x0
+#define ICU_GRP_SR 0x1
+#define ICU_GRP_SEI 0x4
+#define ICU_GRP_REI 0x5
+
+#define CP110_PCIEx_IO_BASE(iface) (CP110_PCIE_IO_BASE + (iface * 0x10000))
+#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIE_MEM_BASE + (iface * 0x1000000))
+#define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) + 0xf00000)
+
+/ {
+ /*
+ * The contents of the node are defined below, in order to
+ * save one indentation level
+ */
+ CP110_NAME: CP110_NAME { };
+};
+
+&CP110_NAME {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ interrupt-parent = <&CP110_LABEL(icu)>;
+ ranges;
+
+ config-space@CP110_BASE {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>;
+
+ CP110_LABEL(ethernet): ethernet@0 {
+ compatible = "marvell,armada-7k-pp22";
+ reg = <0x0 0x100000>, <0x129000 0xb000>;
+ clocks = <&CP110_LABEL(clk) 1 3>, <&CP110_LABEL(clk) 1 9>,
+ <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>,
+ <&CP110_LABEL(clk) 1 18>;
+ clock-names = "pp_clk", "gop_clk",
+ "mg_clk", "mg_core_clk", "axi_clk";
+ marvell,system-controller = <&CP110_LABEL(syscon0)>;
+ status = "disabled";
+ dma-coherent;
+
+ CP110_LABEL(eth0): eth0 {
+ interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
+ "tx-cpu3", "rx-shared", "link";
+ port-id = <0>;
+ gop-port-id = <0>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(eth1): eth1 {
+ interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
+ "tx-cpu3", "rx-shared", "link";
+ port-id = <1>;
+ gop-port-id = <2>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(eth2): eth2 {
+ interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
+ "tx-cpu3", "rx-shared", "link";
+ port-id = <2>;
+ gop-port-id = <3>;
+ status = "disabled";
+ };
+ };
+
+ CP110_LABEL(comphy): phy@120000 {
+ compatible = "marvell,comphy-cp110";
+ reg = <0x120000 0x6000>;
+ marvell,system-controller = <&CP110_LABEL(syscon0)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CP110_LABEL(comphy0): phy@0 {
+ reg = <0>;
+ #phy-cells = <1>;
+ };
+
+ CP110_LABEL(comphy1): phy@1 {
+ reg = <1>;
+ #phy-cells = <1>;
+ };
+
+ CP110_LABEL(comphy2): phy@2 {
+ reg = <2>;
+ #phy-cells = <1>;
+ };
+
+ CP110_LABEL(comphy3): phy@3 {
+ reg = <3>;
+ #phy-cells = <1>;
+ };
+
+ CP110_LABEL(comphy4): phy@4 {
+ reg = <4>;
+ #phy-cells = <1>;
+ };
+
+ CP110_LABEL(comphy5): phy@5 {
+ reg = <5>;
+ #phy-cells = <1>;
+ };
+ };
+
+ CP110_LABEL(mdio): mdio@12a200 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "marvell,orion-mdio";
+ reg = <0x12a200 0x10>;
+ clocks = <&CP110_LABEL(clk) 1 9>, <&CP110_LABEL(clk) 1 5>,
+ <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(xmdio): mdio@12a600 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "marvell,xmdio";
+ reg = <0x12a600 0x10>;
+ clocks = <&CP110_LABEL(clk) 1 5>,
+ <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(icu): interrupt-controller@1e0000 {
+ compatible = "marvell,cp110-icu";
+ reg = <0x1e0000 0x440>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ msi-parent = <&gicp>;
+ };
+
+ CP110_LABEL(rtc): rtc@284000 {
+ compatible = "marvell,armada-8k-rtc";
+ reg = <0x284000 0x20>, <0x284080 0x24>;
+ reg-names = "rtc", "rtc-soc";
+ interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ CP110_LABEL(thermal): thermal@400078 {
+ compatible = "marvell,armada-cp110-thermal";
+ reg = <0x400078 0x4>,
+ <0x400070 0x8>;
+ };
+
+ CP110_LABEL(syscon0): system-controller@440000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x440000 0x2000>;
+
+ CP110_LABEL(clk): clock {
+ compatible = "marvell,cp110-clock";
+ #clock-cells = <2>;
+ };
+
+ CP110_LABEL(gpio1): gpio@100 {
+ compatible = "marvell,armada-8k-gpio";
+ offset = <0x100>;
+ ngpios = <32>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>;
+ interrupt-controller;
+ interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(gpio2): gpio@140 {
+ compatible = "marvell,armada-8k-gpio";
+ offset = <0x140>;
+ ngpios = <31>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&CP110_LABEL(pinctrl) 0 32 31>;
+ interrupt-controller;
+ interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+
+ CP110_LABEL(usb3_0): usb3@500000 {
+ compatible = "marvell,armada-8k-xhci",
+ "generic-xhci";
+ reg = <0x500000 0x4000>;
+ dma-coherent;
+ interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(clk) 1 22>,
+ <&CP110_LABEL(clk) 1 16>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(usb3_1): usb3@510000 {
+ compatible = "marvell,armada-8k-xhci",
+ "generic-xhci";
+ reg = <0x510000 0x4000>;
+ dma-coherent;
+ interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(clk) 1 23>,
+ <&CP110_LABEL(clk) 1 16>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(sata0): sata@540000 {
+ compatible = "marvell,armada-8k-ahci",
+ "generic-ahci";
+ reg = <0x540000 0x30000>;
+ dma-coherent;
+ interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&CP110_LABEL(clk) 1 15>,
+ <&CP110_LABEL(clk) 1 16>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(xor0): xor@6a0000 {
+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+ reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
+ dma-coherent;
+ msi-parent = <&gic_v2m0>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(clk) 1 8>,
+ <&CP110_LABEL(clk) 1 14>;
+ };
+
+ CP110_LABEL(xor1): xor@6c0000 {
+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+ reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
+ dma-coherent;
+ msi-parent = <&gic_v2m0>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(clk) 1 7>,
+ <&CP110_LABEL(clk) 1 14>;
+ };
+
+ CP110_LABEL(spi0): spi@700600 {
+ compatible = "marvell,armada-380-spi";
+ reg = <0x700600 0x50>;
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ clock-names = "core", "axi";
+ clocks = <&CP110_LABEL(clk) 1 21>,
+ <&CP110_LABEL(clk) 1 17>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(spi1): spi@700680 {
+ compatible = "marvell,armada-380-spi";
+ reg = <0x700680 0x50>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "core", "axi";
+ clocks = <&CP110_LABEL(clk) 1 21>,
+ <&CP110_LABEL(clk) 1 17>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(i2c0): i2c@701000 {
+ compatible = "marvell,mv78230-i2c";
+ reg = <0x701000 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(clk) 1 21>,
+ <&CP110_LABEL(clk) 1 17>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(i2c1): i2c@701100 {
+ compatible = "marvell,mv78230-i2c";
+ reg = <0x701100 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(clk) 1 21>,
+ <&CP110_LABEL(clk) 1 17>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(uart0): serial@702000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x702000 0x100>;
+ reg-shift = <2>;
+ interrupts = <ICU_GRP_NSR 122 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ clock-names = "baudclk", "apb_pclk";
+ clocks = <&CP110_LABEL(clk) 1 21>,
+ <&CP110_LABEL(clk) 1 17>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(uart1): serial@702100 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x702100 0x100>;
+ reg-shift = <2>;
+ interrupts = <ICU_GRP_NSR 123 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ clock-names = "baudclk", "apb_pclk";
+ clocks = <&CP110_LABEL(clk) 1 21>,
+ <&CP110_LABEL(clk) 1 17>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(uart2): serial@702200 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x702200 0x100>;
+ reg-shift = <2>;
+ interrupts = <ICU_GRP_NSR 124 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ clock-names = "baudclk", "apb_pclk";
+ clocks = <&CP110_LABEL(clk) 1 21>,
+ <&CP110_LABEL(clk) 1 17>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(uart3): serial@702300 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x702300 0x100>;
+ reg-shift = <2>;
+ interrupts = <ICU_GRP_NSR 125 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ clock-names = "baudclk", "apb_pclk";
+ clocks = <&CP110_LABEL(clk) 1 21>,
+ <&CP110_LABEL(clk) 1 17>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(nand_controller): nand@720000 {
+ /*
+ * Due to the limitation of the pins available
+ * this controller is only usable on the CPM
+ * for A7K and on the CPS for A8K.
+ */
+ compatible = "marvell,armada-8k-nand-controller",
+ "marvell,armada370-nand-controller";
+ reg = <0x720000 0x54>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(clk) 1 2>,
+ <&CP110_LABEL(clk) 1 17>;
+ marvell,system-controller = <&CP110_LABEL(syscon0)>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(trng): trng@760000 {
+ compatible = "marvell,armada-8k-rng",
+ "inside-secure,safexcel-eip76";
+ reg = <0x760000 0x7d>;
+ interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(clk) 1 25>,
+ <&CP110_LABEL(clk) 1 17>;
+ status = "okay";
+ };
+
+ CP110_LABEL(sdhci0): sdhci@780000 {
+ compatible = "marvell,armada-cp110-sdhci";
+ reg = <0x780000 0x300>;
+ interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core", "axi";
+ clocks = <&CP110_LABEL(clk) 1 4>, <&CP110_LABEL(clk) 1 18>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ CP110_LABEL(crypto): crypto@800000 {
+ compatible = "inside-secure,safexcel-eip197";
+ reg = <0x800000 0x200000>;
+ interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mem", "ring0", "ring1",
+ "ring2", "ring3", "eip";
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(clk) 1 26>,
+ <&CP110_LABEL(clk) 1 17>;
+ dma-coherent;
+ };
+ };
+
+ CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE {
+ compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+ reg = <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>,
+ <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>;
+ reg-names = "ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ dma-coherent;
+ msi-parent = <&gic_v2m0>;
+
+ bus-range = <0 0xff>;
+ ranges =
+ /* downstream I/O */
+ <0x81000000 0 CP110_PCIEx_IO_BASE(0) 0 CP110_PCIEx_IO_BASE(0) 0 0x10000
+ /* non-prefetchable memory */
+ 0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BASE(0) 0 0xf00000>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
+ num-lanes = <1>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(clk) 1 13>, <&CP110_LABEL(clk) 1 14>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE {
+ compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+ reg = <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>,
+ <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>;
+ reg-names = "ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ dma-coherent;
+ msi-parent = <&gic_v2m0>;
+
+ bus-range = <0 0xff>;
+ ranges =
+ /* downstream I/O */
+ <0x81000000 0 CP110_PCIEx_IO_BASE(1) 0 CP110_PCIEx_IO_BASE(1) 0 0x10000
+ /* non-prefetchable memory */
+ 0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BASE(1) 0 0xf00000>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
+
+ num-lanes = <1>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(clk) 1 11>, <&CP110_LABEL(clk) 1 14>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE {
+ compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+ reg = <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>,
+ <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>;
+ reg-names = "ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ dma-coherent;
+ msi-parent = <&gic_v2m0>;
+
+ bus-range = <0 0xff>;
+ ranges =
+ /* downstream I/O */
+ <0x81000000 0 CP110_PCIEx_IO_BASE(2) 0 CP110_PCIEx_IO_BASE(2) 0 0x10000
+ /* non-prefetchable memory */
+ 0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BASE(2) 0 0xf00000>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
+
+ num-lanes = <1>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(clk) 1 12>, <&CP110_LABEL(clk) 1 14>;
+ status = "disabled";
+ };
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 14+ messages in thread* [platforms: PATCH v2 2/9] Marvell/Armada7k8k: Enable including additional DXE FV components
2018-08-07 8:58 [platforms: PATCH v2 0/9] Armada7k8k DT/ACPI support Marcin Wojtas
2018-08-07 8:58 ` [platforms: PATCH v2 1/9] Marvell/Armada7k8k: Import device tree Marcin Wojtas
@ 2018-08-07 8:58 ` Marcin Wojtas
2018-08-07 8:58 ` [platforms: PATCH v2 3/9] Marvell/Armada70x0Db: Enable device tree support Marcin Wojtas
` (7 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Marcin Wojtas @ 2018-08-07 8:58 UTC (permalink / raw)
To: edk2-devel; +Cc: leif.lindholm, ard.biesheuvel, nadavh, mw, jsd, jaz
Unified .fdf file allows to update all Armada7k8k-based
boards at the same time. However there may be a need
to add unique DXE firmware volume contents like DTB
or ACPI.
For this purpose create empty files for existing boards
that are included as defined in BOARD_DXE_FV_COMPONENTS
macro.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc | 1 +
Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc | 1 +
Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc | 1 +
Silicon/Marvell/Armada7k8k/Armada7k8k.fdf | 2 ++
Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf.inc | 13 +++++++++++++
Platform/Marvell/Armada80x0Db/Armada80x0Db.fdf.inc | 13 +++++++++++++
Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.fdf.inc | 13 +++++++++++++
7 files changed, 44 insertions(+)
create mode 100644 Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf.inc
create mode 100644 Platform/Marvell/Armada80x0Db/Armada80x0Db.fdf.inc
create mode 100644 Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.fdf.inc
diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc
index 2240a57..0c08328 100644
--- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc
+++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc
@@ -44,6 +44,7 @@
BUILD_TARGETS = DEBUG|RELEASE|NOOPT
SKUID_IDENTIFIER = DEFAULT
FLASH_DEFINITION = Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
+ BOARD_DXE_FV_COMPONENTS = Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf.inc
!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
diff --git a/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc b/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc
index 2425c45..2d4523f2 100644
--- a/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc
+++ b/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc
@@ -44,6 +44,7 @@
BUILD_TARGETS = DEBUG|RELEASE|NOOPT
SKUID_IDENTIFIER = DEFAULT
FLASH_DEFINITION = Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
+ BOARD_DXE_FV_COMPONENTS = Platform/Marvell/Armada80x0Db/Armada80x0Db.fdf.inc
!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
index 1baed88..e1f5827 100644
--- a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
+++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
@@ -44,6 +44,7 @@
BUILD_TARGETS = DEBUG|RELEASE|NOOPT
SKUID_IDENTIFIER = DEFAULT
FLASH_DEFINITION = Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
+ BOARD_DXE_FV_COMPONENTS = Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.fdf.inc
CAPSULE_ENABLE = TRUE
!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf b/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
index 18d5d06..0f38978 100644
--- a/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
+++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
@@ -212,6 +212,8 @@ FvNameGuid = 5eda4200-2c5f-43cb-9da3-0baf74b1b30c
}
!endif
+!include $(BOARD_DXE_FV_COMPONENTS)
+
# PEI phase firmware volume
[FV.FVMAIN_COMPACT]
FvAlignment = 8
diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf.inc b/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf.inc
new file mode 100644
index 0000000..984cf7e
--- /dev/null
+++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf.inc
@@ -0,0 +1,13 @@
+#
+# Copyright (C) 2018 Marvell International Ltd. and its affiliates
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+# Per-board additional content of the DXE phase firmware volume
diff --git a/Platform/Marvell/Armada80x0Db/Armada80x0Db.fdf.inc b/Platform/Marvell/Armada80x0Db/Armada80x0Db.fdf.inc
new file mode 100644
index 0000000..984cf7e
--- /dev/null
+++ b/Platform/Marvell/Armada80x0Db/Armada80x0Db.fdf.inc
@@ -0,0 +1,13 @@
+#
+# Copyright (C) 2018 Marvell International Ltd. and its affiliates
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+# Per-board additional content of the DXE phase firmware volume
diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.fdf.inc b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.fdf.inc
new file mode 100644
index 0000000..984cf7e
--- /dev/null
+++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.fdf.inc
@@ -0,0 +1,13 @@
+#
+# Copyright (C) 2018 Marvell International Ltd. and its affiliates
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+# Per-board additional content of the DXE phase firmware volume
--
2.7.4
^ permalink raw reply related [flat|nested] 14+ messages in thread* [platforms: PATCH v2 3/9] Marvell/Armada70x0Db: Enable device tree support
2018-08-07 8:58 [platforms: PATCH v2 0/9] Armada7k8k DT/ACPI support Marcin Wojtas
2018-08-07 8:58 ` [platforms: PATCH v2 1/9] Marvell/Armada7k8k: Import device tree Marcin Wojtas
2018-08-07 8:58 ` [platforms: PATCH v2 2/9] Marvell/Armada7k8k: Enable including additional DXE FV components Marcin Wojtas
@ 2018-08-07 8:58 ` Marcin Wojtas
2018-08-07 8:58 ` [platforms: PATCH v2 4/9] Marvell/Armada80x0Db: " Marcin Wojtas
` (6 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Marcin Wojtas @ 2018-08-07 8:58 UTC (permalink / raw)
To: edk2-devel; +Cc: leif.lindholm, ard.biesheuvel, nadavh, mw, jsd, jaz
This patch enables compilation of the Armada 7040 DB
device tree. Necessary adjustments are added, so that
the OS can use efi-rtc and has no access to the SPI
flash
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 4 +++
Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc | 3 +++
Silicon/Marvell/Armada7k8k/Armada7k8k.fdf | 8 ++++++
Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf | 28 ++++++++++++++++++++
Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf.inc | 3 +++
Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts | 2 +-
Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi | 1 +
7 files changed, 48 insertions(+), 1 deletion(-)
create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf
diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
index 2d38ea4..f1ccda0 100644
--- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
+++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
@@ -200,6 +200,7 @@
PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf
+ DtPlatformDtbLoaderLib|EmbeddedPkg/Library/DxeDtPlatformDtbLoaderLibDefault/DxeDtPlatformDtbLoaderLibDefault.inf
[LibraryClasses.common.UEFI_APPLICATION]
UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
@@ -585,6 +586,9 @@
gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
}
+ # DTB
+ EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf
+
!ifdef $(INCLUDE_TFTP_COMMAND)
ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
!endif #$(INCLUDE_TFTP_COMMAND)
diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc
index 0c08328..d3dffb0 100644
--- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc
+++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc
@@ -48,6 +48,9 @@
!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
+[Components.common]
+ Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf
+
################################################################################
#
# Pcd Section - list of all EDK II PCD Entries defined by this Platform
diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf b/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
index 0f38978..909ad3e 100644
--- a/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
+++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
@@ -212,6 +212,9 @@ FvNameGuid = 5eda4200-2c5f-43cb-9da3-0baf74b1b30c
}
!endif
+ # DTB
+ INF EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf
+
!include $(BOARD_DXE_FV_COMPONENTS)
# PEI phase firmware volume
@@ -400,3 +403,8 @@ READ_LOCK_STATUS = TRUE
UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
+
+[Rule.Common.USER_DEFINED.DTB]
+ FILE FREEFORM = $(NAMED_GUID) {
+ RAW BIN |.dtb
+ }
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf b/Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf
new file mode 100644
index 0000000..1f2d9ea
--- /dev/null
+++ b/Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf
@@ -0,0 +1,28 @@
+## @file
+#
+# Device tree description of the Marvell Armada 7040 DB platform
+#
+# Copyright (c) 2018, Marvell International Ltd. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = Armada70x0DbDeviceTree
+ FILE_GUID = 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDefaultDtbFileGuid
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ armada-7040-db.dts
+
+[Packages]
+ MdePkg/MdePkg.dec
diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf.inc b/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf.inc
index 984cf7e..b4c3e20 100644
--- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf.inc
+++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf.inc
@@ -11,3 +11,6 @@
#
# Per-board additional content of the DXE phase firmware volume
+
+ # DTB
+ INF RuleOverride = DTB Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts
index 6b28bbe..f5878ef 100644
--- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts
+++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts
@@ -168,7 +168,7 @@
};
&cp0_spi1 {
- status = "okay";
+ status = "disabled";
spi-flash@0 {
#address-cells = <0x1>;
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi
index b9504a3..3337034 100644
--- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi
+++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi
@@ -163,6 +163,7 @@
reg = <0x284000 0x20>, <0x284080 0x24>;
reg-names = "rtc", "rtc-soc";
interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
};
CP110_LABEL(thermal): thermal@400078 {
--
2.7.4
^ permalink raw reply related [flat|nested] 14+ messages in thread* [platforms: PATCH v2 4/9] Marvell/Armada80x0Db: Enable device tree support
2018-08-07 8:58 [platforms: PATCH v2 0/9] Armada7k8k DT/ACPI support Marcin Wojtas
` (2 preceding siblings ...)
2018-08-07 8:58 ` [platforms: PATCH v2 3/9] Marvell/Armada70x0Db: Enable device tree support Marcin Wojtas
@ 2018-08-07 8:58 ` Marcin Wojtas
2018-08-07 8:58 ` [platforms: PATCH v2 5/9] Marvell/Armada80x0McBin: " Marcin Wojtas
` (5 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Marcin Wojtas @ 2018-08-07 8:58 UTC (permalink / raw)
To: edk2-devel; +Cc: leif.lindholm, ard.biesheuvel, nadavh, mw, jsd, jaz
This patch enables compilation of the Armada 8040 DB
device tree. Also disable OS access to the SPI flash.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc | 3 +++
Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf | 28 ++++++++++++++++++++
Platform/Marvell/Armada80x0Db/Armada80x0Db.fdf.inc | 3 +++
Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts | 2 +-
4 files changed, 35 insertions(+), 1 deletion(-)
create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf
diff --git a/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc b/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc
index 2d4523f2..3fc33d4 100644
--- a/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc
+++ b/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc
@@ -48,6 +48,9 @@
!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
+[Components.common]
+ Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf
+
################################################################################
#
# Pcd Section - list of all EDK II PCD Entries defined by this Platform
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf b/Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf
new file mode 100644
index 0000000..e4dd41c
--- /dev/null
+++ b/Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf
@@ -0,0 +1,28 @@
+## @file
+#
+# Device tree description of the Marvell Armada 8040 DB platform
+#
+# Copyright (c) 2018, Marvell International Ltd. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = Armada80x0DbDeviceTree
+ FILE_GUID = 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDefaultDtbFileGuid
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ armada-8040-db.dts
+
+[Packages]
+ MdePkg/MdePkg.dec
diff --git a/Platform/Marvell/Armada80x0Db/Armada80x0Db.fdf.inc b/Platform/Marvell/Armada80x0Db/Armada80x0Db.fdf.inc
index 984cf7e..99e1a11 100644
--- a/Platform/Marvell/Armada80x0Db/Armada80x0Db.fdf.inc
+++ b/Platform/Marvell/Armada80x0Db/Armada80x0Db.fdf.inc
@@ -11,3 +11,6 @@
#
# Per-board additional content of the DXE phase firmware volume
+
+ # DTB
+ INF RuleOverride = DTB Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts
index 7518029..e813922 100644
--- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts
+++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts
@@ -213,7 +213,7 @@
};
&cp1_spi1 {
- status = "okay";
+ status = "disabled";
spi-flash@0 {
#address-cells = <0x1>;
--
2.7.4
^ permalink raw reply related [flat|nested] 14+ messages in thread* [platforms: PATCH v2 5/9] Marvell/Armada80x0McBin: Enable device tree support
2018-08-07 8:58 [platforms: PATCH v2 0/9] Armada7k8k DT/ACPI support Marcin Wojtas
` (3 preceding siblings ...)
2018-08-07 8:58 ` [platforms: PATCH v2 4/9] Marvell/Armada80x0Db: " Marcin Wojtas
@ 2018-08-07 8:58 ` Marcin Wojtas
2018-08-07 8:58 ` [platforms: PATCH v2 6/9] Marvell/Armada7k8k: Add common ACPI tables Marcin Wojtas
` (4 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Marcin Wojtas @ 2018-08-07 8:58 UTC (permalink / raw)
To: edk2-devel; +Cc: leif.lindholm, ard.biesheuvel, nadavh, mw, jsd, jaz
This patch enables compilation of the Armada 8040 MacchiatoBin
device tree. Dsable OS acccess to the SPI flash and extend
PCI ranges to use 256MB mmio32 and 4GB mmio64.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc | 3 +++
Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf | 28 ++++++++++++++++++++
Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.fdf.inc | 3 +++
Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts | 5 +++-
4 files changed, 38 insertions(+), 1 deletion(-)
create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf
diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
index e1f5827..e6cb0d6 100644
--- a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
+++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
@@ -49,6 +49,9 @@
!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
+[Components.common]
+ Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf
+
################################################################################
#
# Pcd Section - list of all EDK II PCD Entries defined by this Platform
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf b/Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf
new file mode 100644
index 0000000..810a52b
--- /dev/null
+++ b/Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf
@@ -0,0 +1,28 @@
+## @file
+#
+# Device tree description of the Marvell Armada 8040 MacchiatoBin platform
+#
+# Copyright (c) 2018, Marvell International Ltd. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = Armada80x0McBinDeviceTree
+ FILE_GUID = 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDefaultDtbFileGuid
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ armada-8040-mcbin.dts
+
+[Packages]
+ MdePkg/MdePkg.dec
diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.fdf.inc b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.fdf.inc
index 984cf7e..4eb1496 100644
--- a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.fdf.inc
+++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.fdf.inc
@@ -11,3 +11,6 @@
#
# Per-board additional content of the DXE phase firmware volume
+
+ # DTB
+ INF RuleOverride = DTB Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf
diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts
index 0e20e70..b86e27e 100644
--- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts
+++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts
@@ -185,6 +185,9 @@
num-lanes = <4>;
num-viewport = <8>;
reset-gpio = <&cp0_gpio1 20 GPIO_ACTIVE_LOW>;
+ ranges = <0x1000000 0x0 0x00000000 0x0 0xeff00000 0x0 0x00010000>,
+ <0x2000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>,
+ <0x3000000 0x8 0x00000000 0x8 0x00000000 0x1 0x00000000>;
status = "okay";
};
@@ -355,7 +358,7 @@
&cp1_spi1 {
pinctrl-names = "default";
pinctrl-0 = <&cp1_spi1_pins>;
- status = "okay";
+ status = "disabled";
spi-flash@0 {
compatible = "st,w25q32";
--
2.7.4
^ permalink raw reply related [flat|nested] 14+ messages in thread* [platforms: PATCH v2 6/9] Marvell/Armada7k8k: Add common ACPI tables
2018-08-07 8:58 [platforms: PATCH v2 0/9] Armada7k8k DT/ACPI support Marcin Wojtas
` (4 preceding siblings ...)
2018-08-07 8:58 ` [platforms: PATCH v2 5/9] Marvell/Armada80x0McBin: " Marcin Wojtas
@ 2018-08-07 8:58 ` Marcin Wojtas
2018-08-07 8:58 ` [platforms: PATCH v2 7/9] Marvell/Armada70x0Db: Enable ACPI support Marcin Wojtas
` (3 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Marcin Wojtas @ 2018-08-07 8:58 UTC (permalink / raw)
To: edk2-devel; +Cc: leif.lindholm, ard.biesheuvel, nadavh, mw, jsd, jaz
This patch adds ACPI tables and necessary headers,
which are common for Armada7k8k SoCs. Per-board
tables and wiring up of support will be done in
the follow-up commits.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
| 45 ++++
Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h | 42 ++++
Silicon/Marvell/Armada7k8k/AcpiTables/Fadt.aslc | 86 ++++++++
Silicon/Marvell/Armada7k8k/AcpiTables/Gtdt.aslc | 64 ++++++
Silicon/Marvell/Armada7k8k/AcpiTables/Madt.aslc | 139 +++++++++++++
Silicon/Marvell/Armada7k8k/AcpiTables/Pptt.aslc | 216 ++++++++++++++++++++
Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc | 53 +++++
7 files changed, 645 insertions(+)
create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/AcpiHeader.h
create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h
create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Fadt.aslc
create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Gtdt.aslc
create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Madt.aslc
create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Pptt.aslc
create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc
--git a/Silicon/Marvell/Armada7k8k/AcpiTables/AcpiHeader.h b/Silicon/Marvell/Armada7k8k/AcpiTables/AcpiHeader.h
new file mode 100644
index 0000000..f5ebd27
--- /dev/null
+++ b/Silicon/Marvell/Armada7k8k/AcpiTables/AcpiHeader.h
@@ -0,0 +1,45 @@
+/** @file
+
+ Multiple APIC Description Table (MADT)
+
+ Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+ Copyright (C) 2018, Marvell International Ltd. and its affiliates.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <IndustryStandard/Acpi.h>
+
+#define ACPI_OEM_ID_ARRAY {'M','V','E','B','U',' '}
+#define ACPI_OEM_REVISION 0
+#define ACPI_CREATOR_ID SIGNATURE_32('L','N','R','O')
+#define ACPI_CREATOR_REVISION 0
+
+#if defined(ARMADA7K)
+#define ACPI_OEM_TABLE_ID SIGNATURE_64('A','R','M','A','D','A','7','K')
+#elif defined (ARMADA8K)
+#define ACPI_OEM_TABLE_ID SIGNATURE_64('A','R','M','A','D','A','8','K')
+#endif
+
+/**
+ * A macro to initialize the common header part of EFI ACPI tables
+ * as defined by EFI_ACPI_DESCRIPTION_HEADER structure.
+ **/
+#define __ACPI_HEADER(sign, type, rev) { \
+ sign, /* UINT32 Signature */ \
+ sizeof (type), /* UINT32 Length */ \
+ rev, /* UINT8 Revision */ \
+ 0, /* UINT8 Checksum */ \
+ ACPI_OEM_ID_ARRAY, /* UINT8 OemId[6] */ \
+ ACPI_OEM_TABLE_ID, /* UINT64 OemTableId */ \
+ ACPI_OEM_REVISION, /* UINT32 OemRevision */ \
+ ACPI_CREATOR_ID, /* UINT32 CreatorId */ \
+ ACPI_CREATOR_REVISION /* UINT32 CreatorRevision */ \
+ }
diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h b/Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h
new file mode 100644
index 0000000..5746ad4
--- /dev/null
+++ b/Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h
@@ -0,0 +1,42 @@
+/**
+
+ Copyright (C) 2018, Marvell International Ltd. and its affiliates.
+
+ This program and the accompanying materials are licensed and made available
+ under the terms and conditions of the BSD License which accompanies this
+ distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Glossary - abbreviations used in Marvell SampleAtReset library implementation:
+ ICU - Interrupt Consolidation Unit
+ AP - Application Processor hardware block (Armada 7k8k incorporates AP806)
+ CP - South Bridge hardware blocks (Armada 7k8k incorporates CP110)
+
+**/
+
+#define CP_GIC_SPI_CP0_PCI0 64
+#define CP_GIC_SPI_CP0_PCI1 65
+#define CP_GIC_SPI_CP0_PCI2 66
+#define CP_GIC_SPI_CP0_SDMMC 67
+#define CP_GIC_SPI_PP2_CP0_PORT0 69, 72, 75, 78, 81, 127
+#define CP_GIC_SPI_PP2_CP0_PORT1 70, 73, 76, 79, 82, 126
+#define CP_GIC_SPI_PP2_CP0_PORT2 71, 74, 77, 80, 83, 125
+#define CP_GIC_SPI_CP0_EIP_RNG0 105
+#define CP_GIC_SPI_CP0_USB_H1 112
+#define CP_GIC_SPI_CP0_USB_H0 113
+#define CP_GIC_SPI_CP0_SATA_H0 114
+
+#define CP_GIC_SPI_CP1_PCI0 288
+#define CP_GIC_SPI_CP1_PCI1 289
+#define CP_GIC_SPI_CP1_PCI2 290
+#define CP_GIC_SPI_CP1_SDMMC 291
+#define CP_GIC_SPI_PP2_CP1_PORT0 293, 296, 299, 302, 305, 351
+#define CP_GIC_SPI_PP2_CP1_PORT1 294, 297, 300, 303, 306, 350
+#define CP_GIC_SPI_PP2_CP1_PORT2 295, 298, 301, 304, 307, 349
+#define CP_GIC_SPI_CP1_EIP_RNG0 329
+#define CP_GIC_SPI_CP1_USB_H1 336
+#define CP_GIC_SPI_CP1_USB_H0 337
+#define CP_GIC_SPI_CP1_SATA_H0 338
diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Fadt.aslc b/Silicon/Marvell/Armada7k8k/AcpiTables/Fadt.aslc
new file mode 100644
index 0000000..de88210
--- /dev/null
+++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Fadt.aslc
@@ -0,0 +1,86 @@
+/** @file
+
+ Fixed ACPI Description Table (FADT)
+
+ Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+ Copyright (C) 2018, Marvell International Ltd. and its affiliates.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/AcpiLib.h>
+
+#include "AcpiHeader.h"
+
+#define FADT_FLAGS EFI_ACPI_6_0_HW_REDUCED_ACPI | \
+ EFI_ACPI_6_0_LOW_POWER_S0_IDLE_CAPABLE | \
+ EFI_ACPI_6_0_HEADLESS
+
+EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
+ __ACPI_HEADER (EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE,
+ EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION),
+ 0, // UINT32 FirmwareCtrl
+ 0, // UINT32 Dsdt
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0
+ EFI_ACPI_6_0_PM_PROFILE_ENTERPRISE_SERVER, // UINT8 PreferredPmProfile
+ 0, // UINT16 SciInt
+ 0, // UINT32 SmiCmd
+ 0, // UINT8 AcpiEnable
+ 0, // UINT8 AcpiDisable
+ 0, // UINT8 S4BiosReq
+ 0, // UINT8 PstateCnt
+ 0, // UINT32 Pm1aEvtBlk
+ 0, // UINT32 Pm1bEvtBlk
+ 0, // UINT32 Pm1aCntBlk
+ 0, // UINT32 Pm1bCntBlk
+ 0, // UINT32 Pm2CntBlk
+ 0, // UINT32 PmTmrBlk
+ 0, // UINT32 Gpe0Blk
+ 0, // UINT32 Gpe1Blk
+ 0, // UINT8 Pm1EvtLen
+ 0, // UINT8 Pm1CntLen
+ 0, // UINT8 Pm2CntLen
+ 0, // UINT8 PmTmrLen
+ 0, // UINT8 Gpe0BlkLen
+ 0, // UINT8 Gpe1BlkLen
+ 0, // UINT8 Gpe1Base
+ 0, // UINT8 CstCnt
+ 0, // UINT16 PLvl2Lat
+ 0, // UINT16 PLvl3Lat
+ 0, // UINT16 FlushSize
+ 0, // UINT16 FlushStride
+ 0, // UINT8 DutyOffset
+ 0, // UINT8 DutyWidth
+ 0, // UINT8 DayAlrm
+ 0, // UINT8 MonAlrm
+ 0, // UINT8 Century
+ 0, // UINT16 IaPcBootArch
+ 0, // UINT8 Reserved1
+ FADT_FLAGS, // UINT32 Flags
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE ResetReg
+ 0, // UINT8 ResetValue
+ EFI_ACPI_6_0_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArch
+ EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorVersion
+ 0, // UINT64 XFirmwareCtrl
+ 0, // UINT64 XDsdt
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg
+ NULL_GAS // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg
+};
+
+VOID CONST * CONST ReferenceAcpiTable = &Fadt;
diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Gtdt.aslc b/Silicon/Marvell/Armada7k8k/AcpiTables/Gtdt.aslc
new file mode 100644
index 0000000..16a8806
--- /dev/null
+++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Gtdt.aslc
@@ -0,0 +1,64 @@
+/** @file
+
+ Multiple APIC Description Table (MADT)
+
+ Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+ Copyright (C) 2018, Marvell International Ltd. and its affiliates.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/AcpiLib.h>
+
+#include "AcpiHeader.h"
+
+// active low, level triggered
+#define GTDT_GTIMER_FLAGS EFI_ACPI_6_0_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY
+
+// active high, level triggered
+#define GTDT_WDG_FLAGS 0x0
+
+#pragma pack(1)
+typedef struct {
+ EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE Header;
+ EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE SbsaWatchdog;
+} ACPI_6_0_GTDT_STRUCTURE;
+#pragma pack()
+
+ACPI_6_0_GTDT_STRUCTURE Gtdt = {
+ {
+ __ACPI_HEADER (EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
+ ACPI_6_0_GTDT_STRUCTURE,
+ EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION),
+ 0xFFFFFFFFFFFFFFFF, // UINT64 PhysicalAddress
+ 0, // UINT32 Reserved
+ FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecureEL1TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 SecureEL1TimerFlags
+ FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecureEL1TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 NonSecureEL1TimerFlags
+ FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags
+ FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecureEL2TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 NonSecureEL2TimerFlags
+ 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBaseAddress
+ 0x1, // UINT32 PlatformTimerCount
+ sizeof (Gtdt.Header) // UINT32 PlatformTimerOffset
+ }, {
+ EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG, // UINT8 Type
+ sizeof (Gtdt.SbsaWatchdog), // UINT16 Length
+ 0x0, // UINT8 Reserved
+ FixedPcdGet64 (PcdGenericWatchdogRefreshBase), // UINT64 RefreshFramePhysicalAddress
+ FixedPcdGet64 (PcdGenericWatchdogControlBase), // UINT64 WatchdogControlFramePhysicalAddress
+ FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum), // UINT32 WatchdogTimerGSIV
+ GTDT_WDG_FLAGS // UINT32 WatchdogTimerFlags
+ },
+};
+
+VOID CONST * CONST ReferenceAcpiTable = &Gtdt;
diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Madt.aslc b/Silicon/Marvell/Armada7k8k/AcpiTables/Madt.aslc
new file mode 100644
index 0000000..3dae5d3
--- /dev/null
+++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Madt.aslc
@@ -0,0 +1,139 @@
+/** @file
+
+ Multiple APIC Description Table (MADT)
+
+ Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+ Copyright (C) 2018, Marvell International Ltd. and its affiliates.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/AcpiLib.h>
+
+#include "AcpiHeader.h"
+
+#define GICC_BASE FixedPcdGet64 (PcdGicInterruptInterfaceBase)
+#define GICD_BASE FixedPcdGet64 (PcdGicDistributorBase)
+#define GICH_BASE 0xF0240000
+#define GICV_BASE 0xF0260000
+#define VGIC_MAINT_INT 25 // SPI #9
+
+#define GIC_MSI_FRAME0 0xF0280000
+#define GIC_MSI_FRAME1 0xF0290000
+#define GIC_MSI_FRAME2 0xF02A0000
+#define GIC_MSI_FRAME3 0xF02B0000
+
+#define PMU_INTERRUPT_CPU0 130
+#define PMU_INTERRUPT_CPU1 131
+#define PMU_INTERRUPT_CPU2 132
+#define PMU_INTERRUPT_CPU3 133
+
+#pragma pack(push, 1)
+typedef struct {
+ EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_0_GIC_STRUCTURE GicC[4];
+ EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE GicD;
+ EFI_ACPI_6_0_GIC_MSI_FRAME_STRUCTURE GicM[4];
+} ACPI_6_0_MADT_STRUCTURE;
+#pragma pack(pop)
+
+
+ACPI_6_0_MADT_STRUCTURE Madt = {
+ {
+ __ACPI_HEADER (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ ACPI_6_0_MADT_STRUCTURE,
+ EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION),
+ 0, // UINT32 LocalApicAddress
+ 0 // UINT32 Flags
+ },
+ {
+ EFI_ACPI_6_0_GICC_STRUCTURE_INIT(0, // GicId
+ 0x000, // AcpiCpuUid
+ 0x000, // Mpidr
+ EFI_ACPI_6_0_GIC_ENABLED, // Flags
+ PMU_INTERRUPT_CPU0, // PmuIrq
+ GICC_BASE, // GicBase
+ GICV_BASE, // GicVBase
+ GICH_BASE, // GicHBase
+ VGIC_MAINT_INT, // GsivId
+ 0, // GicRBase
+ 0 // Efficiency
+ ),
+ EFI_ACPI_6_0_GICC_STRUCTURE_INIT(1, // GicId
+ 0x001, // AcpiCpuUid
+ 0x001, // Mpidr
+ EFI_ACPI_6_0_GIC_ENABLED, // Flags
+ PMU_INTERRUPT_CPU1, // PmuIrq
+ GICC_BASE, // GicBase
+ GICV_BASE, // GicVBase
+ GICH_BASE, // GicHBase
+ VGIC_MAINT_INT, // GsivId
+ 0, // GicRBase
+ 0 // Efficiency
+ ),
+ EFI_ACPI_6_0_GICC_STRUCTURE_INIT(2, // GicId
+ 0x100, // AcpiCpuUid
+ 0x100, // Mpidr
+ EFI_ACPI_6_0_GIC_ENABLED, // Flags
+ PMU_INTERRUPT_CPU2, // PmuIrq
+ GICC_BASE, // GicBase
+ GICV_BASE, // GicVBase
+ GICH_BASE, // GicHBase
+ VGIC_MAINT_INT, // GsivId
+ 0, // GicRBase
+ 0 // Efficiency
+ ),
+ EFI_ACPI_6_0_GICC_STRUCTURE_INIT(3, // GicId
+ 0x101, // AcpiCpuUid
+ 0x101, // Mpidr
+ EFI_ACPI_6_0_GIC_ENABLED, // Flags
+ PMU_INTERRUPT_CPU3, // PmuIrq
+ GICC_BASE, // GicBase
+ GICV_BASE, // GicVBase
+ GICH_BASE, // GicHBase
+ VGIC_MAINT_INT, // GsivId
+ 0, // GicRBase
+ 0 // Efficiency
+ ),
+ },
+ EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0x0, // GicDistHwId
+ GICD_BASE, // GicDistBase
+ 0x0, // GicDistVector
+ EFI_ACPI_6_0_GIC_V2 // GicVersion
+ ),
+ {
+ EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0x0, // GicMsiFrameId
+ GIC_MSI_FRAME0, // BaseAddress
+ 0, // Flags
+ 0, // SPICount
+ 0 // SPIBase
+ ),
+ EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0x1, // GicMsiFrameId
+ GIC_MSI_FRAME1, // BaseAddress
+ 0, // Flags
+ 0, // SPICount
+ 0 // SPIBase
+ ),
+ EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0x2, // GicMsiFrameId
+ GIC_MSI_FRAME2, // BaseAddress
+ 0, // Flags
+ 0, // SPICount
+ 0 // SPIBase
+ ),
+ EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0x3, // GicMsiFrameId
+ GIC_MSI_FRAME3, // BaseAddress
+ 0, // Flags
+ 0, // SPICount
+ 0 // SPIBase
+ ),
+ }
+};
+
+VOID CONST * CONST ReferenceAcpiTable = &Madt;
diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Pptt.aslc b/Silicon/Marvell/Armada7k8k/AcpiTables/Pptt.aslc
new file mode 100644
index 0000000..8de29bd3
--- /dev/null
+++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Pptt.aslc
@@ -0,0 +1,216 @@
+/** @file
+
+ Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR>
+ Copyright (c) 2018, Marvell International Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available
+ under the terms and conditions of the BSD License which accompanies this
+ distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <IndustryStandard/Acpi.h>
+
+#include "AcpiHeader.h"
+
+#define NUM_CORES FixedPcdGet64 (PcdCoreCount)
+
+#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name)
+
+#pragma pack(1)
+typedef struct {
+ EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Core;
+ UINT32 Offset[2];
+ EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE DCache;
+ EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE ICache;
+} ACPI_6_2_PPTT_CORE;
+
+typedef struct {
+ EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Cluster;
+ UINT32 Offset[1];
+ EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L2Cache;
+ ACPI_6_2_PPTT_CORE Cores[2];
+} ACPI_6_2_PPTT_CLUSTER;
+
+typedef struct {
+ EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Package;
+ UINT32 Offset[1];
+ EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L3Cache;
+ ACPI_6_2_PPTT_CLUSTER Clusters[NUM_CORES / 2];
+} ACPI_6_2_PPTT_PACKAGE;
+
+typedef struct {
+ EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Pptt;
+ ACPI_6_2_PPTT_PACKAGE Packages[1];
+} ACPI_6_2_PPTT_STRUCTURE;
+#pragma pack()
+
+#define PPTT_CORE(pid, cid, id) { \
+ { \
+ EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, \
+ FIELD_OFFSET (ACPI_6_2_PPTT_CORE, DCache), \
+ {}, \
+ { \
+ 0, /* PhysicalPackage */ \
+ EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID, /* AcpiProcessorIdValid */ \
+ }, \
+ FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, \
+ Packages[pid].Clusters[cid]), /* Parent */ \
+ 256 * (cid) + (id), /* AcpiProcessorId */ \
+ 2, /* NumberOfPrivateResources */ \
+ }, { \
+ FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, \
+ Packages[pid].Clusters[cid].Cores[id].DCache), \
+ FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, \
+ Packages[pid].Clusters[cid].Cores[id].ICache), \
+ }, { \
+ EFI_ACPI_6_2_PPTT_TYPE_CACHE, \
+ sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \
+ {}, \
+ { \
+ 1, /* SizePropertyValid */ \
+ 1, /* NumberOfSetsValid */ \
+ 1, /* AssociativityValid */ \
+ 1, /* AllocationTypeValid */ \
+ 1, /* CacheTypeValid */ \
+ 1, /* WritePolicyValid */ \
+ 1, /* LineSizeValid */ \
+ }, \
+ 0, /* NextLevelOfCache */ \
+ SIZE_32KB, /* Size */ \
+ 256, /* NumberOfSets */ \
+ 2, /* Associativity */ \
+ { \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \
+ }, \
+ 64 /* LineSize */ \
+ }, { \
+ EFI_ACPI_6_2_PPTT_TYPE_CACHE, \
+ sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \
+ {}, \
+ { \
+ 1, /* SizePropertyValid */ \
+ 1, /* NumberOfSetsValid */ \
+ 1, /* AssociativityValid */ \
+ 1, /* AllocationTypeValid */ \
+ 1, /* CacheTypeValid */ \
+ 0, /* WritePolicyValid */ \
+ 1, /* LineSizeValid */ \
+ }, \
+ 0, /* NextLevelOfCache */ \
+ 3 * SIZE_16KB, /* Size */ \
+ 256, /* NumberOfSets */ \
+ 3, /* Associativity */ \
+ { \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ, /* AllocationType */ \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, \
+ 0, /* WritePolicy */ \
+ }, \
+ 64 /* LineSize */ \
+ } \
+}
+
+#define PPTT_CLUSTER(pid, cid) { \
+ { \
+ EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, \
+ FIELD_OFFSET (ACPI_6_2_PPTT_CLUSTER, L2Cache), \
+ {}, \
+ { \
+ 0, /* PhysicalPackage */ \
+ EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ \
+ }, \
+ FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, Packages[pid]), /* Parent */ \
+ 0, /* AcpiProcessorId */ \
+ 1, /* NumberOfPrivateResources */ \
+ }, { \
+ FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, Packages[pid].Clusters[cid].L2Cache), \
+ }, { \
+ EFI_ACPI_6_2_PPTT_TYPE_CACHE, \
+ sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \
+ {}, \
+ { \
+ 1, /* SizePropertyValid */ \
+ 1, /* NumberOfSetsValid */ \
+ 1, /* AssociativityValid */ \
+ 1, /* AllocationTypeValid */ \
+ 1, /* CacheTypeValid */ \
+ 1, /* WritePolicyValid */ \
+ 1, /* LineSizeValid */ \
+ }, \
+ 0, /* NextLevelOfCache */ \
+ SIZE_512KB, /* Size */ \
+ 256, /* NumberOfSets */ \
+ 16, /* Associativity */ \
+ { \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \
+ }, \
+ 64 /* LineSize */ \
+ }, { \
+ PPTT_CORE(pid, cid, 0), \
+ PPTT_CORE(pid, cid, 1), \
+ } \
+}
+
+ACPI_6_2_PPTT_STRUCTURE Pptt = {
+ {
+ __ACPI_HEADER(EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ ACPI_6_2_PPTT_STRUCTURE,
+ EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION),
+ },
+ {
+ {
+ {
+ EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR,
+ FIELD_OFFSET (ACPI_6_2_PPTT_PACKAGE, L3Cache),
+ {},
+ {
+ 1, /* PhysicalPackage */
+ EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */
+ },
+ 0, /* Parent */
+ 0, /* AcpiProcessorId */
+ 1, /* NumberOfPrivateResources */
+ }, {
+ FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, Packages[0].L3Cache),
+ }, {
+ EFI_ACPI_6_2_PPTT_TYPE_CACHE,
+ sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE),
+ {},
+ {
+ 1, /* SizePropertyValid */
+ 1, /* NumberOfSetsValid */
+ 1, /* AssociativityValid */
+ 1, /* AllocationTypeValid */
+ 1, /* CacheTypeValid */
+ 1, /* WritePolicyValid */
+ 1, /* LineSizeValid */
+ },
+ 0, /* NextLevelOfCache */
+ SIZE_1MB, /* Size */
+ 2048, /* NumberOfSets */
+ 8, /* Associativity */
+ {
+ 0, /* AllocationType */
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED,
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK,
+ },
+ 64 /* LineSize */
+ }, {
+ PPTT_CLUSTER (0, 0),
+#if NUM_CORES > 3
+ PPTT_CLUSTER (0, 1),
+#endif
+ }
+ }
+ }
+};
+
+VOID * CONST ReferenceAcpiTable = &Pptt;
diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc b/Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc
new file mode 100644
index 0000000..e78bb90
--- /dev/null
+++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc
@@ -0,0 +1,53 @@
+/** @file
+ Serial Port Console Redirection Table (SPCR)
+
+ Copyright (c) 2017, Linaro Limited. All rights reserved.
+ Copyright (C) 2018, Marvell International Ltd. and its affiliates.
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
+#include <Library/AcpiLib.h>
+
+#include "AcpiHeader.h"
+
+EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = {
+ __ACPI_HEADER(EFI_ACPI_6_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE,
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION
+ ),
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_16550, // InterfaceType
+ { EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE }, // Reserved1[3]
+ ARM_GAS32 (FixedPcdGet64(PcdSerialRegisterBase)), // BaseAddress
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC, // InterruptType
+ 0, // Irq
+ 51, // GlobalSystemInterrupt
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200, // BaudRate
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY, // Parity
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1, // StopBits
+ 0, // FlowControl
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI, // TerminalType
+ EFI_ACPI_RESERVED_BYTE, // Language
+ 0xFFFF, // PciDeviceId
+ 0xFFFF, // PciVendorId
+ 0, // PciBusNumber
+ 0, // PciDeviceNumber
+ 0, // PciFunctionNumber
+ 0, // PciFlags
+ 0, // PciSegment
+ EFI_ACPI_RESERVED_DWORD // Reserved2
+};
+
+VOID CONST * CONST ReferenceAcpiTable = &Spcr;
--
2.7.4
^ permalink raw reply related [flat|nested] 14+ messages in thread* [platforms: PATCH v2 7/9] Marvell/Armada70x0Db: Enable ACPI support
2018-08-07 8:58 [platforms: PATCH v2 0/9] Armada7k8k DT/ACPI support Marcin Wojtas
` (5 preceding siblings ...)
2018-08-07 8:58 ` [platforms: PATCH v2 6/9] Marvell/Armada7k8k: Add common ACPI tables Marcin Wojtas
@ 2018-08-07 8:58 ` Marcin Wojtas
2018-08-07 8:58 ` [platforms: PATCH v2 8/9] Marvell/Armada80x0Db: " Marcin Wojtas
` (2 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Marcin Wojtas @ 2018-08-07 8:58 UTC (permalink / raw)
To: edk2-devel; +Cc: leif.lindholm, ard.biesheuvel, nadavh, mw, jsd, jaz
This patch introduces DSDT table and adds necessary
wiring in order to enable ACPI support on Armada 7040 DB.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 14 ++
Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc | 3 +
Silicon/Marvell/Armada7k8k/Armada7k8k.fdf | 12 +
Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db.inf | 61 ++++++
Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf.inc | 5 +
Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl | 229 ++++++++++++++++++++
Silicon/Marvell/Documentation/PortingGuide.txt | 22 ++
7 files changed, 346 insertions(+)
create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db.inf
create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl
diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
index f1ccda0..d4c67a2 100644
--- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
+++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
@@ -593,6 +593,20 @@
ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
!endif #$(INCLUDE_TFTP_COMMAND)
+[Components.AARCH64]
+ #
+ # Generic ACPI modules
+ #
+ MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf {
+ <LibraryClasses>
+ PlatformHasAcpiLib|EmbeddedPkg/Library/PlatformHasAcpiLib/PlatformHasAcpiLib.inf
+
+ <PcdsFixedAtBuild>
+ # support ACPI v5.0 or later
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20
+ }
+
[BuildOptions.common.EDKII.DXE_CORE,BuildOptions.common.EDKII.DXE_DRIVER,BuildOptions.common.EDKII.UEFI_DRIVER,BuildOptions.common.EDKII.UEFI_APPLICATION]
GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc
index d3dffb0..e0bf447 100644
--- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc
+++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc
@@ -51,6 +51,9 @@
[Components.common]
Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf
+[Components.AARCH64]
+ Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db.inf
+
################################################################################
#
# Pcd Section - list of all EDK II PCD Entries defined by this Platform
diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf b/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
index 909ad3e..c064a43 100644
--- a/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
+++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
@@ -215,6 +215,12 @@ FvNameGuid = 5eda4200-2c5f-43cb-9da3-0baf74b1b30c
# DTB
INF EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf
+!if $(ARCH) == AARCH64
+ # ACPI support
+ INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+!endif
+
!include $(BOARD_DXE_FV_COMPONENTS)
# PEI phase firmware volume
@@ -408,3 +414,9 @@ READ_LOCK_STATUS = TRUE
FILE FREEFORM = $(NAMED_GUID) {
RAW BIN |.dtb
}
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+ FILE FREEFORM = $(NAMED_GUID) {
+ RAW ASL |.aml
+ RAW ACPI |.acpi
+ }
diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db.inf b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db.inf
new file mode 100644
index 0000000..659c333
--- /dev/null
+++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db.inf
@@ -0,0 +1,61 @@
+## @file
+# Component description file for PlatformAcpiTables module.
+#
+# ACPI table data and ASL sources required to boot the platform.
+#
+# Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+# Copyright (C) 2018, Marvell International Ltd. and its affiliates.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = PlatformAcpiTables
+ FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ Armada70x0Db/Dsdt.asl
+ Fadt.aslc
+ Gtdt.aslc
+ Madt.aslc
+ Pptt.aslc
+ Spcr.aslc
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Marvell/Marvell.dec
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+
+ gArmPlatformTokenSpaceGuid.PcdCoreCount
+
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+
+ gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
+ gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
+ gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate
+
+[BuildOptions]
+ *_*_*_ASLCC_FLAGS = -DARMADA7K
diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf.inc b/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf.inc
index b4c3e20..b7e7a65 100644
--- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf.inc
+++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf.inc
@@ -14,3 +14,8 @@
# DTB
INF RuleOverride = DTB Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf
+
+!if $(ARCH) == AARCH64
+ # ACPI support
+ INF RuleOverride = ACPITABLE Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db.inf
+!endif
diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl
new file mode 100644
index 0000000..621b688
--- /dev/null
+++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl
@@ -0,0 +1,229 @@
+/** @file
+
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR>
+ Copyright (C) 2018, Marvell International Ltd. and its affiliates.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "IcuInterrupts.h"
+
+DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3)
+{
+ Scope (_SB)
+ {
+ Device (CPU0)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x000) // _UID: Unique ID
+ }
+ Device (CPU1)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x001) // _UID: Unique ID
+ }
+ Device (CPU2)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x100) // _UID: Unique ID
+ }
+ Device (CPU3)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x101) // _UID: Unique ID
+ }
+
+ Device (AHC0)
+ {
+ Name (_HID, "LNRO001E") // _HID: Hardware ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Name (_CLS, Package (0x03) // _CLS: Class Code
+ {
+ 0x01,
+ 0x06,
+ 0x01
+ })
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xF2540000, // Address Base (MMIO)
+ 0x00030000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_CP0_SATA_H0
+ }
+ })
+ }
+
+ Device (XHC0)
+ {
+ Name (_HID, "PNP0D10") // _HID: Hardware ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xF2500000, // Address Base (MMIO)
+ 0x00004000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_CP0_USB_H0
+ }
+ })
+ }
+
+ Device (XHC1)
+ {
+ Name (_HID, "PNP0D10") // _HID: Hardware ID
+ Name (_UID, 0x01) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xF2510000, // Address Base (MMIO)
+ 0x00004000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_CP0_USB_H1
+ }
+ })
+ }
+
+ Device (COM1)
+ {
+ Name (_HID, "HISI0031") // _HID: Hardware ID
+ Name (_CID, "8250dw") // _CID: Compatible ID
+ Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ FixedPcdGet64(PcdSerialRegisterBase), // Address Base
+ 0x00000100, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 51
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "clock-frequency", FixedPcdGet32 (PcdSerialClockRate) },
+ Package () { "reg-io-width", 1 },
+ Package () { "reg-shift", 2 },
+ }
+ })
+ }
+
+ Device (PP20)
+ {
+ Name (_HID, "MRVL0110") // _HID: Hardware ID
+ Name (_CCA, 0x01) // Cache-coherent controller
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000)
+ Memory32Fixed (ReadWrite, 0xf2129000 , 0xb000)
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "clock-frequency", 333333333 },
+ }
+ })
+ Device (ETH0)
+ {
+ Name (_ADR, 0x0)
+ Name (_CRS, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_PP2_CP0_PORT0
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "port-id", 0 },
+ Package () { "gop-port-id", 0 },
+ Package () { "phy-mode", "10gbase-kr"},
+ }
+ })
+ }
+ Device (ETH1)
+ {
+ Name (_ADR, 0x0)
+ Name (_CRS, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_PP2_CP0_PORT1
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "port-id", 1 },
+ Package () { "gop-port-id", 2 },
+ Package () { "phy-mode", "sgmii"},
+ }
+ })
+ }
+ Device (ETH2)
+ {
+ Name (_ADR, 0x0)
+ Name (_CRS, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_PP2_CP0_PORT2
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "port-id", 2 },
+ Package () { "gop-port-id", 3 },
+ Package () { "phy-mode", "rgmii-id"},
+ }
+ })
+ }
+ }
+
+ Device (RNG0)
+ {
+ Name (_HID, "PRP0001") // _HID: Hardware ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0xF2760000, 0x7D)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared)
+ {
+ CP_GIC_SPI_CP0_EIP_RNG0
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "compatible", "inside-secure,safexcel-eip76" },
+ }
+ })
+ }
+ }
+}
diff --git a/Silicon/Marvell/Documentation/PortingGuide.txt b/Silicon/Marvell/Documentation/PortingGuide.txt
index d5deed5..2603980 100644
--- a/Silicon/Marvell/Documentation/PortingGuide.txt
+++ b/Silicon/Marvell/Documentation/PortingGuide.txt
@@ -43,6 +43,28 @@ board. For the sake of simplicity new Marvell board will be called "new_board".
- Output files (and among others FD file, which may be used by ATF) are
generated under directory pointed by "OUTPUT_DIRECTORY" entry (see point 1.2).
+5. ACPI support (optional)
+ - The tables can be enabled as in A70x0Db example:
+
+ <path to edk2-platforms>/Platforms/Marvell/Armada/AcpiTables/Armada70x0Db/
+
+ - Enable compilation of the tables in the board's .dsc file. Add it to the
+ output flash image contents via .fdf.inc file - path to it defined as
+ BOARD_DXE_FV_COMPONENTS. Example:
+ Armada70x0Db.dsc:
+
+ BOARD_DXE_FV_COMPONENTS = Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf.inc
+
+ [Components.AARCH64]
+ Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/AcpiTables.inf
+
+ Armada70x0Db.fdf.inc:
+
+ !if $(ARCH) == AARCH64
+ # ACPI support
+ INF RuleOverride = ACPITABLE Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/AcpiTables.inf
+ !endif
+
COMPHY configuration
====================
--
2.7.4
^ permalink raw reply related [flat|nested] 14+ messages in thread* [platforms: PATCH v2 8/9] Marvell/Armada80x0Db: Enable ACPI support
2018-08-07 8:58 [platforms: PATCH v2 0/9] Armada7k8k DT/ACPI support Marcin Wojtas
` (6 preceding siblings ...)
2018-08-07 8:58 ` [platforms: PATCH v2 7/9] Marvell/Armada70x0Db: Enable ACPI support Marcin Wojtas
@ 2018-08-07 8:58 ` Marcin Wojtas
2018-08-07 8:58 ` [platforms: PATCH v2 9/9] Marvell/Armada80x0McBin: " Marcin Wojtas
2018-08-07 9:18 ` [platforms: PATCH v2 0/9] Armada7k8k DT/ACPI support Ard Biesheuvel
9 siblings, 0 replies; 14+ messages in thread
From: Marcin Wojtas @ 2018-08-07 8:58 UTC (permalink / raw)
To: edk2-devel; +Cc: leif.lindholm, ard.biesheuvel, nadavh, mw, jsd, jaz
This patch introduces DSDT table and adds necessary
wiring in order to enable ACPI support on Armada 8040 DB.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc | 3 +
Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf | 61 ++++
Platform/Marvell/Armada80x0Db/Armada80x0Db.fdf.inc | 5 +
Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl | 330 ++++++++++++++++++++
4 files changed, 399 insertions(+)
create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf
create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl
diff --git a/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc b/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc
index 3fc33d4..92e2dc8 100644
--- a/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc
+++ b/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc
@@ -51,6 +51,9 @@
[Components.common]
Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf
+[Components.AARCH64]
+ Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf
+
################################################################################
#
# Pcd Section - list of all EDK II PCD Entries defined by this Platform
diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf
new file mode 100644
index 0000000..35a679b
--- /dev/null
+++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf
@@ -0,0 +1,61 @@
+## @file
+# Component description file for PlatformAcpiTables module.
+#
+# ACPI table data and ASL sources required to boot the platform.
+#
+# Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+# Copyright (C) 2018, Marvell International Ltd. and its affiliates.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = PlatformAcpiTables
+ FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ Armada80x0Db/Dsdt.asl
+ Fadt.aslc
+ Gtdt.aslc
+ Madt.aslc
+ Pptt.aslc
+ Spcr.aslc
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Marvell/Marvell.dec
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+
+ gArmPlatformTokenSpaceGuid.PcdCoreCount
+
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+
+ gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
+ gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
+ gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate
+
+[BuildOptions]
+ *_*_*_ASLCC_FLAGS = -DARMADA8K
diff --git a/Platform/Marvell/Armada80x0Db/Armada80x0Db.fdf.inc b/Platform/Marvell/Armada80x0Db/Armada80x0Db.fdf.inc
index 99e1a11..81a81d0 100644
--- a/Platform/Marvell/Armada80x0Db/Armada80x0Db.fdf.inc
+++ b/Platform/Marvell/Armada80x0Db/Armada80x0Db.fdf.inc
@@ -14,3 +14,8 @@
# DTB
INF RuleOverride = DTB Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf
+
+!if $(ARCH) == AARCH64
+ # ACPI support
+ INF RuleOverride = ACPITABLE Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf
+!endif
diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl
new file mode 100644
index 0000000..7c65949
--- /dev/null
+++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl
@@ -0,0 +1,330 @@
+/** @file
+
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR>
+ Copyright (C) 2018, Marvell International Ltd. and its affiliates.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "IcuInterrupts.h"
+
+DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
+{
+ Scope (_SB)
+ {
+ Device (CPU0)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x000) // _UID: Unique ID
+ }
+ Device (CPU1)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x001) // _UID: Unique ID
+ }
+ Device (CPU2)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x100) // _UID: Unique ID
+ }
+ Device (CPU3)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x101) // _UID: Unique ID
+ }
+
+ Device (AHC0)
+ {
+ Name (_HID, "LNRO001E") // _HID: Hardware ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Name (_CLS, Package (0x03) // _CLS: Class Code
+ {
+ 0x01,
+ 0x06,
+ 0x01
+ })
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xF2540000, // Address Base (MMIO)
+ 0x00002000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_CP0_SATA_H0
+ }
+ })
+ }
+
+ Device (AHC1)
+ {
+ Name (_HID, "LNRO001E") // _HID: Hardware ID
+ Name (_UID, 0x01) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Name (_CLS, Package (0x03) // _CLS: Class Code
+ {
+ 0x01,
+ 0x06,
+ 0x01
+ })
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xF4540000, // Address Base (MMIO)
+ 0x00002000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_CP1_SATA_H0
+ }
+ })
+ }
+
+ Device (XHC0)
+ {
+ Name (_HID, "PNP0D10") // _HID: Hardware ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xF2500000, // Address Base (MMIO)
+ 0x00004000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_CP0_USB_H0
+ }
+ })
+ }
+
+ Device (XHC1)
+ {
+ Name (_HID, "PNP0D10") // _HID: Hardware ID
+ Name (_UID, 0x01) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xF2510000, // Address Base (MMIO)
+ 0x00004000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_CP0_USB_H1
+ }
+ })
+ }
+
+ Device (XHC2)
+ {
+ Name (_HID, "PNP0D10") // _HID: Hardware ID
+ Name (_UID, 0x02) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xF4500000, // Address Base (MMIO)
+ 0x00004000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_CP1_USB_H0
+ }
+ })
+ }
+
+ Device (COM1)
+ {
+ Name (_HID, "HISI0031") // _HID: Hardware ID
+ Name (_CID, "8250dw") // _CID: Compatible ID
+ Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ FixedPcdGet64(PcdSerialRegisterBase), // Address Base
+ 0x00000100, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 51
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "clock-frequency", FixedPcdGet32 (PcdSerialClockRate) },
+ Package () { "reg-io-width", 1 },
+ Package () { "reg-shift", 2 },
+ }
+ })
+ }
+
+ Device (PP20)
+ {
+ Name (_HID, "MRVL0110") // _HID: Hardware ID
+ Name (_CCA, 0x01) // Cache-coherent controller
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000)
+ Memory32Fixed (ReadWrite, 0xf2129000 , 0xb000)
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "clock-frequency", 333333333 },
+ }
+ })
+ Device (ETH0)
+ {
+ Name (_ADR, 0x0)
+ Name (_CRS, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_PP2_CP0_PORT0
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "port-id", 0 },
+ Package () { "gop-port-id", 0 },
+ Package () { "phy-mode", "10gbase-kr"},
+ }
+ })
+ }
+ Device (ETH2)
+ {
+ Name (_ADR, 0x0)
+ Name (_CRS, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_PP2_CP0_PORT2
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "port-id", 2 },
+ Package () { "gop-port-id", 3 },
+ Package () { "phy-mode", "rgmii-id"},
+ }
+ })
+ }
+ }
+
+ Device (PP21)
+ {
+ Name (_HID, "MRVL0110") // _HID: Hardware ID
+ Name (_CCA, 0x01) // Cache-coherent controller
+ Name (_UID, 0x01) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000)
+ Memory32Fixed (ReadWrite, 0xf4129000 , 0xb000)
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "clock-frequency", 333333333 },
+ }
+ })
+ Device (ETH0)
+ {
+ Name (_ADR, 0x0)
+ Name (_CRS, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_PP2_CP1_PORT0
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "port-id", 0 },
+ Package () { "gop-port-id", 0 },
+ Package () { "phy-mode", "10gbase-kr"},
+ }
+ })
+ }
+ Device (ETH1)
+ {
+ Name (_ADR, 0x0)
+ Name (_CRS, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_PP2_CP1_PORT1
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "port-id", 1 },
+ Package () { "gop-port-id", 2 },
+ Package () { "phy-mode", "rgmii-id"},
+ }
+ })
+ }
+ }
+
+ Device (RNG0)
+ {
+ Name (_HID, "PRP0001") // _HID: Hardware ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0xF2760000, 0x7D)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared)
+ {
+ CP_GIC_SPI_CP0_EIP_RNG0
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "compatible", "inside-secure,safexcel-eip76" },
+ }
+ })
+ }
+
+ Device (RNG1)
+ {
+ Name (_HID, "PRP0001") // _HID: Hardware ID
+ Name (_UID, 0x01) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0xF4760000, 0x7D)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared)
+ {
+ CP_GIC_SPI_CP1_EIP_RNG0
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "compatible", "inside-secure,safexcel-eip76" },
+ }
+ })
+ }
+ }
+}
--
2.7.4
^ permalink raw reply related [flat|nested] 14+ messages in thread* [platforms: PATCH v2 9/9] Marvell/Armada80x0McBin: Enable ACPI support
2018-08-07 8:58 [platforms: PATCH v2 0/9] Armada7k8k DT/ACPI support Marcin Wojtas
` (7 preceding siblings ...)
2018-08-07 8:58 ` [platforms: PATCH v2 8/9] Marvell/Armada80x0Db: " Marcin Wojtas
@ 2018-08-07 8:58 ` Marcin Wojtas
2018-08-07 9:18 ` [platforms: PATCH v2 0/9] Armada7k8k DT/ACPI support Ard Biesheuvel
9 siblings, 0 replies; 14+ messages in thread
From: Marcin Wojtas @ 2018-08-07 8:58 UTC (permalink / raw)
To: edk2-devel; +Cc: leif.lindholm, ard.biesheuvel, nadavh, mw, jsd, jaz
This patch introduces DSDT table and adds necessary wiring
in order to enable ACPI support on Armada 8040 MacchiatoBin.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc | 3 +
Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf | 61 ++++
Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.fdf.inc | 4 +
Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl | 310 ++++++++++++++++++++
4 files changed, 378 insertions(+)
create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf
create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl
diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
index e6cb0d6..52e2b9b 100644
--- a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
+++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
@@ -52,6 +52,9 @@
[Components.common]
Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf
+[Components.AARCH64]
+ Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf
+
################################################################################
#
# Pcd Section - list of all EDK II PCD Entries defined by this Platform
diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf
new file mode 100644
index 0000000..9e52281
--- /dev/null
+++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf
@@ -0,0 +1,61 @@
+## @file
+# Component description file for PlatformAcpiTables module.
+#
+# ACPI table data and ASL sources required to boot the platform.
+#
+# Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+# Copyright (C) 2018, Marvell International Ltd. and its affiliates.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = PlatformAcpiTables
+ FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ Armada80x0McBin/Dsdt.asl
+ Fadt.aslc
+ Gtdt.aslc
+ Madt.aslc
+ Pptt.aslc
+ Spcr.aslc
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Marvell/Marvell.dec
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+
+ gArmPlatformTokenSpaceGuid.PcdCoreCount
+
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+
+ gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
+ gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
+ gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate
+
+[BuildOptions]
+ *_*_*_ASLCC_FLAGS = -DARMADA8K
diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.fdf.inc b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.fdf.inc
index 4eb1496..326da2e 100644
--- a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.fdf.inc
+++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.fdf.inc
@@ -14,3 +14,7 @@
# DTB
INF RuleOverride = DTB Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf
+
+!if $(ARCH) == AARCH64
+ INF RuleOverride = ACPITABLE Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf
+!endif
diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl
new file mode 100644
index 0000000..87cb93a
--- /dev/null
+++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl
@@ -0,0 +1,310 @@
+/** @file
+
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "IcuInterrupts.h"
+
+DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
+{
+ Scope (_SB)
+ {
+ Device (CPU0)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x000) // _UID: Unique ID
+ }
+ Device (CPU1)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x001) // _UID: Unique ID
+ }
+ Device (CPU2)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x100) // _UID: Unique ID
+ }
+ Device (CPU3)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x101) // _UID: Unique ID
+ }
+
+ Device (AHC0)
+ {
+ Name (_HID, "LNRO001E") // _HID: Hardware ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Name (_CLS, Package (0x03) // _CLS: Class Code
+ {
+ 0x01,
+ 0x06,
+ 0x01
+ })
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xF2540000, // Address Base (MMIO)
+ 0x00002000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_CP0_SATA_H0
+ }
+ })
+ }
+
+ Device (AHC1)
+ {
+ Name (_HID, "LNRO001E") // _HID: Hardware ID
+ Name (_UID, 0x01) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Name (_CLS, Package (0x03) // _CLS: Class Code
+ {
+ 0x01,
+ 0x06,
+ 0x01
+ })
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xF4540000, // Address Base (MMIO)
+ 0x00002000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_CP1_SATA_H0
+ }
+ })
+ }
+
+ Device (XHC0)
+ {
+ Name (_HID, "PNP0D10") // _HID: Hardware ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xF2500000, // Address Base (MMIO)
+ 0x00004000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_CP0_USB_H0
+ }
+ })
+ }
+
+ Device (XHC1)
+ {
+ Name (_HID, "PNP0D10") // _HID: Hardware ID
+ Name (_UID, 0x01) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xF2510000, // Address Base (MMIO)
+ 0x00004000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_CP0_USB_H1
+ }
+ })
+ }
+
+ Device (XHC2)
+ {
+ Name (_HID, "PNP0D10") // _HID: Hardware ID
+ Name (_UID, 0x02) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xF4500000, // Address Base (MMIO)
+ 0x00004000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_CP1_USB_H0
+ }
+ })
+ }
+
+ Device (COM1)
+ {
+ Name (_HID, "HISI0031") // _HID: Hardware ID
+ Name (_CID, "8250dw") // _CID: Compatible ID
+ Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ FixedPcdGet64(PcdSerialRegisterBase), // Address Base
+ 0x00000100, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 51
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "clock-frequency", FixedPcdGet32 (PcdSerialClockRate) },
+ Package () { "reg-io-width", 1 },
+ Package () { "reg-shift", 2 },
+ }
+ })
+ }
+
+ Device (PP20)
+ {
+ Name (_HID, "MRVL0110") // _HID: Hardware ID
+ Name (_CCA, 0x01) // Cache-coherent controller
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000)
+ Memory32Fixed (ReadWrite, 0xf2129000 , 0xb000)
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "clock-frequency", 333333333 },
+ }
+ })
+ Device (ETH0)
+ {
+ Name (_ADR, 0x0)
+ Name (_CRS, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_PP2_CP0_PORT0
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "port-id", 0 },
+ Package () { "gop-port-id", 0 },
+ Package () { "phy-mode", "10gbase-kr"},
+ }
+ })
+ }
+ }
+
+ Device (PP21)
+ {
+ Name (_HID, "MRVL0110") // _HID: Hardware ID
+ Name (_CCA, 0x01) // Cache-coherent controller
+ Name (_UID, 0x01) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000)
+ Memory32Fixed (ReadWrite, 0xf4129000 , 0xb000)
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "clock-frequency", 333333333 },
+ }
+ })
+ Device (ETH0)
+ {
+ Name (_ADR, 0x0)
+ Name (_CRS, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_PP2_CP1_PORT0
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "port-id", 0 },
+ Package () { "gop-port-id", 0 },
+ Package () { "phy-mode", "10gbase-kr"},
+ }
+ })
+ }
+ Device (ETH1)
+ {
+ Name (_ADR, 0x0)
+ Name (_CRS, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_PP2_CP1_PORT1
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "port-id", 1 },
+ Package () { "gop-port-id", 2 },
+ Package () { "phy-mode", "sgmii"},
+ }
+ })
+ }
+ }
+
+ Device (RNG0)
+ {
+ Name (_HID, "PRP0001") // _HID: Hardware ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0xF2760000, 0x7D)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared)
+ {
+ CP_GIC_SPI_CP0_EIP_RNG0
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "compatible", "inside-secure,safexcel-eip76" },
+ }
+ })
+ }
+
+ Device (RNG1)
+ {
+ Name (_HID, "PRP0001") // _HID: Hardware ID
+ Name (_UID, 0x01) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0xF4760000, 0x7D)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared)
+ {
+ CP_GIC_SPI_CP1_EIP_RNG0
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "compatible", "inside-secure,safexcel-eip76" },
+ }
+ })
+ }
+ }
+}
--
2.7.4
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [platforms: PATCH v2 0/9] Armada7k8k DT/ACPI support
2018-08-07 8:58 [platforms: PATCH v2 0/9] Armada7k8k DT/ACPI support Marcin Wojtas
` (8 preceding siblings ...)
2018-08-07 8:58 ` [platforms: PATCH v2 9/9] Marvell/Armada80x0McBin: " Marcin Wojtas
@ 2018-08-07 9:18 ` Ard Biesheuvel
2018-08-07 11:28 ` Marcin Wojtas
9 siblings, 1 reply; 14+ messages in thread
From: Ard Biesheuvel @ 2018-08-07 9:18 UTC (permalink / raw)
To: Marcin Wojtas
Cc: edk2-devel@lists.01.org, Leif Lindholm, Nadav Haklai,
Jan Dąbroś, Grzegorz Jaszczyk
On 7 August 2018 at 10:58, Marcin Wojtas <mw@semihalf.com> wrote:
> Hi,
>
> The second version of the patchset modifies AcpiTables
> directory structure in order to avoid passing relative
> paths in the boards' .inf files.
>
> The patches are available in the github:
> https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/dt-acpi-upstream-r20180807
>
> I'm looking forward to review and any comments/remarks.
>
> Best regards,
> Marcin
>
> Marcin Wojtas (9):
> Marvell/Armada7k8k: Import device tree
> Marvell/Armada7k8k: Enable including additional DXE FV components
> Marvell/Armada70x0Db: Enable device tree support
> Marvell/Armada80x0Db: Enable device tree support
> Marvell/Armada80x0McBin: Enable device tree support
> Marvell/Armada7k8k: Add common ACPI tables
> Marvell/Armada70x0Db: Enable ACPI support
> Marvell/Armada80x0Db: Enable ACPI support
> Marvell/Armada80x0McBin: Enable ACPI support
>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Pushed as 02daa58c21f8..89c6c77b3d91
> Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 18 +
> Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc | 7 +
> Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc | 7 +
> Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc | 7 +
> Silicon/Marvell/Armada7k8k/Armada7k8k.fdf | 22 +
> Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db.inf | 61 +++
> Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf | 61 +++
> Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf | 61 +++
> Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf | 28 ++
> Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf | 28 ++
> Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf | 28 ++
> Silicon/Marvell/Armada7k8k/AcpiTables/AcpiHeader.h | 45 ++
> Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h | 42 ++
> Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf.inc | 21 +
> Platform/Marvell/Armada80x0Db/Armada80x0Db.fdf.inc | 21 +
> Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.fdf.inc | 20 +
> Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl | 229 +++++++++
> Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl | 330 +++++++++++++
> Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl | 310 ++++++++++++
> Silicon/Marvell/Armada7k8k/AcpiTables/Fadt.aslc | 86 ++++
> Silicon/Marvell/Armada7k8k/AcpiTables/Gtdt.aslc | 64 +++
> Silicon/Marvell/Armada7k8k/AcpiTables/Madt.aslc | 139 ++++++
> Silicon/Marvell/Armada7k8k/AcpiTables/Pptt.aslc | 216 +++++++++
> Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc | 53 ++
> Silicon/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi | 16 +
> Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts | 267 +++++++++++
> Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi | 16 +
> Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi | 64 +++
> Silicon/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi | 26 +
> Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts | 336 +++++++++++++
> Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts | 374 +++++++++++++++
> Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi | 25 +
> Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi | 108 +++++
> Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi | 31 ++
> Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi | 43 ++
> Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi | 264 ++++++++++
> Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi | 10 +
> Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi | 504 ++++++++++++++++++++
> Silicon/Marvell/Documentation/PortingGuide.txt | 22 +
> 39 files changed, 4010 insertions(+)
> create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db.inf
> create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf
> create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf
> create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf
> create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf
> create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf
> create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/AcpiHeader.h
> create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h
> create mode 100644 Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf.inc
> create mode 100644 Platform/Marvell/Armada80x0Db/Armada80x0Db.fdf.inc
> create mode 100644 Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.fdf.inc
> create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl
> create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl
> create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl
> create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Fadt.aslc
> create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Gtdt.aslc
> create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Madt.aslc
> create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Pptt.aslc
> create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc
> create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi
> create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts
> create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi
> create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi
> create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi
> create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts
> create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts
> create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi
> create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi
> create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi
> create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi
> create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi
> create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi
> create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi
>
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [platforms: PATCH v2 0/9] Armada7k8k DT/ACPI support
2018-08-07 9:18 ` [platforms: PATCH v2 0/9] Armada7k8k DT/ACPI support Ard Biesheuvel
@ 2018-08-07 11:28 ` Marcin Wojtas
2018-08-07 21:48 ` Mark Kettenis
0 siblings, 1 reply; 14+ messages in thread
From: Marcin Wojtas @ 2018-08-07 11:28 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: edk2-devel-01, Leif Lindholm, nadavh, jsd@semihalf.com,
Grzegorz Jaszczyk
wt., 7 sie 2018 o 11:18 Ard Biesheuvel <ard.biesheuvel@linaro.org> napisał(a):
>
> On 7 August 2018 at 10:58, Marcin Wojtas <mw@semihalf.com> wrote:
> > Hi,
> >
> > The second version of the patchset modifies AcpiTables
> > directory structure in order to avoid passing relative
> > paths in the boards' .inf files.
> >
> > The patches are available in the github:
> > https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/dt-acpi-upstream-r20180807
> >
> > I'm looking forward to review and any comments/remarks.
> >
> > Best regards,
> > Marcin
> >
> > Marcin Wojtas (9):
> > Marvell/Armada7k8k: Import device tree
> > Marvell/Armada7k8k: Enable including additional DXE FV components
> > Marvell/Armada70x0Db: Enable device tree support
> > Marvell/Armada80x0Db: Enable device tree support
> > Marvell/Armada80x0McBin: Enable device tree support
> > Marvell/Armada7k8k: Add common ACPI tables
> > Marvell/Armada70x0Db: Enable ACPI support
> > Marvell/Armada80x0Db: Enable ACPI support
> > Marvell/Armada80x0McBin: Enable ACPI support
> >
>
> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>
> Pushed as 02daa58c21f8..89c6c77b3d91
>
Thank you!
Marcin
>
> > Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 18 +
> > Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc | 7 +
> > Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc | 7 +
> > Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc | 7 +
> > Silicon/Marvell/Armada7k8k/Armada7k8k.fdf | 22 +
> > Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db.inf | 61 +++
> > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf | 61 +++
> > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf | 61 +++
> > Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf | 28 ++
> > Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf | 28 ++
> > Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf | 28 ++
> > Silicon/Marvell/Armada7k8k/AcpiTables/AcpiHeader.h | 45 ++
> > Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h | 42 ++
> > Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf.inc | 21 +
> > Platform/Marvell/Armada80x0Db/Armada80x0Db.fdf.inc | 21 +
> > Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.fdf.inc | 20 +
> > Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl | 229 +++++++++
> > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl | 330 +++++++++++++
> > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl | 310 ++++++++++++
> > Silicon/Marvell/Armada7k8k/AcpiTables/Fadt.aslc | 86 ++++
> > Silicon/Marvell/Armada7k8k/AcpiTables/Gtdt.aslc | 64 +++
> > Silicon/Marvell/Armada7k8k/AcpiTables/Madt.aslc | 139 ++++++
> > Silicon/Marvell/Armada7k8k/AcpiTables/Pptt.aslc | 216 +++++++++
> > Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc | 53 ++
> > Silicon/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi | 16 +
> > Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts | 267 +++++++++++
> > Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi | 16 +
> > Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi | 64 +++
> > Silicon/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi | 26 +
> > Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts | 336 +++++++++++++
> > Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts | 374 +++++++++++++++
> > Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi | 25 +
> > Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi | 108 +++++
> > Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi | 31 ++
> > Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi | 43 ++
> > Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi | 264 ++++++++++
> > Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi | 10 +
> > Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi | 504 ++++++++++++++++++++
> > Silicon/Marvell/Documentation/PortingGuide.txt | 22 +
> > 39 files changed, 4010 insertions(+)
> > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db.inf
> > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf
> > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf
> > create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf
> > create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf
> > create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf
> > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/AcpiHeader.h
> > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h
> > create mode 100644 Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf.inc
> > create mode 100644 Platform/Marvell/Armada80x0Db/Armada80x0Db.fdf.inc
> > create mode 100644 Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.fdf.inc
> > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl
> > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl
> > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl
> > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Fadt.aslc
> > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Gtdt.aslc
> > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Madt.aslc
> > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Pptt.aslc
> > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc
> > create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi
> > create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts
> > create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi
> > create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi
> > create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi
> > create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts
> > create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts
> > create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi
> > create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi
> > create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi
> > create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi
> > create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi
> > create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi
> > create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi
> >
> > --
> > 2.7.4
> >
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [platforms: PATCH v2 0/9] Armada7k8k DT/ACPI support
2018-08-07 11:28 ` Marcin Wojtas
@ 2018-08-07 21:48 ` Mark Kettenis
2018-08-07 23:03 ` Marcin Wojtas
0 siblings, 1 reply; 14+ messages in thread
From: Mark Kettenis @ 2018-08-07 21:48 UTC (permalink / raw)
To: mw; +Cc: ard.biesheuvel, nadavh, jaz, edk2-devel
> From: Marcin Wojtas <mw@semihalf.com>
> Date: Tue, 7 Aug 2018 13:28:19 +0200
>
> wt., 7 sie 2018 o 11:18 Ard Biesheuvel <ard.biesheuvel@linaro.org> napisał(a):
> >
> > On 7 August 2018 at 10:58, Marcin Wojtas <mw@semihalf.com> wrote:
> > > Hi,
> > >
> > > The second version of the patchset modifies AcpiTables
> > > directory structure in order to avoid passing relative
> > > paths in the boards' .inf files.
> > >
> > > The patches are available in the github:
> > > https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/dt-acpi-upstream-r20180807
> > >
> > > I'm looking forward to review and any comments/remarks.
> > >
> > > Best regards,
> > > Marcin
> > >
> > > Marcin Wojtas (9):
> > > Marvell/Armada7k8k: Import device tree
> > > Marvell/Armada7k8k: Enable including additional DXE FV components
> > > Marvell/Armada70x0Db: Enable device tree support
> > > Marvell/Armada80x0Db: Enable device tree support
> > > Marvell/Armada80x0McBin: Enable device tree support
> > > Marvell/Armada7k8k: Add common ACPI tables
> > > Marvell/Armada70x0Db: Enable ACPI support
> > > Marvell/Armada80x0Db: Enable ACPI support
> > > Marvell/Armada80x0McBin: Enable ACPI support
> > >
> >
> > Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> >
> > Pushed as 02daa58c21f8..89c6c77b3d91
> >
>
> Thank you!
> Marcin
Thank you Marcin!
My MACCHIATObin is now running OpenBSD/arm64 on firmware based on
unmodified mainline ATF and mainline EDK II.
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [platforms: PATCH v2 0/9] Armada7k8k DT/ACPI support
2018-08-07 21:48 ` Mark Kettenis
@ 2018-08-07 23:03 ` Marcin Wojtas
0 siblings, 0 replies; 14+ messages in thread
From: Marcin Wojtas @ 2018-08-07 23:03 UTC (permalink / raw)
To: mark.kettenis; +Cc: Ard Biesheuvel, nadavh, Grzegorz Jaszczyk, edk2-devel-01
Hi Mark,
wt., 7 sie 2018 o 23:48 Mark Kettenis <mark.kettenis@xs4all.nl> napisał(a):
>
> > From: Marcin Wojtas <mw@semihalf.com>
> > Date: Tue, 7 Aug 2018 13:28:19 +0200
> >
> > wt., 7 sie 2018 o 11:18 Ard Biesheuvel <ard.biesheuvel@linaro.org> napisał(a):
> > >
> > > On 7 August 2018 at 10:58, Marcin Wojtas <mw@semihalf.com> wrote:
> > > > Hi,
> > > >
> > > > The second version of the patchset modifies AcpiTables
> > > > directory structure in order to avoid passing relative
> > > > paths in the boards' .inf files.
> > > >
> > > > The patches are available in the github:
> > > > https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/dt-acpi-upstream-r20180807
> > > >
> > > > I'm looking forward to review and any comments/remarks.
> > > >
> > > > Best regards,
> > > > Marcin
> > > >
> > > > Marcin Wojtas (9):
> > > > Marvell/Armada7k8k: Import device tree
> > > > Marvell/Armada7k8k: Enable including additional DXE FV components
> > > > Marvell/Armada70x0Db: Enable device tree support
> > > > Marvell/Armada80x0Db: Enable device tree support
> > > > Marvell/Armada80x0McBin: Enable device tree support
> > > > Marvell/Armada7k8k: Add common ACPI tables
> > > > Marvell/Armada70x0Db: Enable ACPI support
> > > > Marvell/Armada80x0Db: Enable ACPI support
> > > > Marvell/Armada80x0McBin: Enable ACPI support
> > > >
> > >
> > > Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> > >
> > > Pushed as 02daa58c21f8..89c6c77b3d91
> > >
> >
> > Thank you!
> > Marcin
>
> Thank you Marcin!
>
> My MACCHIATObin is now running OpenBSD/arm64 on firmware based on
> unmodified mainline ATF and mainline EDK II.
I'm pleased to read that. Last bits left and the mainline
edk2-platforms support will be complete.
Best regards,
Marcin
^ permalink raw reply [flat|nested] 14+ messages in thread