From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::541; helo=mail-pg1-x541.google.com; envelope-from=haojian.zhuang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pg1-x541.google.com (mail-pg1-x541.google.com [IPv6:2607:f8b0:4864:20::541]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 638C2210F93C7 for ; Tue, 21 Aug 2018 04:35:46 -0700 (PDT) Received: by mail-pg1-x541.google.com with SMTP id y5-v6so8334956pgv.1 for ; Tue, 21 Aug 2018 04:35:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uUeDOtQa5Kc9rRNpKHYoTRQQeSXhnL5skuNDeKRgllk=; b=aWAISS7Ay3o+xh3ykjqxYlRBI+mN8D7tkgt8JRGijBU38zDvmIg9StAbDOFMwlCBFq APb5rrOOA6SBqTtiZDynSE+CP6w704J+tQLT94qoDupaW2rl2Hhnfu1XLQMdYqL8HHnn GoHKQTwNonesm09G99mQf3dIaON9kOZHjvUzw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uUeDOtQa5Kc9rRNpKHYoTRQQeSXhnL5skuNDeKRgllk=; b=fybzJonAdFFofX0SJoukO/tNCXhfv3u7Zgr5vgWMwPDCY/pVVEw3SZx5I1WIR3jw/O UNT8U1AFiArrsdwiw3A/r4DRN4rRATyQ4VQFPgupDKP34K/tMh6b0nHebPowV87GJiDG IbsrN5VFGpc52BShAzA0EFgaWBs2FTO8La12IuHFNbEnlQZKeBx/YQ6n+yaRzPu8468j ngzlJwG6Pg4IIp+YjpI8ybqRweT+X7HjgyQgKTtYrRWon0VCfm6vsWvx1/iGEgKAuNZ/ dLTea72gd2cc470MVD34Wky5F6tCJto2UrwHqqv8XatDi0hbpeFyyyotTVOq8ZSx+WON gNJA== X-Gm-Message-State: AOUpUlG6altp4iO8DkrNd4m7kyI9iyerfZAgSw9nVq3oUJqqPuSdOxw+ TA1gaVHQe3L2mfijys0x8pP/BIekjdw0eg== X-Google-Smtp-Source: AA+uWPxCHG6sfDGg1cMb94EFA/Zn6vun7X+MiYY6BwImsVj17+R6+vFSNrHfUe1zrbs1ZN15Vxc4VQ== X-Received: by 2002:a63:b00f:: with SMTP id h15-v6mr47559424pgf.442.1534851345786; Tue, 21 Aug 2018 04:35:45 -0700 (PDT) Received: from localhost.localdomain ([64.64.108.219]) by smtp.gmail.com with ESMTPSA id s14-v6sm21678388pfj.105.2018.08.21.04.35.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 21 Aug 2018 04:35:44 -0700 (PDT) From: Haojian Zhuang To: edk2-devel@lists.01.org Date: Tue, 21 Aug 2018 19:35:35 +0800 Message-Id: <1534851338-21419-2-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1534851338-21419-1-git-send-email-haojian.zhuang@linaro.org> References: <1534851338-21419-1-git-send-email-haojian.zhuang@linaro.org> Subject: [PATCH edk-platforms v1 1/4] Platform/HiKey: add more register definitions X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 21 Aug 2018 11:35:46 -0000 These register definitions are used in USB device driver. Cc: Leif Lindholm Cc: Ard Biesheuvel Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Haojian Zhuang --- Silicon/Hisilicon/Hi6220/Include/Hi6220.h | 53 ++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/Silicon/Hisilicon/Hi6220/Include/Hi6220.h b/Silicon/Hisilicon/Hi6220/Include/Hi6220.h index 9b2508955772..ff0ba691bb61 100644 --- a/Silicon/Hisilicon/Hi6220/Include/Hi6220.h +++ b/Silicon/Hisilicon/Hi6220/Include/Hi6220.h @@ -29,6 +29,23 @@ #define IOCG_BASE 0xF7010800 #define IOCG_084_REG (IOCG_BASE + 0x150) +#define GPIO4_CTRL_BASE 0xF7020000 +#define GPIO5_CTRL_BASE 0xF7021000 +#define GPIO6_CTRL_BASE 0xF7022000 +#define GPIO7_CTRL_BASE 0xF7023000 +#define GPIO8_CTRL_BASE 0xF7024000 +#define GPIO9_CTRL_BASE 0xF7025000 +#define GPIO10_CTRL_BASE 0xF7026000 +#define GPIO11_CTRL_BASE 0xF7027000 +#define GPIO12_CTRL_BASE 0xF7028000 +#define GPIO13_CTRL_BASE 0xF7029000 +#define GPIO14_CTRL_BASE 0xF702A000 +#define GPIO15_CTRL_BASE 0xF702B000 +#define GPIO16_CTRL_BASE 0xF702C000 +#define GPIO17_CTRL_BASE 0xF702D000 +#define GPIO18_CTRL_BASE 0xF702E000 +#define GPIO19_CTRL_BASE 0xF702F000 + #define PERI_CTRL_BASE 0xF7030000 #define SC_PERIPH_CTRL4 0x00C #define CTRL4_FPGA_EXT_PHY_SEL BIT3 @@ -51,18 +68,47 @@ #define SC_PERIPH_CTRL8 0x018 #define SC_PERIPH_CLKEN0 0x200 + +#define PERIPH_CLKEN0_USBOTG BIT4 + #define SC_PERIPH_CLKDIS0 0x204 #define SC_PERIPH_CLKSTAT0 0x208 +#define SC_PERIPH_CLKEN3 0x230 #define SC_PERIPH_RSTEN0 0x300 #define SC_PERIPH_RSTDIS0 0x304 #define SC_PERIPH_RSTSTAT0 0x308 +#define SC_PERIPH_RSTEN3 0x330 +#define SC_PERIPH_RSTDIS3 0x334 +#define SC_PERIPH_RSTSTAT3 0x338 #define RST0_USBOTG_BUS BIT4 #define RST0_POR_PICOPHY BIT5 #define RST0_USBOTG BIT6 #define RST0_USBOTG_32K BIT7 +/* SC_PERIPH_RSTEN0/RSTDIS0/RSTSTAT0 */ +#define PERIPH_RST0_MMC2 (1 << 2) + +/* SC_PERIPH_RSTEN3/RSTDIS3/RSTSTAT3 */ +#define PERIPH_RST3_CSSYS (1 << 0) +#define PERIPH_RST3_I2C0 (1 << 1) +#define PERIPH_RST3_I2C1 (1 << 2) +#define PERIPH_RST3_I2C2 (1 << 3) +#define PERIPH_RST3_I2C3 (1 << 4) +#define PERIPH_RST3_UART1 (1 << 5) +#define PERIPH_RST3_UART2 (1 << 6) +#define PERIPH_RST3_UART3 (1 << 7) +#define PERIPH_RST3_UART4 (1 << 8) +#define PERIPH_RST3_SSP (1 << 9) +#define PERIPH_RST3_PWM (1 << 10) +#define PERIPH_RST3_BLPWM (1 << 11) +#define PERIPH_RST3_TSENSOR (1 << 12) +#define PERIPH_RST3_DAPB (1 << 18) +#define PERIPH_RST3_HKADC (1 << 19) +#define PERIPH_RST3_CODEC_SSI (1 << 20) +#define PERIPH_RST3_PMUSSI1 (1 << 22) + #define EYE_PATTERN_PARA 0x7053348c #define MDDRC_AXI_BASE 0xF7120000 @@ -80,4 +126,11 @@ #define PMUSSI_BASE 0xF8000000 +#define PMUSSI_REG(x) (PMUSSI_BASE + ((x) << 2)) + +#define GPIO0_CTRL_BASE 0xF8011000 +#define GPIO1_CTRL_BASE 0xF8012000 +#define GPIO2_CTRL_BASE 0xF8013000 +#define GPIO3_CTRL_BASE 0xF8014000 + #endif /* __HI6220_H__ */ -- 2.7.4