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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id q16-v6sm1197337ljj.68.2018.09.07.02.10.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 07 Sep 2018 02:10:58 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Cc: feng.tian@intel.com, michael.d.kinney@intel.com, liming.gao@intel.com, leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, mw@semihalf.com, jsd@semihalf.com, tm@semihalf.com Date: Fri, 7 Sep 2018 11:10:13 +0200 Message-Id: <1536311416-2751-2-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1536311416-2751-1-git-send-email-mw@semihalf.com> References: <1536311416-2751-1-git-send-email-mw@semihalf.com> Subject: [PATCH v2 1/4] MdeModulePkg/SdMmcPciHcDxe: Fix HS200 operation X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 07 Sep 2018 09:11:01 -0000 When switching to any of high speed modes (HS, HS200, HS400) there is need to set HS_ENABLE bit in Host Control 1 register which allow Host Controller to output CMD and DAT lines on both edges of clock. In Linux it is done after switching bus width in sdhci_set_ios(). Also according to JESD84-B50-1 chapter 6.6.4 "HS200 timing mode selection" (documentation about eMMC4.5 standard) there is no need to disable clock when switching to HS200. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 5 ++++ MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 30 +++----------------- 2 files changed, 9 insertions(+), 26 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h index e389d52..e3fadb5 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h @@ -63,6 +63,11 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. #define SD_MMC_HC_CTRL_VER 0xFE // +// SD Host Control 1 Register bits description +// +#define SD_MMC_HC_HOST_CTRL1_HS_ENABLE (1 << 2) + +// // The transfer modes supported by SD Host Controller // Simplified Spec 3.0 Table 1-2 // diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c index c5fd214..b3903b4 100755 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c @@ -816,8 +816,8 @@ EmmcSwitchToHS200 ( { EFI_STATUS Status; UINT8 HsTiming; + UINT8 HostCtrl1; UINT8 HostCtrl2; - UINT16 ClockCtrl; if ((BusWidth != 4) && (BusWidth != 8)) { return EFI_INVALID_PARAMETER; @@ -828,12 +828,10 @@ EmmcSwitchToHS200 ( return Status; } // - // Set to HS200/SDR104 timing - // - // - // Stop bus clock at first + // Set to High Speed timing // - Status = SdMmcHcStopClock (PciIo, Slot); + HostCtrl1 = SD_MMC_HC_HOST_CTRL1_HS_ENABLE; + Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1); if (EFI_ERROR (Status)) { return Status; } @@ -853,26 +851,6 @@ EmmcSwitchToHS200 ( if (EFI_ERROR (Status)) { return Status; } - // - // Wait Internal Clock Stable in the Clock Control register to be 1 before set SD Clock Enable bit - // - Status = SdMmcHcWaitMmioSet ( - PciIo, - Slot, - SD_MMC_HC_CLOCK_CTRL, - sizeof (ClockCtrl), - BIT1, - BIT1, - SD_MMC_HC_GENERIC_TIMEOUT - ); - if (EFI_ERROR (Status)) { - return Status; - } - // - // Set SD Clock Enable in the Clock Control register to 1 - // - ClockCtrl = BIT2; - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl); HsTiming = 2; Status = EmmcSwitchClockFreq (PciIo, PassThru, Slot, Rca, HsTiming, ClockFreq); -- 2.7.4